diff --git a/src/amd/compiler/aco_instruction_selection.cpp b/src/amd/compiler/aco_instruction_selection.cpp
index 55d44c64c9e..8181b215858 100644
--- a/src/amd/compiler/aco_instruction_selection.cpp
+++ b/src/amd/compiler/aco_instruction_selection.cpp
@@ -11484,7 +11484,7 @@ create_fs_exports(isel_context* ctx)
        * require MRT0 to be written. Just copy MRT1 into MRT0. Skipping MRT1 exports seems to be
        * fine.
        */
-      if (ctx->options->key.ps.mrt0_is_dual_src && !ctx->outputs.mask[FRAG_RESULT_DATA0] &&
+      if (ctx->options->key.ps.epilog.mrt0_is_dual_src && !ctx->outputs.mask[FRAG_RESULT_DATA0] &&
           ctx->outputs.mask[FRAG_RESULT_DATA1]) {
          u_foreach_bit (j, ctx->outputs.mask[FRAG_RESULT_DATA1]) {
             ctx->outputs.temps[FRAG_RESULT_DATA0 * 4u + j] =
@@ -11506,10 +11506,11 @@ create_fs_exports(isel_context* ctx)
 
          out.slot = compacted_mrt_index;
          out.write_mask = ctx->outputs.mask[i];
-         out.col_format = (ctx->options->key.ps.spi_shader_col_format >> (4 * idx)) & 0xf;
-         out.is_int8 = (ctx->options->key.ps.color_is_int8 >> idx) & 1;
-         out.is_int10 = (ctx->options->key.ps.color_is_int10 >> idx) & 1;
-         out.enable_mrt_output_nan_fixup = (ctx->options->key.ps.enable_mrt_output_nan_fixup >> idx) & 1;
+         out.col_format = (ctx->options->key.ps.epilog.spi_shader_col_format >> (4 * idx)) & 0xf;
+         out.is_int8 = (ctx->options->key.ps.epilog.color_is_int8 >> idx) & 1;
+         out.is_int10 = (ctx->options->key.ps.epilog.color_is_int10 >> idx) & 1;
+         out.enable_mrt_output_nan_fixup =
+            (ctx->options->key.ps.epilog.enable_mrt_output_nan_fixup >> idx) & 1;
 
          for (unsigned c = 0; c < 4; ++c) {
             if (out.write_mask & (1 << c)) {
@@ -11526,7 +11527,7 @@ create_fs_exports(isel_context* ctx)
       }
 
       if (exported) {
-         if (ctx->options->gfx_level >= GFX11 && ctx->options->key.ps.mrt0_is_dual_src) {
+         if (ctx->options->gfx_level >= GFX11 && ctx->options->key.ps.epilog.mrt0_is_dual_src) {
             struct aco_export_mrt* mrt0 = mrts[0].enabled_channels ? &mrts[0] : NULL;
             struct aco_export_mrt* mrt1 = mrts[1].enabled_channels ? &mrts[1] : NULL;
             create_fs_dual_src_export_gfx11(ctx, mrt0, mrt1);
diff --git a/src/amd/compiler/aco_shader_info.h b/src/amd/compiler/aco_shader_info.h
index bc62784367b..cec8fd7c015 100644
--- a/src/amd/compiler/aco_shader_info.h
+++ b/src/amd/compiler/aco_shader_info.h
@@ -60,17 +60,6 @@ struct aco_vs_prolog_key {
    gl_shader_stage next_stage;
 };
 
-struct aco_ps_epilog_key {
-   uint32_t spi_shader_col_format;
-
-   /* Bitmasks, each bit represents one of the 8 MRTs. */
-   uint8_t color_is_int8;
-   uint8_t color_is_int10;
-   uint8_t enable_mrt_output_nan_fixup;
-
-   bool mrt0_is_dual_src;
-};
-
 struct aco_vp_output_info {
    uint8_t vs_output_param_offset[VARYING_SLOT_MAX];
    uint8_t clip_dist_mask;
@@ -138,6 +127,17 @@ enum aco_compiler_debug_level {
    ACO_COMPILER_DEBUG_LEVEL_ERROR,
 };
 
+struct aco_ps_epilog_key {
+   uint32_t spi_shader_col_format;
+
+   /* Bitmasks, each bit represents one of the 8 MRTs. */
+   uint8_t color_is_int8;
+   uint8_t color_is_int10;
+   uint8_t enable_mrt_output_nan_fixup;
+
+   bool mrt0_is_dual_src;
+};
+
 struct aco_stage_input {
    uint32_t optimisations_disabled : 1;
    uint32_t image_2d_view_of_3d : 1;
@@ -156,14 +156,10 @@ struct aco_stage_input {
    } tcs;
 
    struct {
-      uint32_t spi_shader_col_format;
-      uint8_t color_is_int8;
-      uint8_t color_is_int10;
-      uint8_t enable_mrt_output_nan_fixup;
+      struct aco_ps_epilog_key epilog;
 
       /* Used to export alpha through MRTZ for alpha-to-coverage (GFX11+). */
       bool alpha_to_coverage_via_mrtz;
-      bool mrt0_is_dual_src;
    } ps;
 };
 
diff --git a/src/amd/vulkan/radv_aco_shader_info.h b/src/amd/vulkan/radv_aco_shader_info.h
index cb70f7233e5..e090595557e 100644
--- a/src/amd/vulkan/radv_aco_shader_info.h
+++ b/src/amd/vulkan/radv_aco_shader_info.h
@@ -124,6 +124,7 @@ static inline void
 radv_aco_convert_pipe_key(struct aco_stage_input *aco_info,
                           const struct radv_pipeline_key *radv)
 {
+   radv_aco_convert_ps_epilog_key(&aco_info->ps.epilog, &radv->ps.epilog);
    ASSIGN_FIELD(optimisations_disabled);
    ASSIGN_FIELD(image_2d_view_of_3d);
    ASSIGN_FIELD(vs.instance_rate_inputs);
@@ -134,12 +135,7 @@ radv_aco_convert_pipe_key(struct aco_stage_input *aco_info,
    ASSIGN_FIELD_CP(vs.vertex_attribute_strides);
    ASSIGN_FIELD_CP(vs.vertex_binding_align);
    ASSIGN_FIELD(tcs.tess_input_vertices);
-   ASSIGN_FIELD(ps.spi_shader_col_format);
-   ASSIGN_FIELD(ps.color_is_int8);
-   ASSIGN_FIELD(ps.color_is_int10);
-   ASSIGN_FIELD(ps.enable_mrt_output_nan_fixup);
    ASSIGN_FIELD(ps.alpha_to_coverage_via_mrtz);
-   ASSIGN_FIELD(ps.mrt0_is_dual_src);
 }
 
 static inline void
diff --git a/src/amd/vulkan/radv_nir_to_llvm.c b/src/amd/vulkan/radv_nir_to_llvm.c
index 03638630cf8..ec608fdab96 100644
--- a/src/amd/vulkan/radv_nir_to_llvm.c
+++ b/src/amd/vulkan/radv_nir_to_llvm.c
@@ -567,10 +567,12 @@ si_llvm_init_export_args(struct radv_shader_context *ctx, LLVMValueRef *values,
 
    bool is_16bit = ac_get_type_size(LLVMTypeOf(values[0])) == 2;
    if (ctx->stage == MESA_SHADER_FRAGMENT) {
-      unsigned col_format = (ctx->options->key.ps.spi_shader_col_format >> (4 * index)) & 0xf;
-      bool is_int8 = (ctx->options->key.ps.color_is_int8 >> index) & 1;
-      bool is_int10 = (ctx->options->key.ps.color_is_int10 >> index) & 1;
-      bool enable_mrt_output_nan_fixup = (ctx->options->key.ps.enable_mrt_output_nan_fixup >> index) & 1;
+      unsigned col_format =
+         (ctx->options->key.ps.epilog.spi_shader_col_format >> (4 * index)) & 0xf;
+      bool is_int8 = (ctx->options->key.ps.epilog.color_is_int8 >> index) & 1;
+      bool is_int10 = (ctx->options->key.ps.epilog.color_is_int10 >> index) & 1;
+      bool enable_mrt_output_nan_fixup =
+         (ctx->options->key.ps.epilog.enable_mrt_output_nan_fixup >> index) & 1;
 
       LLVMValueRef (*packf)(struct ac_llvm_context * ctx, LLVMValueRef args[2]) = NULL;
       LLVMValueRef (*packi)(struct ac_llvm_context * ctx, LLVMValueRef args[2], unsigned bits,
@@ -937,7 +939,7 @@ si_export_mrt_color(struct radv_shader_context *ctx, LLVMValueRef *color, unsign
 {
    unsigned mrt_target = V_008DFC_SQ_EXP_MRT + target;
 
-   if (ctx->options->gfx_level >= GFX11 && ctx->options->key.ps.mrt0_is_dual_src &&
+   if (ctx->options->gfx_level >= GFX11 && ctx->options->key.ps.epilog.mrt0_is_dual_src &&
        (target == 0 || target == 1)) {
       mrt_target += 21;
    }
@@ -1006,7 +1008,7 @@ handle_fs_outputs_post(struct radv_shader_context *ctx)
       color_args[last].valid_mask = 1; /* whether the EXEC mask is valid */
       color_args[last].done = 1;       /* DONE bit */
 
-      if (ctx->options->gfx_level >= GFX11 && ctx->options->key.ps.mrt0_is_dual_src) {
+      if (ctx->options->gfx_level >= GFX11 && ctx->options->key.ps.epilog.mrt0_is_dual_src) {
          ac_build_dual_src_blend_swizzle(&ctx->ac, &color_args[0], &color_args[1]);
       }
    }
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 212370616ee..2de3f2376d8 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -2215,12 +2215,12 @@ radv_remove_color_exports(const struct radv_pipeline_key *pipeline_key, nir_shad
       if (idx < 0)
          continue;
 
-      unsigned col_format = (pipeline_key->ps.spi_shader_col_format >> (4 * idx)) & 0xf;
+      unsigned col_format = (pipeline_key->ps.epilog.spi_shader_col_format >> (4 * idx)) & 0xf;
       unsigned cb_target_mask = (pipeline_key->ps.cb_target_mask >> (4 * idx)) & 0xf;
 
       if (col_format == V_028714_SPI_SHADER_ZERO ||
           (col_format == V_028714_SPI_SHADER_32_R && !cb_target_mask &&
-           !pipeline_key->ps.mrt0_is_dual_src)) {
+           !pipeline_key->ps.epilog.mrt0_is_dual_src)) {
          /* Remove the color export if it's unused or in presence of holes. */
          nir->info.outputs_written &= ~BITFIELD64_BIT(var->data.location);
          var->data.location = 0;
@@ -2750,12 +2750,12 @@ radv_generate_graphics_pipeline_key(const struct radv_graphics_pipeline *pipelin
       }
    }
 
-   key.ps.spi_shader_col_format = blend->spi_shader_col_format;
+   key.ps.epilog.spi_shader_col_format = blend->spi_shader_col_format;
    key.ps.cb_target_mask = blend->cb_target_mask;
-   key.ps.mrt0_is_dual_src = blend->mrt0_is_dual_src;
+   key.ps.epilog.mrt0_is_dual_src = blend->mrt0_is_dual_src;
    if (device->physical_device->rad_info.gfx_level < GFX8) {
-      key.ps.color_is_int8 = blend->col_format_is_int8;
-      key.ps.color_is_int10 = blend->col_format_is_int10;
+      key.ps.epilog.color_is_int8 = blend->col_format_is_int8;
+      key.ps.epilog.color_is_int10 = blend->col_format_is_int10;
    }
    if (device->physical_device->rad_info.gfx_level >= GFX11 && state->ms) {
       key.ps.alpha_to_coverage_via_mrtz = state->ms->alpha_to_coverage_enable;
@@ -2774,8 +2774,7 @@ radv_generate_graphics_pipeline_key(const struct radv_graphics_pipeline *pipelin
       key.ps.lower_discard_to_demote = true;
 
    if (device->instance->enable_mrt_output_nan_fixup)
-      key.ps.enable_mrt_output_nan_fixup = blend->col_format_is_float32;
-
+      key.ps.epilog.enable_mrt_output_nan_fixup = blend->col_format_is_float32;
 
    key.ps.force_vrs_enabled = device->force_vrs_enabled;
 
@@ -3752,15 +3751,7 @@ radv_pipeline_create_ps_epilog(struct radv_graphics_pipeline *pipeline,
 
    if (pipeline->base.shaders[MESA_SHADER_FRAGMENT] &&
        pipeline->base.shaders[MESA_SHADER_FRAGMENT]->info.ps.has_epilog && !pipeline->ps_epilog) {
-      struct radv_ps_epilog_key epilog_key = {
-         .spi_shader_col_format = pipeline_key->ps.spi_shader_col_format,
-         .color_is_int8 = pipeline_key->ps.color_is_int8,
-         .color_is_int10 = pipeline_key->ps.color_is_int10,
-         .enable_mrt_output_nan_fixup = pipeline_key->ps.enable_mrt_output_nan_fixup,
-         .mrt0_is_dual_src = pipeline_key->ps.mrt0_is_dual_src,
-      };
-
-      pipeline->ps_epilog = radv_create_ps_epilog(device, &epilog_key);
+      pipeline->ps_epilog = radv_create_ps_epilog(device, &pipeline_key->ps.epilog);
       if (!pipeline->ps_epilog)
          return false;
    }
@@ -5601,15 +5592,7 @@ radv_graphics_lib_pipeline_init(struct radv_graphics_lib_pipeline *pipeline,
       struct radv_pipeline_key key =
          radv_generate_graphics_pipeline_key(&pipeline->base, pCreateInfo, state, &blend);
 
-      struct radv_ps_epilog_key epilog_key = {
-         .spi_shader_col_format = blend.spi_shader_col_format,
-         .color_is_int8 = blend.col_format_is_int8,
-         .color_is_int10 = blend.col_format_is_int10,
-         .enable_mrt_output_nan_fixup = key.ps.enable_mrt_output_nan_fixup,
-         .mrt0_is_dual_src = blend.mrt0_is_dual_src,
-      };
-
-      pipeline->base.ps_epilog = radv_create_ps_epilog(device, &epilog_key);
+      pipeline->base.ps_epilog = radv_create_ps_epilog(device, &key.ps.epilog);
       if (!pipeline->base.ps_epilog)
          goto fail_layout;
    }
diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
index 4bf5a551d84..598279abc0b 100644
--- a/src/amd/vulkan/radv_shader.c
+++ b/src/amd/vulkan/radv_shader.c
@@ -2370,7 +2370,7 @@ radv_fill_nir_compiler_options(struct radv_nir_compiler_options *options,
    options->address32_hi = device->physical_device->rad_info.address32_hi;
    options->has_ls_vgpr_init_bug = device->physical_device->rad_info.has_ls_vgpr_init_bug;
    options->enable_mrt_output_nan_fixup =
-      !is_meta_shader && options->key.ps.enable_mrt_output_nan_fixup;
+      !is_meta_shader && options->key.ps.epilog.enable_mrt_output_nan_fixup;
 }
 
 static struct radv_shader *
diff --git a/src/amd/vulkan/radv_shader.h b/src/amd/vulkan/radv_shader.h
index b21332dec2a..1723ba4bd36 100644
--- a/src/amd/vulkan/radv_shader.h
+++ b/src/amd/vulkan/radv_shader.h
@@ -52,6 +52,17 @@ struct radv_shader_args;
 struct radv_vs_input_state;
 struct radv_shader_args;
 
+struct radv_ps_epilog_key {
+   uint32_t spi_shader_col_format;
+
+   /* Bitmasks, each bit represents one of the 8 MRTs. */
+   uint8_t color_is_int8;
+   uint8_t color_is_int10;
+   uint8_t enable_mrt_output_nan_fixup;
+
+   bool mrt0_is_dual_src;
+};
+
 struct radv_pipeline_key {
    uint32_t has_multiview_view_index : 1;
    uint32_t optimisations_disabled : 1;
@@ -85,16 +96,13 @@ struct radv_pipeline_key {
    } tcs;
 
    struct {
-      uint32_t spi_shader_col_format;
-      uint8_t color_is_int8;
-      uint8_t color_is_int10;
+      struct radv_ps_epilog_key epilog;
+
       uint32_t cb_target_mask;
       uint8_t num_samples;
       bool sample_shading_enable;
-      bool mrt0_is_dual_src;
 
       bool lower_discard_to_demote;
-      uint8_t enable_mrt_output_nan_fixup;
       bool force_vrs_enabled;
 
       /* Used to export alpha through MRTZ for alpha-to-coverage (GFX11+). */
@@ -406,17 +414,6 @@ struct radv_vs_prolog_key {
    gl_shader_stage next_stage;
 };
 
-struct radv_ps_epilog_key {
-   uint32_t spi_shader_col_format;
-
-   /* Bitmasks, each bit represents one of the 8 MRTs. */
-   uint8_t color_is_int8;
-   uint8_t color_is_int10;
-   uint8_t enable_mrt_output_nan_fixup;
-
-   bool mrt0_is_dual_src;
-};
-
 enum radv_shader_binary_type { RADV_BINARY_TYPE_LEGACY, RADV_BINARY_TYPE_RTLD };
 
 struct radv_shader_binary {