fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2025-12-24 19:40:10 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

freedreno/a6xx: fix MSAA resolve hangs

Browse source 
Seems like RB_BLIT_SCISSOR needs to be aligned to (minimum?) tile size.

Fixes intermittent GPU hangs triggered by some of the three.js samples
on https://threejs.org/

Signed-off-by: Rob Clark <robdclark@chromium.org>
This commit is contained in:
Rob Clark 2019-07-24 13:31:13 -07:00
parent 73cc2dc084
commit 010d255656
1 changed files with 4 additions and 11 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

15
src/gallium/drivers/freedreno/a6xx/fd6_gmem.c
View file

@ -679,17 +679,10 @@ set_blit_scissor(struct fd_batch *batch, struct fd_ringbuffer *ring)
struct pipe_scissor_state blit_scissor;
struct pipe_framebuffer_state *pfb = &batch->framebuffer;
blit_scissor.minx = batch->max_scissor.minx;
blit_scissor.miny = batch->max_scissor.miny;
blit_scissor.maxx = MIN2(pfb->width, batch->max_scissor.maxx);
blit_scissor.maxy = MIN2(pfb->height, batch->max_scissor.maxy);
/* NOTE: blob switches to CP_BLIT instead of CP_EVENT_WRITE:BLIT for
* small render targets. But since we align pitch to binw I think
* we can get away avoiding GPU hangs a simpler way, by just rounding
* up the blit scissor:
*/
blit_scissor.maxx = MAX2(blit_scissor.maxx, batch->ctx->screen->gmem_alignw);
blit_scissor.minx = 0;
blit_scissor.miny = 0;
blit_scissor.maxx = align(pfb->width, batch->ctx->screen->gmem_alignw);
blit_scissor.maxy = align(pfb->height, batch->ctx->screen->gmem_alignh);
OUT_PKT4(ring, REG_A6XX_RB_BLIT_SCISSOR_TL, 2);
OUT_RING(ring,