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anv/drirc: add option to disable FCV optimization

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There are rendering issues with FCV on DG2 and Unreal engine 5.1,
patch adds option to disable fcv in drirc.

Cc: mesa-stable
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26169>
This commit is contained in:
Tapani Pälli 2023-11-13 09:56:25 +02:00 • committed by Marge Bot
parent aedf9113c4
commit 01046cd6ad
6 changed files with 28 additions and 11 deletions
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5
src/intel/vulkan/anv_device.c
View file

@ -78,6 +78,7 @@ static const driOptionDescription anv_dri_options[] = {
DRI_CONF_VK_KHR_PRESENT_WAIT(false)
DRI_CONF_VK_XWAYLAND_WAIT_READY(true)
DRI_CONF_ANV_ASSUME_FULL_SUBGROUPS(false)
DRI_CONF_ANV_DISABLE_FCV(false)
DRI_CONF_ANV_SAMPLE_MASK_OUT_OPENGL_BEHAVIOUR(false)
DRI_CONF_ANV_FP64_WORKAROUND_ENABLED(false)
DRI_CONF_ANV_GENERATED_INDIRECT_THRESHOLD(4)
@ -1376,6 +1377,8 @@ anv_physical_device_try_create(struct vk_instance *vk_instance,
device->flush_astc_ldr_void_extent_denorms =
device->has_astc_ldr && !device->emu_astc_ldr;
}
device->disable_fcv = intel_device_info_is_mtl(&device->info) ||
instance->disable_fcv;
result = anv_physical_device_init_heaps(device, fd);
if (result != VK_SUCCESS)
@ -1620,6 +1623,8 @@ anv_init_dri_options(struct anv_instance *instance)
instance->has_fake_sparse =
driQueryOptionb(&instance->dri_options, "fake_sparse");
instance->enable_tbimr = driQueryOptionb(&instance->dri_options, "intel_tbimr");
instance->disable_fcv =
driQueryOptionb(&instance->dri_options, "anv_disable_fcv");
}
VkResult anv_CreateInstance(

3
src/intel/vulkan/anv_image.c
View file

@ -830,7 +830,8 @@ add_aux_surface_if_supported(struct anv_device *device,
if (intel_needs_workaround(device->info, 1607794140)) {
/* FCV is permanently enabled on this HW. */
image->planes[plane].aux_usage = ISL_AUX_USAGE_FCV_CCS_E;
} else if (intel_device_info_is_dg2(device->info)) {
} else if (device->info->verx10 >= 125 &&
!device->physical->disable_fcv) {
/* FCV is enabled via 3DSTATE_3D_MODE. We'd expect plain CCS_E to
* perform better because it allows for non-zero fast clear colors,
* but we've run into regressions in several benchmarks (F1 22 and

4
src/intel/vulkan/anv_private.h
View file

@ -919,7 +919,8 @@ struct anv_physical_device {
bool flush_astc_ldr_void_extent_denorms;
/** True if ASTC LDR is supported via emulation */
bool emu_astc_ldr;
/* true if FCV optimization should be disabled. */
bool disable_fcv;
/**/
bool uses_ex_bso;
@ -1095,6 +1096,7 @@ struct anv_instance {
unsigned query_copy_with_shader_threshold;
unsigned force_vk_vendor;
bool has_fake_sparse;
bool disable_fcv;
/* HW workarounds */
bool no_16bit;

19
src/intel/vulkan/genX_init_state.c
View file

@ -149,21 +149,22 @@ genX(emit_slice_hashing_state)(struct anv_device *device,
ptr.SliceHashTableStatePointer = device->slice_hash.offset;
}
/* TODO: Figure out FCV support for other platforms
* Testing indicates that FCV is broken on MTL, but works fine on DG2.
* Let's disable FCV on MTL for now till we figure out what's wrong.
*
* Alternatively, it can be toggled off via drirc option 'anv_disable_fcv'.
*
* Ref: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9987
*/
anv_batch_emit(batch, GENX(3DSTATE_3D_MODE), mode) {
mode.SliceHashingTableEnable = true;
mode.SliceHashingTableEnableMask = true;
mode.CrossSliceHashingMode = (util_bitcount(ppipe_mask) > 1 ?
hashing32x32 : NormalMode);
mode.CrossSliceHashingModeMask = -1;
/* TODO: Figure out FCV support for other platforms
* Testing indicates that FCV is broken on MTL, but works fine on DG2.
* Let's disable FCV on MTL for now till we figure out what's wrong.
*
* Ref: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9987
*/
mode.FastClearOptimizationEnable = intel_device_info_is_dg2(device->info);
mode.FastClearOptimizationEnableMask =
intel_device_info_is_dg2(device->info);
mode.FastClearOptimizationEnable = !device->physical->disable_fcv;
mode.FastClearOptimizationEnableMask = !device->physical->disable_fcv;
}
#endif
}

4
src/util/00-mesa-defaults.conf
View file

@ -1180,6 +1180,10 @@ TODO: document the other workarounds.
<engine engine_name_match="mesa zink">
<option name="no_16bit" value="true" />
</engine>
<!-- Disable FCV optimization for Unreal Engine 5.1 workloads. -->
<engine engine_name_match="UnrealEngine5.1">
<option name="anv_disable_fcv" value="true" />
</engine>
</device>
<device driver="dzn">
<application name="DOOMEternal" executable="DOOMEternalx64vk.exe">

4
src/util/driconf.h
View file

@ -742,6 +742,10 @@
DRI_CONF_OPT_B(force_indirect_descriptors, def, \
"Use an indirection to access buffer/image/texture/sampler handles")
#define DRI_CONF_ANV_DISABLE_FCV(def) \
DRI_CONF_OPT_B(anv_disable_fcv, def, \
"Disable FCV optimization")
/**
* \brief DZN specific configuration options
*/