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r600g: set correct tiling flags in depth info

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The kernel currently overwrites the flags, but if we stopped doing that,
this would break badly.
(cherry picked from commit faa16dc456)

BTW, this may be an actual fix for very old kernels.
https://bugs.freedesktop.org/show_bug.cgi?id=42175

Conflicts:

	src/gallium/drivers/r600/evergreen_state.c
	src/gallium/drivers/r600/r600_state.c
This commit is contained in:
Marek Olšák 2011-10-26 14:51:30 +02:00
parent e4f88bcad3
commit 00c44de1a6
2 changed files with 13 additions and 9 deletions
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12
src/gallium/drivers/r600/evergreen_state.c
View file

@ -809,9 +809,7 @@ static void evergreen_db(struct r600_pipe_context *rctx, struct r600_pipe_state
struct r600_resource_texture *rtex;
struct r600_resource *rbuffer;
struct r600_surface *surf;
unsigned level;
unsigned pitch, slice, format, stencil_format;
unsigned offset;
unsigned level, pitch, slice, format, stencil_format, offset, array_mode;
if (state->zsbuf == NULL)
return;
@ -823,9 +821,13 @@ static void evergreen_db(struct r600_pipe_context *rctx, struct r600_pipe_state
rbuffer = &rtex->resource;
/* XXX quite sure for dx10+ hw don't need any offset hacks */
offset = r600_texture_get_offset((struct r600_resource_texture *)state->zsbuf->texture,
level, state->zsbuf->u.tex.first_layer);
/* XXX remove this once tiling is properly supported */
array_mode = rtex->array_mode[level] ? rtex->array_mode[level] :
V_028C70_ARRAY_1D_TILED_THIN1;
pitch = rtex->pitch_in_blocks[level] / 8 - 1;
slice = rtex->pitch_in_blocks[level] * surf->aligned_height / 64 - 1;
format = r600_translate_dbformat(state->zsbuf->texture->format);
@ -851,7 +853,7 @@ static void evergreen_db(struct r600_pipe_context *rctx, struct r600_pipe_state
S_028044_FORMAT(stencil_format), 0xFFFFFFFF, rbuffer->bo);
r600_pipe_state_add_reg(rstate, R_028040_DB_Z_INFO,
S_028040_ARRAY_MODE(rtex->array_mode[level]) | S_028040_FORMAT(format),
S_028040_ARRAY_MODE(array_mode) | S_028040_FORMAT(format),
0xFFFFFFFF, rbuffer->bo);
r600_pipe_state_add_reg(rstate, R_028058_DB_DEPTH_SIZE,
S_028058_PITCH_TILE_MAX(pitch),

10
src/gallium/drivers/r600/r600_state.c
View file

@ -886,9 +886,7 @@ static void r600_db(struct r600_pipe_context *rctx, struct r600_pipe_state *rsta
struct r600_resource_texture *rtex;
struct r600_resource *rbuffer;
struct r600_surface *surf;
unsigned level;
unsigned pitch, slice, format;
unsigned offset;
unsigned level, pitch, slice, format, offset, array_mode;
if (state->zsbuf == NULL)
return;
@ -900,6 +898,10 @@ static void r600_db(struct r600_pipe_context *rctx, struct r600_pipe_state *rsta
rbuffer = &rtex->resource;
/* XXX remove this once tiling is properly supported */
array_mode = rtex->array_mode[level] ? rtex->array_mode[level] :
V_0280A0_ARRAY_1D_TILED_THIN1;
/* XXX quite sure for dx10+ hw don't need any offset hacks */
offset = r600_texture_get_offset((struct r600_resource_texture *)state->zsbuf->texture,
level, state->zsbuf->u.tex.first_layer);
@ -914,7 +916,7 @@ static void r600_db(struct r600_pipe_context *rctx, struct r600_pipe_state *rsta
0xFFFFFFFF, NULL);
r600_pipe_state_add_reg(rstate, R_028004_DB_DEPTH_VIEW, 0x00000000, 0xFFFFFFFF, NULL);
r600_pipe_state_add_reg(rstate, R_028010_DB_DEPTH_INFO,
S_028010_ARRAY_MODE(rtex->array_mode[level]) | S_028010_FORMAT(format),
S_028010_ARRAY_MODE(array_mode) | S_028010_FORMAT(format),
0xFFFFFFFF, rbuffer->bo);
r600_pipe_state_add_reg(rstate, R_028D34_DB_PREFETCH_LIMIT,
(surf->aligned_height / 8) - 1, 0xFFFFFFFF, NULL);