diff --git a/src/gallium/auxiliary/pipebuffer/pb_buffer.h b/src/gallium/auxiliary/pipebuffer/pb_buffer.h
index 8c0545505d5..89cd0b25678 100644
--- a/src/gallium/auxiliary/pipebuffer/pb_buffer.h
+++ b/src/gallium/auxiliary/pipebuffer/pb_buffer.h
@@ -64,13 +64,13 @@ enum pb_usage_flags {
    PB_USAGE_CPU_WRITE = (1 << 1),
    PB_USAGE_GPU_READ = (1 << 2),
    PB_USAGE_GPU_WRITE = (1 << 3),
-   PB_USAGE_DONTBLOCK = (1 << 9),
-   PB_USAGE_UNSYNCHRONIZED = (1 << 10),
+   PB_USAGE_DONTBLOCK = (1 << 4),
+   PB_USAGE_UNSYNCHRONIZED = (1 << 5),
    /* Persistent mappings may remain across a flush. Note that contrary
     * to OpenGL persistent maps, there is no requirement at the pipebuffer
     * api level to explicitly enforce coherency by barriers or range flushes.
     */
-   PB_USAGE_PERSISTENT = (1 << 13)
+   PB_USAGE_PERSISTENT = (1 << 8)
 };
 
 /* For error checking elsewhere */
diff --git a/src/gallium/drivers/iris/iris_bufmgr.h b/src/gallium/drivers/iris/iris_bufmgr.h
index c2e2d0e8e54..0b098b76110 100644
--- a/src/gallium/drivers/iris/iris_bufmgr.h
+++ b/src/gallium/drivers/iris/iris_bufmgr.h
@@ -298,8 +298,8 @@ void iris_bo_unreference(struct iris_bo *bo);
 #define MAP_PERSISTENT    PIPE_MAP_PERSISTENT
 #define MAP_COHERENT      PIPE_MAP_COHERENT
 /* internal */
-#define MAP_INTERNAL_MASK (0xffu << 24)
-#define MAP_RAW           (0x01 << 24)
+#define MAP_RAW           (PIPE_MAP_DRV_PRV << 0)
+#define MAP_INTERNAL_MASK (MAP_RAW)
 
 #define MAP_FLAGS         (MAP_READ | MAP_WRITE | MAP_ASYNC | \
                            MAP_PERSISTENT | MAP_COHERENT | MAP_INTERNAL_MASK)
diff --git a/src/gallium/include/pipe/p_defines.h b/src/gallium/include/pipe/p_defines.h
index b42f26b26d4..0462d6aa2cd 100644
--- a/src/gallium/include/pipe/p_defines.h
+++ b/src/gallium/include/pipe/p_defines.h
@@ -246,13 +246,13 @@ enum pipe_map_flags
     * Resource contents read back (or accessed directly) at transfer
     * create time.
     */
-   PIPE_MAP_READ = (1 << 0),
+   PIPE_MAP_READ = 1 << 0,
    
    /**
     * Resource contents will be written back at transfer_unmap
     * time (or modified as a result of being accessed directly).
     */
-   PIPE_MAP_WRITE = (1 << 1),
+   PIPE_MAP_WRITE = 1 << 1,
 
    /**
     * Read/modify/write
@@ -270,7 +270,7 @@ enum pipe_map_flags
     *
     * This flag supresses implicit "DISCARD" for buffer_subdata.
     */
-   PIPE_MAP_DIRECTLY = (1 << 2),
+   PIPE_MAP_DIRECTLY = 1 << 2,
 
    /**
     * Discards the memory within the mapped region.
@@ -280,7 +280,7 @@ enum pipe_map_flags
     * See also:
     * - OpenGL's ARB_map_buffer_range extension, MAP_INVALIDATE_RANGE_BIT flag.
     */
-   PIPE_MAP_DISCARD_RANGE = (1 << 8),
+   PIPE_MAP_DISCARD_RANGE = 1 << 3,
 
    /**
     * Fail if the resource cannot be mapped immediately.
@@ -290,7 +290,7 @@ enum pipe_map_flags
     * - Mesa's MESA_MAP_NOWAIT_BIT flag.
     * - WDDM's D3DDDICB_LOCKFLAGS.DonotWait flag.
     */
-   PIPE_MAP_DONTBLOCK = (1 << 9),
+   PIPE_MAP_DONTBLOCK = 1 << 4,
 
    /**
     * Do not attempt to synchronize pending operations on the resource when mapping.
@@ -302,7 +302,7 @@ enum pipe_map_flags
     * - Direct3D's D3DLOCK_NOOVERWRITE flag.
     * - WDDM's D3DDDICB_LOCKFLAGS.IgnoreSync flag.
     */
-   PIPE_MAP_UNSYNCHRONIZED = (1 << 10),
+   PIPE_MAP_UNSYNCHRONIZED = 1 << 5,
 
    /**
     * Written ranges will be notified later with
@@ -314,7 +314,7 @@ enum pipe_map_flags
     * - pipe_context::transfer_flush_region
     * - OpenGL's ARB_map_buffer_range extension, MAP_FLUSH_EXPLICIT_BIT flag.
     */
-   PIPE_MAP_FLUSH_EXPLICIT = (1 << 11),
+   PIPE_MAP_FLUSH_EXPLICIT = 1 << 6,
 
    /**
     * Discards all memory backing the resource.
@@ -329,7 +329,7 @@ enum pipe_map_flags
     * - D3D10 DDI's D3D10_DDI_MAP_WRITE_DISCARD flag
     * - D3D10's D3D10_MAP_WRITE_DISCARD flag.
     */
-   PIPE_MAP_DISCARD_WHOLE_RESOURCE = (1 << 12),
+   PIPE_MAP_DISCARD_WHOLE_RESOURCE = 1 << 7,
 
    /**
     * Allows the resource to be used for rendering while mapped.
@@ -340,7 +340,7 @@ enum pipe_map_flags
     * If COHERENT is not set, memory_barrier(PIPE_BARRIER_MAPPED_BUFFER)
     * must be called to ensure the device can see what the CPU has written.
     */
-   PIPE_MAP_PERSISTENT = (1 << 13),
+   PIPE_MAP_PERSISTENT = 1 << 8,
 
    /**
     * If PERSISTENT is set, this ensures any writes done by the device are
@@ -349,35 +349,35 @@ enum pipe_map_flags
     * PIPE_RESOURCE_FLAG_MAP_COHERENT must be set when creating
     * the resource.
     */
-   PIPE_MAP_COHERENT = (1 << 14),
+   PIPE_MAP_COHERENT = 1 << 9,
 
    /**
     * Map a resource in a thread-safe manner, because the calling thread can
     * be any thread. It can only be used if both WRITE and UNSYNCHRONIZED are
     * set.
     */
-   PIPE_MAP_THREAD_SAFE = 1 << 15,
+   PIPE_MAP_THREAD_SAFE = 1 << 10,
 
    /**
     * Map only the depth aspect of a resource
     */
-   PIPE_MAP_DEPTH_ONLY = 1 << 16,
+   PIPE_MAP_DEPTH_ONLY = 1 << 11,
 
    /**
     * Map only the stencil aspect of a resource
     */
-   PIPE_MAP_STENCIL_ONLY = 1 << 17,
+   PIPE_MAP_STENCIL_ONLY = 1 << 12,
 
    /**
     * Mapping will be used only once (never remapped).
     */
-   PIPE_MAP_ONCE = 1 << 18,
+   PIPE_MAP_ONCE = 1 << 13,
 
    /**
     * This and higher bits are reserved for private use by drivers. Drivers
     * should use this as (PIPE_MAP_DRV_PRV << i).
     */
-   PIPE_MAP_DRV_PRV = (1 << 24)
+   PIPE_MAP_DRV_PRV = 1 << 14,
 };
 
 /**