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anv: fix vkCmdWaitEvents2 handling
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Cc: mesa-stable Reviewed-by: Rohan Garg <rohan.garg@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29716>
This commit is contained in:
Lionel Landwerlin
Marge Bot
parent
97ebe52ee3
commit
00982e1af6
1 changed files with 256 additions and 230 deletions
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@ -3781,62 +3781,73 @@ mask_is_transfer_write(const VkAccessFlags2 access)
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static void
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cmd_buffer_barrier_video(struct anv_cmd_buffer *cmd_buffer,
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const VkDependencyInfo *dep_info)
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uint32_t n_dep_infos,
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const VkDependencyInfo *dep_infos)
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{
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assert(anv_cmd_buffer_is_video_queue(cmd_buffer));
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bool flush_llc = false;
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bool flush_ccs = false;
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for (uint32_t i = 0; i < dep_info->imageMemoryBarrierCount; i++) {
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const VkImageMemoryBarrier2 *img_barrier =
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&dep_info->pImageMemoryBarriers[i];
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ANV_FROM_HANDLE(anv_image, image, img_barrier->image);
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const VkImageSubresourceRange *range = &img_barrier->subresourceRange;
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for (uint32_t d = 0; d < n_dep_infos; d++) {
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const VkDependencyInfo *dep_info = &dep_infos[d];
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/* If srcQueueFamilyIndex is not equal to dstQueueFamilyIndex, this
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* memory barrier defines a queue family ownership transfer.
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*/
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if (img_barrier->srcQueueFamilyIndex != img_barrier->dstQueueFamilyIndex)
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flush_llc = true;
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VkImageAspectFlags img_aspects =
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for (uint32_t i = 0; i < dep_info->imageMemoryBarrierCount; i++) {
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const VkImageMemoryBarrier2 *img_barrier =
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&dep_info->pImageMemoryBarriers[i];
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ANV_FROM_HANDLE(anv_image, image, img_barrier->image);
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const VkImageSubresourceRange *range = &img_barrier->subresourceRange;
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/* If srcQueueFamilyIndex is not equal to dstQueueFamilyIndex, this
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* memory barrier defines a queue family ownership transfer.
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*/
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if (img_barrier->srcQueueFamilyIndex != img_barrier->dstQueueFamilyIndex)
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flush_llc = true;
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VkImageAspectFlags img_aspects =
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vk_image_expand_aspect_mask(&image->vk, range->aspectMask);
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anv_foreach_image_aspect_bit(aspect_bit, image, img_aspects) {
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const uint32_t plane =
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anv_image_aspect_to_plane(image, 1UL << aspect_bit);
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if (isl_aux_usage_has_ccs(image->planes[plane].aux_usage)) {
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flush_ccs = true;
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anv_foreach_image_aspect_bit(aspect_bit, image, img_aspects) {
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const uint32_t plane =
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anv_image_aspect_to_plane(image, 1UL << aspect_bit);
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if (isl_aux_usage_has_ccs(image->planes[plane].aux_usage)) {
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flush_ccs = true;
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}
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}
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}
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}
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for (uint32_t i = 0; i < dep_info->bufferMemoryBarrierCount; i++) {
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/* Flush the cache if something is written by the video operations and
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* used by any other stages except video encode/decode stages or if
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* srcQueueFamilyIndex is not equal to dstQueueFamilyIndex, this memory
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* barrier defines a queue family ownership transfer.
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*/
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if ((stage_is_video(dep_info->pBufferMemoryBarriers[i].srcStageMask) &&
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mask_is_write(dep_info->pBufferMemoryBarriers[i].srcAccessMask) &&
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!stage_is_video(dep_info->pBufferMemoryBarriers[i].dstStageMask)) ||
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(dep_info->pBufferMemoryBarriers[i].srcQueueFamilyIndex !=
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dep_info->pBufferMemoryBarriers[i].dstQueueFamilyIndex)) {
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flush_llc = true;
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break;
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for (uint32_t i = 0; i < dep_info->bufferMemoryBarrierCount; i++) {
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/* Flush the cache if something is written by the video operations and
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* used by any other stages except video encode/decode stages or if
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* srcQueueFamilyIndex is not equal to dstQueueFamilyIndex, this memory
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* barrier defines a queue family ownership transfer.
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*/
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if ((stage_is_video(dep_info->pBufferMemoryBarriers[i].srcStageMask) &&
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mask_is_write(dep_info->pBufferMemoryBarriers[i].srcAccessMask) &&
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!stage_is_video(dep_info->pBufferMemoryBarriers[i].dstStageMask)) ||
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(dep_info->pBufferMemoryBarriers[i].srcQueueFamilyIndex !=
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dep_info->pBufferMemoryBarriers[i].dstQueueFamilyIndex)) {
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flush_llc = true;
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break;
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}
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}
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}
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for (uint32_t i = 0; i < dep_info->memoryBarrierCount; i++) {
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/* Flush the cache if something is written by the video operations and
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* used by any other stages except video encode/decode stage.
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*/
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if (stage_is_video(dep_info->pMemoryBarriers[i].srcStageMask) &&
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mask_is_write(dep_info->pMemoryBarriers[i].srcAccessMask) &&
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!stage_is_video(dep_info->pMemoryBarriers[i].dstStageMask)) {
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flush_llc = true;
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break;
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for (uint32_t i = 0; i < dep_info->memoryBarrierCount; i++) {
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/* Flush the cache if something is written by the video operations and
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* used by any other stages except video encode/decode stage.
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*/
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if (stage_is_video(dep_info->pMemoryBarriers[i].srcStageMask) &&
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mask_is_write(dep_info->pMemoryBarriers[i].srcAccessMask) &&
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!stage_is_video(dep_info->pMemoryBarriers[i].dstStageMask)) {
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flush_llc = true;
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break;
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}
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}
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/* We cannot gather more information than that. */
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if (flush_ccs && flush_llc)
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break;
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}
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if (flush_ccs || flush_llc) {
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@ -3857,7 +3868,8 @@ cmd_buffer_barrier_video(struct anv_cmd_buffer *cmd_buffer,
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static void
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cmd_buffer_barrier_blitter(struct anv_cmd_buffer *cmd_buffer,
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const VkDependencyInfo *dep_info)
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uint32_t n_dep_infos,
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const VkDependencyInfo *dep_infos)
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{
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#if GFX_VERx10 >= 125
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assert(anv_cmd_buffer_is_blitter_queue(cmd_buffer));
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@ -3867,65 +3879,74 @@ cmd_buffer_barrier_blitter(struct anv_cmd_buffer *cmd_buffer,
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*/
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bool flush_llc = false;
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bool flush_ccs = false;
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for (uint32_t i = 0; i < dep_info->imageMemoryBarrierCount; i++) {
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const VkImageMemoryBarrier2 *img_barrier =
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&dep_info->pImageMemoryBarriers[i];
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ANV_FROM_HANDLE(anv_image, image, img_barrier->image);
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const VkImageSubresourceRange *range = &img_barrier->subresourceRange;
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for (uint32_t d = 0; d < n_dep_infos; d++) {
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const VkDependencyInfo *dep_info = &dep_infos[d];
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/* If srcQueueFamilyIndex is not equal to dstQueueFamilyIndex, this
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* memory barrier defines a queue family transfer operation.
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*/
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if (img_barrier->srcQueueFamilyIndex != img_barrier->dstQueueFamilyIndex)
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flush_llc = true;
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for (uint32_t i = 0; i < dep_info->imageMemoryBarrierCount; i++) {
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const VkImageMemoryBarrier2 *img_barrier =
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&dep_info->pImageMemoryBarriers[i];
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/* Flush cache if transfer command reads the output of the previous
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* transfer command, ideally we should just wait for the completion but
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* for now just flush the cache to make the data visible.
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*/
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if ((img_barrier->oldLayout == VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL ||
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img_barrier->oldLayout == VK_IMAGE_LAYOUT_GENERAL) &&
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(img_barrier->newLayout == VK_IMAGE_LAYOUT_TRANSFER_SRC_OPTIMAL ||
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img_barrier->newLayout == VK_IMAGE_LAYOUT_GENERAL)) {
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flush_llc = true;
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}
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ANV_FROM_HANDLE(anv_image, image, img_barrier->image);
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const VkImageSubresourceRange *range = &img_barrier->subresourceRange;
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VkImageAspectFlags img_aspects =
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/* If srcQueueFamilyIndex is not equal to dstQueueFamilyIndex, this
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* memory barrier defines a queue family transfer operation.
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*/
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if (img_barrier->srcQueueFamilyIndex != img_barrier->dstQueueFamilyIndex)
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flush_llc = true;
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/* Flush cache if transfer command reads the output of the previous
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* transfer command, ideally we should just wait for the completion
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* but for now just flush the cache to make the data visible.
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*/
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if ((img_barrier->oldLayout == VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL ||
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img_barrier->oldLayout == VK_IMAGE_LAYOUT_GENERAL) &&
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(img_barrier->newLayout == VK_IMAGE_LAYOUT_TRANSFER_SRC_OPTIMAL ||
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img_barrier->newLayout == VK_IMAGE_LAYOUT_GENERAL)) {
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flush_llc = true;
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}
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VkImageAspectFlags img_aspects =
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vk_image_expand_aspect_mask(&image->vk, range->aspectMask);
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anv_foreach_image_aspect_bit(aspect_bit, image, img_aspects) {
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const uint32_t plane =
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anv_image_aspect_to_plane(image, 1UL << aspect_bit);
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if (isl_aux_usage_has_ccs(image->planes[plane].aux_usage)) {
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flush_ccs = true;
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anv_foreach_image_aspect_bit(aspect_bit, image, img_aspects) {
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const uint32_t plane =
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anv_image_aspect_to_plane(image, 1UL << aspect_bit);
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if (isl_aux_usage_has_ccs(image->planes[plane].aux_usage)) {
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flush_ccs = true;
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}
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}
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}
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}
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for (uint32_t i = 0; i < dep_info->bufferMemoryBarrierCount; i++) {
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/* Flush the cache if something is written by the transfer command and
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* used by any other stages except transfer stage or if
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* srcQueueFamilyIndex is not equal to dstQueueFamilyIndex, this memory
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* barrier defines a queue family transfer operation.
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*/
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if ((stage_is_transfer(dep_info->pBufferMemoryBarriers[i].srcStageMask) &&
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mask_is_write(dep_info->pBufferMemoryBarriers[i].srcAccessMask)) ||
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(dep_info->pBufferMemoryBarriers[i].srcQueueFamilyIndex !=
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dep_info->pBufferMemoryBarriers[i].dstQueueFamilyIndex)) {
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flush_llc = true;
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break;
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for (uint32_t i = 0; i < dep_info->bufferMemoryBarrierCount; i++) {
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/* Flush the cache if something is written by the transfer command
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* and used by any other stages except transfer stage or if
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* srcQueueFamilyIndex is not equal to dstQueueFamilyIndex, this
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* memory barrier defines a queue family transfer operation.
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*/
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if ((stage_is_transfer(dep_info->pBufferMemoryBarriers[i].srcStageMask) &&
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mask_is_write(dep_info->pBufferMemoryBarriers[i].srcAccessMask)) ||
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(dep_info->pBufferMemoryBarriers[i].srcQueueFamilyIndex !=
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dep_info->pBufferMemoryBarriers[i].dstQueueFamilyIndex)) {
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flush_llc = true;
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break;
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}
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}
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}
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for (uint32_t i = 0; i < dep_info->memoryBarrierCount; i++) {
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/* Flush the cache if something is written by the transfer command and
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* used by any other stages except transfer stage.
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*/
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if (stage_is_transfer(dep_info->pMemoryBarriers[i].srcStageMask) &&
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mask_is_write(dep_info->pMemoryBarriers[i].srcAccessMask)) {
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flush_llc = true;
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break;
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for (uint32_t i = 0; i < dep_info->memoryBarrierCount; i++) {
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/* Flush the cache if something is written by the transfer command
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* and used by any other stages except transfer stage.
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*/
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if (stage_is_transfer(dep_info->pMemoryBarriers[i].srcStageMask) &&
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mask_is_write(dep_info->pMemoryBarriers[i].srcAccessMask)) {
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flush_llc = true;
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break;
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}
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}
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/* We cannot gather more information than that. */
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if (flush_ccs && flush_llc)
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break;
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}
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if (flush_ccs || flush_llc) {
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@ -3954,24 +3975,25 @@ cmd_buffer_has_pending_copy_query(struct anv_cmd_buffer *cmd_buffer)
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static void
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cmd_buffer_barrier(struct anv_cmd_buffer *cmd_buffer,
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const VkDependencyInfo *dep_info,
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uint32_t n_dep_infos,
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const VkDependencyInfo *dep_infos,
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const char *reason)
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{
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if (anv_cmd_buffer_is_video_queue(cmd_buffer)) {
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cmd_buffer_barrier_video(cmd_buffer, dep_info);
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cmd_buffer_barrier_video(cmd_buffer, n_dep_infos, dep_infos);
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return;
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}
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if (anv_cmd_buffer_is_blitter_queue(cmd_buffer)) {
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cmd_buffer_barrier_blitter(cmd_buffer, dep_info);
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cmd_buffer_barrier_blitter(cmd_buffer, n_dep_infos, dep_infos);
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return;
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}
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struct anv_device *device = cmd_buffer->device;
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/* XXX: Right now, we're really dumb and just flush whatever categories
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* the app asks for. One of these days we may make this a bit better
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* but right now that's all the hardware allows for in most areas.
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* the app asks for. One of these days we may make this a bit better but
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* right now that's all the hardware allows for in most areas.
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*/
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VkAccessFlags2 src_flags = 0;
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VkAccessFlags2 dst_flags = 0;
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@ -3979,166 +4001,170 @@ cmd_buffer_barrier(struct anv_cmd_buffer *cmd_buffer,
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bool apply_sparse_flushes = false;
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bool flush_query_copies = false;
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for (uint32_t i = 0; i < dep_info->memoryBarrierCount; i++) {
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src_flags |= dep_info->pMemoryBarriers[i].srcAccessMask;
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dst_flags |= dep_info->pMemoryBarriers[i].dstAccessMask;
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for (uint32_t d = 0; d < n_dep_infos; d++) {
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const VkDependencyInfo *dep_info = &dep_infos[d];
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/* Shader writes to buffers that could then be written by a transfer
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* command (including queries).
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*/
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if (stage_is_shader(dep_info->pMemoryBarriers[i].srcStageMask) &&
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mask_is_shader_write(dep_info->pMemoryBarriers[i].srcAccessMask) &&
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stage_is_transfer(dep_info->pMemoryBarriers[i].dstStageMask)) {
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cmd_buffer->state.queries.buffer_write_bits |=
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ANV_QUERY_COMPUTE_WRITES_PENDING_BITS;
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for (uint32_t i = 0; i < dep_info->memoryBarrierCount; i++) {
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src_flags |= dep_info->pMemoryBarriers[i].srcAccessMask;
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dst_flags |= dep_info->pMemoryBarriers[i].dstAccessMask;
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/* Shader writes to buffers that could then be written by a transfer
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* command (including queries).
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*/
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if (stage_is_shader(dep_info->pMemoryBarriers[i].srcStageMask) &&
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mask_is_shader_write(dep_info->pMemoryBarriers[i].srcAccessMask) &&
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stage_is_transfer(dep_info->pMemoryBarriers[i].dstStageMask)) {
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cmd_buffer->state.queries.buffer_write_bits |=
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ANV_QUERY_COMPUTE_WRITES_PENDING_BITS;
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}
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if (stage_is_transfer(dep_info->pMemoryBarriers[i].srcStageMask) &&
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mask_is_transfer_write(dep_info->pMemoryBarriers[i].srcAccessMask) &&
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cmd_buffer_has_pending_copy_query(cmd_buffer))
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flush_query_copies = true;
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/* There's no way of knowing if this memory barrier is related to
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* sparse buffers! This is pretty horrible.
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*/
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if (mask_is_write(src_flags) &&
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p_atomic_read(&device->num_sparse_resources) > 0)
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apply_sparse_flushes = true;
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}
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if (stage_is_transfer(dep_info->pMemoryBarriers[i].srcStageMask) &&
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mask_is_transfer_write(dep_info->pMemoryBarriers[i].srcAccessMask) &&
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cmd_buffer_has_pending_copy_query(cmd_buffer))
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flush_query_copies = true;
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for (uint32_t i = 0; i < dep_info->bufferMemoryBarrierCount; i++) {
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const VkBufferMemoryBarrier2 *buf_barrier =
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&dep_info->pBufferMemoryBarriers[i];
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ANV_FROM_HANDLE(anv_buffer, buffer, buf_barrier->buffer);
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/* There's no way of knowing if this memory barrier is related to sparse
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* buffers! This is pretty horrible.
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*/
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if (mask_is_write(src_flags) &&
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p_atomic_read(&device->num_sparse_resources) > 0)
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apply_sparse_flushes = true;
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}
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src_flags |= buf_barrier->srcAccessMask;
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dst_flags |= buf_barrier->dstAccessMask;
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for (uint32_t i = 0; i < dep_info->bufferMemoryBarrierCount; i++) {
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const VkBufferMemoryBarrier2 *buf_barrier =
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&dep_info->pBufferMemoryBarriers[i];
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ANV_FROM_HANDLE(anv_buffer, buffer, buf_barrier->buffer);
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/* Shader writes to buffers that could then be written by a transfer
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* command (including queries).
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*/
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if (stage_is_shader(buf_barrier->srcStageMask) &&
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mask_is_shader_write(buf_barrier->srcAccessMask) &&
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stage_is_transfer(buf_barrier->dstStageMask)) {
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cmd_buffer->state.queries.buffer_write_bits |=
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ANV_QUERY_COMPUTE_WRITES_PENDING_BITS;
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}
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src_flags |= buf_barrier->srcAccessMask;
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dst_flags |= buf_barrier->dstAccessMask;
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if (stage_is_transfer(buf_barrier->srcStageMask) &&
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mask_is_transfer_write(buf_barrier->srcAccessMask) &&
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cmd_buffer_has_pending_copy_query(cmd_buffer))
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flush_query_copies = true;
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/* Shader writes to buffers that could then be written by a transfer
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* command (including queries).
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*/
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if (stage_is_shader(buf_barrier->srcStageMask) &&
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mask_is_shader_write(buf_barrier->srcAccessMask) &&
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stage_is_transfer(buf_barrier->dstStageMask)) {
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cmd_buffer->state.queries.buffer_write_bits |=
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ANV_QUERY_COMPUTE_WRITES_PENDING_BITS;
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if (anv_buffer_is_sparse(buffer) && mask_is_write(src_flags))
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apply_sparse_flushes = true;
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}
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if (stage_is_transfer(buf_barrier->srcStageMask) &&
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mask_is_transfer_write(buf_barrier->srcAccessMask) &&
|
||||
cmd_buffer_has_pending_copy_query(cmd_buffer))
|
||||
flush_query_copies = true;
|
||||
for (uint32_t i = 0; i < dep_info->imageMemoryBarrierCount; i++) {
|
||||
const VkImageMemoryBarrier2 *img_barrier =
|
||||
&dep_info->pImageMemoryBarriers[i];
|
||||
|
||||
if (anv_buffer_is_sparse(buffer) && mask_is_write(src_flags))
|
||||
apply_sparse_flushes = true;
|
||||
}
|
||||
src_flags |= img_barrier->srcAccessMask;
|
||||
dst_flags |= img_barrier->dstAccessMask;
|
||||
|
||||
for (uint32_t i = 0; i < dep_info->imageMemoryBarrierCount; i++) {
|
||||
const VkImageMemoryBarrier2 *img_barrier =
|
||||
&dep_info->pImageMemoryBarriers[i];
|
||||
ANV_FROM_HANDLE(anv_image, image, img_barrier->image);
|
||||
const VkImageSubresourceRange *range = &img_barrier->subresourceRange;
|
||||
|
||||
src_flags |= img_barrier->srcAccessMask;
|
||||
dst_flags |= img_barrier->dstAccessMask;
|
||||
uint32_t base_layer, layer_count;
|
||||
if (image->vk.image_type == VK_IMAGE_TYPE_3D) {
|
||||
base_layer = 0;
|
||||
layer_count = u_minify(image->vk.extent.depth, range->baseMipLevel);
|
||||
} else {
|
||||
base_layer = range->baseArrayLayer;
|
||||
layer_count = vk_image_subresource_layer_count(&image->vk, range);
|
||||
}
|
||||
const uint32_t level_count =
|
||||
vk_image_subresource_level_count(&image->vk, range);
|
||||
|
||||
ANV_FROM_HANDLE(anv_image, image, img_barrier->image);
|
||||
const VkImageSubresourceRange *range = &img_barrier->subresourceRange;
|
||||
VkImageLayout old_layout = img_barrier->oldLayout;
|
||||
VkImageLayout new_layout = img_barrier->newLayout;
|
||||
|
||||
uint32_t base_layer, layer_count;
|
||||
if (image->vk.image_type == VK_IMAGE_TYPE_3D) {
|
||||
base_layer = 0;
|
||||
layer_count = u_minify(image->vk.extent.depth, range->baseMipLevel);
|
||||
} else {
|
||||
base_layer = range->baseArrayLayer;
|
||||
layer_count = vk_image_subresource_layer_count(&image->vk, range);
|
||||
}
|
||||
const uint32_t level_count =
|
||||
vk_image_subresource_level_count(&image->vk, range);
|
||||
/* If we're inside a render pass, the runtime might have converted
|
||||
* some layouts from GENERAL to FEEDBACK_LOOP. Check if that's the
|
||||
* case and reconvert back to the original layout so that application
|
||||
* barriers within renderpass are operating with consistent layouts.
|
||||
*/
|
||||
if (!cmd_buffer->vk.runtime_rp_barrier &&
|
||||
cmd_buffer->vk.render_pass != NULL) {
|
||||
assert(anv_cmd_graphics_state_has_image_as_attachment(&cmd_buffer->state.gfx,
|
||||
image));
|
||||
VkImageLayout subpass_att_layout, subpass_stencil_att_layout;
|
||||
|
||||
VkImageLayout old_layout = img_barrier->oldLayout;
|
||||
VkImageLayout new_layout = img_barrier->newLayout;
|
||||
vk_command_buffer_get_attachment_layout(
|
||||
&cmd_buffer->vk, &image->vk,
|
||||
&subpass_att_layout, &subpass_stencil_att_layout);
|
||||
|
||||
/* If we're inside a render pass, the runtime might have converted some
|
||||
* layouts from GENERAL to FEEDBACK_LOOP. Check if that's the case and
|
||||
* reconvert back to the original layout so that application barriers
|
||||
* within renderpass are operating with consistent layouts.
|
||||
*/
|
||||
if (!cmd_buffer->vk.runtime_rp_barrier &&
|
||||
cmd_buffer->vk.render_pass != NULL) {
|
||||
assert(anv_cmd_graphics_state_has_image_as_attachment(&cmd_buffer->state.gfx,
|
||||
image));
|
||||
VkImageLayout subpass_att_layout, subpass_stencil_att_layout;
|
||||
old_layout = subpass_att_layout;
|
||||
new_layout = subpass_att_layout;
|
||||
}
|
||||
|
||||
vk_command_buffer_get_attachment_layout(
|
||||
&cmd_buffer->vk, &image->vk,
|
||||
&subpass_att_layout, &subpass_stencil_att_layout);
|
||||
|
||||
old_layout = subpass_att_layout;
|
||||
new_layout = subpass_att_layout;
|
||||
}
|
||||
|
||||
if (range->aspectMask & VK_IMAGE_ASPECT_DEPTH_BIT) {
|
||||
transition_depth_buffer(cmd_buffer, image,
|
||||
range->baseMipLevel, level_count,
|
||||
base_layer, layer_count,
|
||||
old_layout, new_layout,
|
||||
false /* will_full_fast_clear */);
|
||||
}
|
||||
|
||||
if (range->aspectMask & VK_IMAGE_ASPECT_STENCIL_BIT) {
|
||||
transition_stencil_buffer(cmd_buffer, image,
|
||||
range->baseMipLevel, level_count,
|
||||
base_layer, layer_count,
|
||||
old_layout, new_layout,
|
||||
false /* will_full_fast_clear */);
|
||||
}
|
||||
|
||||
if (range->aspectMask & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) {
|
||||
VkImageAspectFlags color_aspects =
|
||||
vk_image_expand_aspect_mask(&image->vk, range->aspectMask);
|
||||
anv_foreach_image_aspect_bit(aspect_bit, image, color_aspects) {
|
||||
transition_color_buffer(cmd_buffer, image, 1UL << aspect_bit,
|
||||
if (range->aspectMask & VK_IMAGE_ASPECT_DEPTH_BIT) {
|
||||
transition_depth_buffer(cmd_buffer, image,
|
||||
range->baseMipLevel, level_count,
|
||||
base_layer, layer_count,
|
||||
old_layout, new_layout,
|
||||
img_barrier->srcQueueFamilyIndex,
|
||||
img_barrier->dstQueueFamilyIndex,
|
||||
false /* will_full_fast_clear */);
|
||||
}
|
||||
}
|
||||
|
||||
/* Mark image as compressed if the destination layout has untracked
|
||||
* writes to the aux surface.
|
||||
*/
|
||||
VkImageAspectFlags aspects =
|
||||
vk_image_expand_aspect_mask(&image->vk, range->aspectMask);
|
||||
anv_foreach_image_aspect_bit(aspect_bit, image, aspects) {
|
||||
VkImageAspectFlagBits aspect = 1UL << aspect_bit;
|
||||
if (anv_layout_has_untracked_aux_writes(
|
||||
device->info,
|
||||
image, aspect,
|
||||
img_barrier->newLayout,
|
||||
cmd_buffer->queue_family->queueFlags)) {
|
||||
for (uint32_t l = 0; l < level_count; l++) {
|
||||
const uint32_t level = range->baseMipLevel + l;
|
||||
const uint32_t aux_layers =
|
||||
anv_image_aux_layers(image, aspect, level);
|
||||
if (range->aspectMask & VK_IMAGE_ASPECT_STENCIL_BIT) {
|
||||
transition_stencil_buffer(cmd_buffer, image,
|
||||
range->baseMipLevel, level_count,
|
||||
base_layer, layer_count,
|
||||
old_layout, new_layout,
|
||||
false /* will_full_fast_clear */);
|
||||
}
|
||||
|
||||
if (base_layer >= aux_layers)
|
||||
break; /* We will only get fewer layers as level increases */
|
||||
|
||||
uint32_t level_layer_count =
|
||||
MIN2(layer_count, aux_layers - base_layer);
|
||||
|
||||
set_image_compressed_bit(cmd_buffer, image, aspect,
|
||||
level,
|
||||
base_layer, level_layer_count,
|
||||
true);
|
||||
if (range->aspectMask & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) {
|
||||
VkImageAspectFlags color_aspects =
|
||||
vk_image_expand_aspect_mask(&image->vk, range->aspectMask);
|
||||
anv_foreach_image_aspect_bit(aspect_bit, image, color_aspects) {
|
||||
transition_color_buffer(cmd_buffer, image, 1UL << aspect_bit,
|
||||
range->baseMipLevel, level_count,
|
||||
base_layer, layer_count,
|
||||
old_layout, new_layout,
|
||||
img_barrier->srcQueueFamilyIndex,
|
||||
img_barrier->dstQueueFamilyIndex,
|
||||
false /* will_full_fast_clear */);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if (anv_image_is_sparse(image) && mask_is_write(src_flags))
|
||||
apply_sparse_flushes = true;
|
||||
/* Mark image as compressed if the destination layout has untracked
|
||||
* writes to the aux surface.
|
||||
*/
|
||||
VkImageAspectFlags aspects =
|
||||
vk_image_expand_aspect_mask(&image->vk, range->aspectMask);
|
||||
anv_foreach_image_aspect_bit(aspect_bit, image, aspects) {
|
||||
VkImageAspectFlagBits aspect = 1UL << aspect_bit;
|
||||
if (anv_layout_has_untracked_aux_writes(
|
||||
device->info,
|
||||
image, aspect,
|
||||
img_barrier->newLayout,
|
||||
cmd_buffer->queue_family->queueFlags)) {
|
||||
for (uint32_t l = 0; l < level_count; l++) {
|
||||
const uint32_t level = range->baseMipLevel + l;
|
||||
const uint32_t aux_layers =
|
||||
anv_image_aux_layers(image, aspect, level);
|
||||
|
||||
if (base_layer >= aux_layers)
|
||||
break; /* We will only get fewer layers as level increases */
|
||||
|
||||
uint32_t level_layer_count =
|
||||
MIN2(layer_count, aux_layers - base_layer);
|
||||
|
||||
set_image_compressed_bit(cmd_buffer, image, aspect,
|
||||
level,
|
||||
base_layer, level_layer_count,
|
||||
true);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if (anv_image_is_sparse(image) && mask_is_write(src_flags))
|
||||
apply_sparse_flushes = true;
|
||||
}
|
||||
}
|
||||
|
||||
enum anv_pipe_bits bits =
|
||||
|
|
@ -4175,7 +4201,7 @@ void genX(CmdPipelineBarrier2)(
|
|||
{
|
||||
ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
|
||||
|
||||
cmd_buffer_barrier(cmd_buffer, pDependencyInfo, "pipe barrier");
|
||||
cmd_buffer_barrier(cmd_buffer, 1, pDependencyInfo, "pipe barrier");
|
||||
}
|
||||
|
||||
void
|
||||
|
|
@ -5701,7 +5727,7 @@ void genX(CmdWaitEvents2)(
|
|||
}
|
||||
}
|
||||
|
||||
cmd_buffer_barrier(cmd_buffer, pDependencyInfos, "wait event");
|
||||
cmd_buffer_barrier(cmd_buffer, eventCount, pDependencyInfos, "wait event");
|
||||
}
|
||||
|
||||
static uint32_t vk_to_intel_index_type(VkIndexType type)
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue