freedreno: Decouple GPU gen from gpu_id/chip_id

gpu_id is obsolete, chip_id doesn't encode the GPU generation.
Thus we have to manually specify the GPU gen instead of inferring it.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23828>

src/freedreno/common/freedreno_dev_info.h

@@ -38,6 +38,8 @@ extern "C" {
  */
 
 struct fd_dev_info {
+   uint8_t chip;
+
    /* alignment for size of tiles */
    uint32_t tile_align_w, tile_align_h;
    /* gmem load/store granularity */
@@ -195,10 +197,12 @@ fd_dev_gpu_id(const struct fd_dev_id *id)
    return id->gpu_id;
 }
 
+const struct fd_dev_info * fd_dev_info(const struct fd_dev_id *id);
+
 static uint8_t
 fd_dev_gen(const struct fd_dev_id *id)
 {
-   return fd_dev_gpu_id(id) / 100;
+   return fd_dev_info(id)->chip;
 }
 
 static inline bool
@@ -218,7 +222,6 @@ fd_dev_64b(const struct fd_dev_id *id)
  */
 #define A6XX_CCU_GMEM_COLOR_SIZE (16 * 1024)
 
-const struct fd_dev_info * fd_dev_info(const struct fd_dev_id *id);
 const char * fd_dev_name(const struct fd_dev_id *id);
 
 #ifdef __cplusplus

src/freedreno/common/freedreno_devices.py

@@ -22,10 +22,21 @@
 
 from mako.template import Template
 import sys
+from enum import Enum
 
 def max_bitfield_val(high, low, shift):
     return ((1 << (high - low)) - 1) << shift
 
+
+class CHIP(Enum):
+    A2XX = 2
+    A3XX = 3
+    A4XX = 4
+    A5XX = 5
+    A6XX = 6
+    A7XX = 7
+
+
 class State(object):
     def __init__(self):
         # List of unique device-info structs, multiple different GPU ids
@@ -89,9 +100,10 @@ class GPUInfo(Struct):
        tends to have lower limits, in which case a comment will describe
        the bitfield size/shift
     """
-    def __init__(self, gmem_align_w, gmem_align_h,
+    def __init__(self, chip, gmem_align_w, gmem_align_h,
                  tile_align_w, tile_align_h,
                  tile_max_w, tile_max_h, num_vsc_pipes):
+        self.chip          = chip.value
         self.gmem_align_w  = gmem_align_w
         self.gmem_align_h  = gmem_align_h
         self.tile_align_w  = tile_align_w
@@ -108,8 +120,8 @@ class A6xxGPUInfo(GPUInfo):
        into distinct sub-generations.  The template parameter avoids
        duplication of parameters that are unique to the sub-generation.
     """
-    def __init__(self, template, num_ccu, tile_align_w, tile_align_h, magic_regs):
-        super().__init__(gmem_align_w = 16, gmem_align_h = 4,
+    def __init__(self, chip, template, num_ccu, tile_align_w, tile_align_h, magic_regs):
+        super().__init__(chip, gmem_align_w = 16, gmem_align_h = 4,
                          tile_align_w = tile_align_w,
                          tile_align_h = tile_align_h,
                          tile_max_w   = 1024, # max_bitfield_val(5, 0, 5)
@@ -144,6 +156,7 @@ add_gpus([
         GPUId(205),
         GPUId(220),
     ], GPUInfo(
+        CHIP.A2XX,
         gmem_align_w = 32,  gmem_align_h = 32,
         tile_align_w = 32,  tile_align_h = 32,
         tile_max_w   = 512,
@@ -157,6 +170,7 @@ add_gpus([
         GPUId(320),
         GPUId(330),
     ], GPUInfo(
+        CHIP.A3XX,
         gmem_align_w = 32,  gmem_align_h = 32,
         tile_align_w = 32,  tile_align_h = 32,
         tile_max_w   = 992, # max_bitfield_val(4, 0, 5)
@@ -169,6 +183,7 @@ add_gpus([
         GPUId(420),
         GPUId(430),
     ], GPUInfo(
+        CHIP.A4XX,
         gmem_align_w = 32,  gmem_align_h = 32,
         tile_align_w = 32,  tile_align_h = 32,
         tile_max_w   = 1024, # max_bitfield_val(4, 0, 5)
@@ -185,6 +200,7 @@ add_gpus([
         GPUId(530),
         GPUId(540),
     ], GPUInfo(
+        CHIP.A5XX,
         gmem_align_w = 64,  gmem_align_h = 32,
         tile_align_w = 64,  tile_align_h = 32,
         tile_max_w   = 1024, # max_bitfield_val(7, 0, 5)
@@ -273,6 +289,7 @@ add_gpus([
         GPUId(618),
         GPUId(619),
     ], A6xxGPUInfo(
+        CHIP.A6XX,
         a6xx_gen1,
         num_ccu = 1,
         tile_align_w = 32,
@@ -297,6 +314,7 @@ add_gpus([
 add_gpus([
         GPUId(620),
     ], A6xxGPUInfo(
+        CHIP.A6XX,
         a6xx_gen1,
         num_ccu = 1,
         tile_align_w = 32,
@@ -321,6 +339,7 @@ add_gpus([
 add_gpus([
         GPUId(630),
     ], A6xxGPUInfo(
+        CHIP.A6XX,
         a6xx_gen1,
         num_ccu = 2,
         tile_align_w = 32,
@@ -345,6 +364,7 @@ add_gpus([
 add_gpus([
         GPUId(640),
     ], A6xxGPUInfo(
+        CHIP.A6XX,
         a6xx_gen2,
         num_ccu = 2,
         tile_align_w = 32,
@@ -369,6 +389,7 @@ add_gpus([
 add_gpus([
         GPUId(680),
     ], A6xxGPUInfo(
+        CHIP.A6XX,
         a6xx_gen2,
         num_ccu = 4,
         tile_align_w = 64,
@@ -393,6 +414,7 @@ add_gpus([
 add_gpus([
         GPUId(650),
     ], A6xxGPUInfo(
+        CHIP.A6XX,
         a6xx_gen3,
         num_ccu = 3,
         tile_align_w = 96,
@@ -422,6 +444,7 @@ add_gpus([
         # fallback wildcard entry should be last:
         GPUId(chip_id=0xffff06030500, name="Adreno 7c+ Gen 3"),
     ], A6xxGPUInfo(
+        CHIP.A6XX,
         a6xx_gen4,
         num_ccu = 2,
         tile_align_w = 32,
@@ -446,6 +469,7 @@ add_gpus([
 add_gpus([
         GPUId(660),
     ], A6xxGPUInfo(
+        CHIP.A6XX,
         a6xx_gen4,
         num_ccu = 3,
         tile_align_w = 96,
@@ -470,6 +494,7 @@ add_gpus([
 add_gpus([
         GPUId(690),
     ], A6xxGPUInfo(
+        CHIP.A6XX,
         a6xx_gen4,
         num_ccu = 8,
         tile_align_w = 64,
@@ -496,6 +521,7 @@ add_gpus([
         GPUId(730),
         GPUId(740),
     ], A6xxGPUInfo(
+        CHIP.A7XX,
         a6xx_gen4,
         num_ccu = 4,
         tile_align_w = 64,

src/freedreno/ir3/ir3_shader.c

@@ -838,7 +838,7 @@ ir3_shader_disasm(struct ir3_shader_variant *so, uint32_t *bin, FILE *out)
 
    isa_decode(bin, so->info.sizedwords * 4, out,
               &(struct isa_decode_options){
-                 .gpu_id = fd_dev_gpu_id(ir->compiler->dev_id),
+                 .gpu_id = ir->compiler->gen * 100,
                  .show_errors = true,
                  .branch_labels = true,
                  .no_match_cb = print_raw,