From 008163f3820eba5519cc80c31d660fa3de336f6d Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marcin=20=C5=9Alusarz?= <marcin.slusarz@intel.com>
Date: Mon, 13 Jun 2022 14:44:30 +0200
Subject: [PATCH] intel/compiler: vectorize task payload loads/stores
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Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17000>
---
 src/intel/compiler/brw_nir.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/intel/compiler/brw_nir.c b/src/intel/compiler/brw_nir.c
index 471409993d5..87fff7c9b85 100644
--- a/src/intel/compiler/brw_nir.c
+++ b/src/intel/compiler/brw_nir.c
@@ -1081,7 +1081,8 @@ brw_vectorize_lower_mem_access(nir_shader *nir,
    if (is_scalar) {
       nir_load_store_vectorize_options options = {
          .modes = nir_var_mem_ubo | nir_var_mem_ssbo |
-                  nir_var_mem_global | nir_var_mem_shared,
+                  nir_var_mem_global | nir_var_mem_shared |
+                  nir_var_mem_task_payload,
          .callback = brw_nir_should_vectorize_mem,
          .robust_modes = (nir_variable_mode)0,
       };