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nv50/ir: fix surface lowering when values get shared accross operations

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With nir I encountered the case where the same value can be written to from
multiple surface operations. This caused some weird messups with the unions
as the def.rewrite operations caused unrelated instructions to get new their
value replaced as well.

In order to replace def.rewrite, we have to create a new temp value, write
to that one instead and move to the original value.

Fixes: 869e32593a ("gm107/ir: fix loading z offset for layered 3d image bindings")
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11053>
(cherry picked from commit c1f938b647)
This commit is contained in:
Karol Herbst 2020-06-16 20:17:55 +02:00 • committed by Eric Engestrom
parent f7d970b274
commit 007e596ac5
2 changed files with 16 additions and 14 deletions
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2
.pick_status.json
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@ -1237,7 +1237,7 @@
"description": "nv50/ir: fix surface lowering when values get shared accross operations",
"nominated": true,
"nomination_type": 1,
"resolution": 0,
"resolution": 1,
"main_sha": null,
"because_sha": "869e32593a9096b845dd6106f8f86e1c41fac968"
},

28
src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
View file

@ -2328,15 +2328,15 @@ NVC0LoweringPass::insertOOBSurfaceOpResult(TexInstruction *su)
bld.setPosition(su, true);
for (unsigned i = 0; su->defExists(i); ++i) {
ValueDef &def = su->def(i);
Value *def = su->getDef(i);
Value *newDef = bld.getSSA();
su->setDef(i, newDef);
Instruction *mov = bld.mkMov(bld.getSSA(), bld.loadImm(NULL, 0));
assert(su->cc == CC_NOT_P);
mov->setPredicate(CC_P, su->getPredicate());
Instruction *uni = bld.mkOp2(OP_UNION, TYPE_U32, bld.getSSA(), NULL, mov->getDef(0));
def.replace(uni->getDef(0), false);
uni->setSrc(0, def.get());
Instruction *uni = bld.mkOp2(OP_UNION, TYPE_U32, bld.getSSA(), newDef, mov->getDef(0));
bld.mkMov(def, uni->getDef(0));
}
}
@ -2613,10 +2613,12 @@ NVC0LoweringPass::processSurfaceCoordsGM107(TexInstruction *su, Instruction *ret
for (unsigned i = 0; su->defExists(i); ++i) {
assert(i < 4);
ValueDef &def = su->def(i);
Value *def = su->getDef(i);
Value *newDef = bld.getSSA();
ValueDef &def2 = su2d->def(i);
Instruction *mov = NULL;
su->setDef(i, newDef);
if (pred) {
mov = bld.mkMov(bld.getSSA(), bld.loadImm(NULL, 0));
mov->setPredicate(CC_P, pred->getDef(0));
@ -2624,11 +2626,10 @@ NVC0LoweringPass::processSurfaceCoordsGM107(TexInstruction *su, Instruction *ret
Instruction *uni = ret[i] = bld.mkOp2(OP_UNION, TYPE_U32,
bld.getSSA(),
NULL, def2.get());
def.replace(uni->getDef(0), false);
uni->setSrc(0, def.get());
newDef, def2.get());
if (mov)
uni->setSrc(2, mov->getDef(0));
bld.mkMov(def, uni->getDef(0));
}
} else if (pred) {
// Create a UNION so that RA assigns the same registers
@ -2636,16 +2637,17 @@ NVC0LoweringPass::processSurfaceCoordsGM107(TexInstruction *su, Instruction *ret
for (unsigned i = 0; su->defExists(i); ++i) {
assert(i < 4);
ValueDef &def = su->def(i);
Value *def = su->getDef(i);
Value *newDef = bld.getSSA();
su->setDef(i, newDef);
Instruction *mov = bld.mkMov(bld.getSSA(), bld.loadImm(NULL, 0));
mov->setPredicate(CC_P, pred->getDef(0));
Instruction *uni = ret[i] = bld.mkOp2(OP_UNION, TYPE_U32,
bld.getSSA(),
NULL, mov->getDef(0));
def.replace(uni->getDef(0), false);
uni->setSrc(0, def.get());
newDef, mov->getDef(0));
bld.mkMov(def, uni->getDef(0));
}
}