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radv: configure the screen scissor to the maximum image dimension

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The framebuffer dimension exposed to apps is still 16k but since the
driver allows 32k image on GFX12+, meta operations might perform
operations (like a copy) using graphics.

While we are at it, use the correct bitfield for setting BR_X/BR_Y on
GFX12.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37974>
This commit is contained in:
Samuel Pitoiset 2025-10-21 15:56:39 +02:00 • committed by Marge Bot
parent bcde1a6650
commit 002ebb4fe5
1 changed files with 2 additions and 2 deletions
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4
src/amd/vulkan/radv_cmd_buffer.c
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@ -9734,7 +9734,7 @@ radv_CmdBeginRendering(VkCommandBuffer commandBuffer, const VkRenderingInfo *pRe
VK_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer); VK_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
struct radv_device *device = radv_cmd_buffer_device(cmd_buffer); struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
const struct radv_physical_device *pdev = radv_device_physical(device); const struct radv_physical_device *pdev = radv_device_physical(device);
VkExtent2D screen_scissor = {MAX_FRAMEBUFFER_WIDTH, MAX_FRAMEBUFFER_HEIGHT}; VkExtent2D screen_scissor = {pdev->image_props.max_dims.width, pdev->image_props.max_dims.height};
struct radv_cmd_stream *cs = cmd_buffer->cs; struct radv_cmd_stream *cs = cmd_buffer->cs;
bool disable_constant_encode_ac01 = false; bool disable_constant_encode_ac01 = false;
@ -9984,7 +9984,7 @@ radv_CmdBeginRendering(VkCommandBuffer commandBuffer, const VkRenderingInfo *pRe
gfx12_set_context_reg(R_028208_PA_SC_WINDOW_SCISSOR_BR, gfx12_set_context_reg(R_028208_PA_SC_WINDOW_SCISSOR_BR,
S_028208_BR_X(maxx - 1) | S_028208_BR_Y(maxy - 1)); /* inclusive */ S_028208_BR_X(maxx - 1) | S_028208_BR_Y(maxy - 1)); /* inclusive */
gfx12_set_context_reg(R_028184_PA_SC_SCREEN_SCISSOR_BR, gfx12_set_context_reg(R_028184_PA_SC_SCREEN_SCISSOR_BR,
S_028034_BR_X(screen_scissor.width) | S_028034_BR_Y(screen_scissor.height)); S_028184_BR_X(screen_scissor.width) | S_028184_BR_Y(screen_scissor.height));
gfx12_end_context_regs(); gfx12_end_context_regs();
radeon_end(); radeon_end();
} else { } else {