2019-06-17 16:27:37 -07:00
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/*
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* Copyright © 2019 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <gtest/gtest.h>
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#include "nir.h"
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#include "nir_builder.h"
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class comparison_pre_test : public ::testing::Test {
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protected:
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comparison_pre_test()
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{
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2019-07-31 15:40:05 +03:00
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glsl_type_singleton_init_or_ref();
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2019-06-17 16:27:37 -07:00
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static const nir_shader_compiler_options options = { };
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2020-10-26 11:28:33 -07:00
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bld = nir_builder_init_simple_shader(MESA_SHADER_VERTEX, &options);
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2019-06-17 16:27:37 -07:00
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v1 = nir_imm_vec4(&bld, -2.0, -1.0, 1.0, 2.0);
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v2 = nir_imm_vec4(&bld, 2.0, 1.0, -1.0, -2.0);
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v3 = nir_imm_vec4(&bld, 3.0, 4.0, 5.0, 6.0);
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}
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~comparison_pre_test()
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{
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ralloc_free(bld.shader);
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2019-07-31 15:40:05 +03:00
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glsl_type_singleton_decref();
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2019-06-17 16:27:37 -07:00
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}
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struct nir_builder bld;
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nir_ssa_def *v1;
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nir_ssa_def *v2;
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nir_ssa_def *v3;
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const uint8_t xxxx[4] = { 0, 0, 0, 0 };
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const uint8_t wwww[4] = { 3, 3, 3, 3 };
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};
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TEST_F(comparison_pre_test, a_lt_b_vs_neg_a_plus_b)
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{
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/* Before:
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*
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* vec4 32 ssa_0 = load_const (-2.0, -1.0, 1.0, 2.0)
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* vec4 32 ssa_1 = load_const ( 2.0, 1.0, -1.0, -2.0)
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* vec4 32 ssa_2 = load_const ( 3.0, 4.0, 5.0, 6.0)
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* vec1 32 ssa_3 = load_const ( 1.0)
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* vec4 32 ssa_4 = fadd ssa_0, ssa_2
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* vec1 32 ssa_5 = mov ssa_4.x
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* vec1 1 ssa_6 = flt ssa_5, ssa_3
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*
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* if ssa_6 {
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* vec1 32 ssa_7 = fneg ssa_5
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* vec1 32 ssa_8 = fadd ssa_7, ssa_3
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* } else {
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* }
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*
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* After:
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*
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* vec4 32 ssa_0 = load_const (-2.0, -1.0, 1.0, 2.0)
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* vec4 32 ssa_1 = load_const ( 2.0, 1.0, -1.0, -2.0)
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* vec4 32 ssa_2 = load_const ( 3.0, 4.0, 5.0, 6.0)
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* vec1 32 ssa_3 = load_const ( 1.0)
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* vec4 32 ssa_4 = fadd ssa_0, ssa_2
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* vec1 32 ssa_5 = mov ssa_4.x
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* vec1 32 ssa_9 = fneg ssa_5
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* vec1 32 ssa_10 = fadd ssa_3, ssa_9
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* vec1 32 ssa_11 = load_const (0.0)
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* vec1 1 ssa_12 = flt ssa_11, ssa_10
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* vec1 32 ssa_13 = mov ssa_10
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* vec1 1 ssa_14 = mov ssa_12
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*
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* if ssa_14 {
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* vec1 32 ssa_7 = fneg ssa_5
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* } else {
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* }
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*/
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nir_ssa_def *one = nir_imm_float(&bld, 1.0f);
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nir_ssa_def *a = nir_channel(&bld, nir_fadd(&bld, v1, v3), 0);
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nir_ssa_def *flt = nir_flt(&bld, a, one);
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nir_if *nif = nir_push_if(&bld, flt);
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nir_fadd(&bld, nir_fneg(&bld, a), one);
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nir_pop_if(&bld, nif);
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EXPECT_TRUE(nir_opt_comparison_pre_impl(bld.impl));
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}
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TEST_F(comparison_pre_test, a_lt_b_vs_a_minus_b)
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{
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/* Before:
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*
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* vec4 32 ssa_0 = load_const (-2.0, -1.0, 1.0, 2.0)
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* vec4 32 ssa_1 = load_const ( 2.0, 1.0, -1.0, -2.0)
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* vec4 32 ssa_2 = load_const ( 3.0, 4.0, 5.0, 6.0)
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* vec1 32 ssa_3 = load_const ( 1.0)
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* vec4 32 ssa_4 = fadd ssa_0, ssa_2
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* vec1 32 ssa_5 = mov ssa_4.x
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* vec1 1 ssa_6 = flt ssa_3, ssa_5
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*
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* if ssa_6 {
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* vec1 32 ssa_7 = fneg ssa_5
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* vec1 32 ssa_8 = fadd ssa_3, ssa_7
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* } else {
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* }
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*
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* After:
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*
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* vec4 32 ssa_0 = load_const (-2.0, -1.0, 1.0, 2.0)
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* vec4 32 ssa_1 = load_const ( 2.0, 1.0, -1.0, -2.0)
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* vec4 32 ssa_2 = load_const ( 3.0, 4.0, 5.0, 6.0)
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* vec1 32 ssa_3 = load_const ( 1.0)
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* vec4 32 ssa_4 = fadd ssa_0, ssa_2
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* vec1 32 ssa_5 = mov ssa_4.x
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* vec1 32 ssa_9 = fneg ssa_5
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* vec1 32 ssa_10 = fadd ssa_3, ssa_9
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* vec1 32 ssa_11 = load_const (0.0)
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* vec1 1 ssa_12 = flt ssa_10, ssa_11
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* vec1 32 ssa_13 = mov ssa_10
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* vec1 1 ssa_14 = mov ssa_12
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*
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* if ssa_14 {
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* vec1 32 ssa_7 = fneg ssa_5
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* } else {
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* }
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*/
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nir_ssa_def *one = nir_imm_float(&bld, 1.0f);
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nir_ssa_def *b = nir_channel(&bld, nir_fadd(&bld, v1, v3), 0);
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nir_ssa_def *flt = nir_flt(&bld, one, b);
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nir_if *nif = nir_push_if(&bld, flt);
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nir_fadd(&bld, one, nir_fneg(&bld, b));
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nir_pop_if(&bld, nif);
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EXPECT_TRUE(nir_opt_comparison_pre_impl(bld.impl));
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}
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TEST_F(comparison_pre_test, neg_a_lt_b_vs_a_plus_b)
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{
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/* Before:
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*
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* vec4 32 ssa_0 = load_const (-2.0, -1.0, 1.0, 2.0)
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* vec4 32 ssa_1 = load_const ( 2.0, 1.0, -1.0, -2.0)
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* vec4 32 ssa_2 = load_const ( 3.0, 4.0, 5.0, 6.0)
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* vec1 32 ssa_3 = load_const ( 1.0)
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* vec4 32 ssa_4 = fadd ssa_0, ssa_2
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* vec1 32 ssa_5 = mov ssa_4.x
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* vec1 32 ssa_6 = fneg ssa_5
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* vec1 1 ssa_7 = flt ssa_6, ssa_3
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*
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* if ssa_7 {
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* vec1 32 ssa_8 = fadd ssa_5, ssa_3
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* } else {
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* }
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*
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* After:
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*
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* vec4 32 ssa_0 = load_const (-2.0, -1.0, 1.0, 2.0)
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* vec4 32 ssa_1 = load_const ( 2.0, 1.0, -1.0, -2.0)
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* vec4 32 ssa_2 = load_const ( 3.0, 4.0, 5.0, 6.0)
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* vec1 32 ssa_3 = load_const ( 1.0)
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* vec4 32 ssa_4 = fadd ssa_0, ssa_2
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* vec1 32 ssa_5 = mov ssa_4.x
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* vec1 32 ssa_9 = fneg ssa_5
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* vec1 32 ssa_9 = fneg ssa_6
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* vec1 32 ssa_10 = fadd ssa_3, ssa_9
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* vec1 32 ssa_11 = load_const ( 0.0)
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* vec1 1 ssa_12 = flt ssa_11, ssa_10
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* vec1 32 ssa_13 = mov ssa_10
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* vec1 1 ssa_14 = mov ssa_12
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*
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* if ssa_14 {
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* } else {
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* }
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*/
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nir_ssa_def *one = nir_imm_float(&bld, 1.0f);
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nir_ssa_def *a = nir_channel(&bld, nir_fadd(&bld, v1, v3), 0);
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nir_ssa_def *flt = nir_flt(&bld, nir_fneg(&bld, a), one);
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nir_if *nif = nir_push_if(&bld, flt);
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nir_fadd(&bld, a, one);
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nir_pop_if(&bld, nif);
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EXPECT_TRUE(nir_opt_comparison_pre_impl(bld.impl));
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}
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TEST_F(comparison_pre_test, a_lt_neg_b_vs_a_plus_b)
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{
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/* Before:
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*
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* vec4 32 ssa_0 = load_const (-2.0, -1.0, 1.0, 2.0)
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* vec4 32 ssa_1 = load_const ( 2.0, 1.0, -1.0, -2.0)
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* vec4 32 ssa_2 = load_const ( 3.0, 4.0, 5.0, 6.0)
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* vec1 32 ssa_3 = load_const ( 1.0)
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* vec4 32 ssa_4 = fadd ssa_0, ssa_2
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* vec1 32 ssa_5 = mov ssa_4.x
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* vec1 32 ssa_6 = fneg ssa_5
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* vec1 1 ssa_7 = flt ssa_3, ssa_6
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*
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* if ssa_7 {
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* vec1 32 ssa_8 = fadd ssa_3, ssa_5
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* } else {
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* }
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*
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* After:
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*
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* vec4 32 ssa_0 = load_const (-2.0, -1.0, 1.0, 2.0)
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* vec4 32 ssa_1 = load_const ( 2.0, 1.0, -1.0, -2.0)
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* vec4 32 ssa_2 = load_const ( 3.0, 4.0, 5.0, 6.0)
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* vec1 32 ssa_3 = load_const ( 1.0)
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* vec4 32 ssa_4 = fadd ssa_0, ssa_2
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* vec1 32 ssa_5 = mov ssa_4.x
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* vec1 32 ssa_9 = fneg ssa_5
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* vec1 32 ssa_9 = fneg ssa_6
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* vec1 32 ssa_10 = fadd ssa_3, ssa_9
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* vec1 32 ssa_11 = load_const ( 0.0)
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* vec1 1 ssa_12 = flt ssa_10, ssa_11
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* vec1 32 ssa_13 = mov ssa_10
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* vec1 1 ssa_14 = mov ssa_12
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*
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* if ssa_14 {
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* } else {
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* }
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*/
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nir_ssa_def *one = nir_imm_float(&bld, 1.0f);
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nir_ssa_def *b = nir_channel(&bld, nir_fadd(&bld, v1, v3), 0);
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nir_ssa_def *flt = nir_flt(&bld, one, nir_fneg(&bld, b));
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nir_if *nif = nir_push_if(&bld, flt);
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nir_fadd(&bld, one, b);
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nir_pop_if(&bld, nif);
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EXPECT_TRUE(nir_opt_comparison_pre_impl(bld.impl));
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}
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2019-06-13 14:19:11 -07:00
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TEST_F(comparison_pre_test, imm_lt_b_vs_neg_imm_plus_b)
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{
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/* Before:
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*
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* vec4 32 ssa_0 = load_const (-2.0, -1.0, 1.0, 2.0)
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* vec4 32 ssa_1 = load_const ( 2.0, 1.0, -1.0, -2.0)
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* vec4 32 ssa_2 = load_const ( 3.0, 4.0, 5.0, 6.0)
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* vec1 32 ssa_3 = load_const ( 1.0)
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* vec1 32 ssa_4 = load_const (-1.0)
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* vec4 32 ssa_5 = fadd ssa_0, ssa_2
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* vec1 32 ssa_6 = mov ssa_5.x
|
|
|
|
|
* vec1 1 ssa_7 = flt ssa_3, ssa_6
|
|
|
|
|
*
|
|
|
|
|
* if ssa_7 {
|
|
|
|
|
* vec1 32 ssa_8 = fadd ssa_4, ssa_6
|
|
|
|
|
* } else {
|
|
|
|
|
* }
|
|
|
|
|
*
|
|
|
|
|
* After:
|
|
|
|
|
*
|
|
|
|
|
* vec4 32 ssa_0 = load_const (-2.0, -1.0, 1.0, 2.0)
|
|
|
|
|
* vec4 32 ssa_1 = load_const ( 2.0, 1.0, -1.0, -2.0)
|
|
|
|
|
* vec4 32 ssa_2 = load_const ( 3.0, 4.0, 5.0, 6.0)
|
|
|
|
|
* vec1 32 ssa_3 = load_const ( 1.0)
|
|
|
|
|
* vec1 32 ssa_4 = load_const (-1.0)
|
|
|
|
|
* vec4 32 ssa_5 = fadd ssa_0, ssa_2
|
|
|
|
|
* vec1 32 ssa_6 = mov ssa_5.x
|
|
|
|
|
* vec1 32 ssa_9 = fneg ssa_3
|
|
|
|
|
* vec1 32 ssa_10 = fadd ssa_6, ssa_9
|
|
|
|
|
* vec1 32 ssa_11 = load_const ( 0.0)
|
|
|
|
|
* vec1 1 ssa_12 = flt ssa_11, ssa_10
|
|
|
|
|
* vec1 32 ssa_13 = mov ssa_10
|
|
|
|
|
* vec1 1 ssa_14 = mov ssa_12
|
|
|
|
|
*
|
|
|
|
|
* if ssa_14 {
|
|
|
|
|
* } else {
|
|
|
|
|
* }
|
|
|
|
|
*/
|
|
|
|
|
nir_ssa_def *one = nir_imm_float(&bld, 1.0f);
|
|
|
|
|
nir_ssa_def *neg_one = nir_imm_float(&bld, -1.0f);
|
|
|
|
|
nir_ssa_def *a = nir_channel(&bld, nir_fadd(&bld, v1, v3), 0);
|
|
|
|
|
|
|
|
|
|
nir_ssa_def *flt = nir_flt(&bld, one, a);
|
|
|
|
|
|
|
|
|
|
nir_if *nif = nir_push_if(&bld, flt);
|
|
|
|
|
|
|
|
|
|
nir_fadd(&bld, neg_one, a);
|
|
|
|
|
|
|
|
|
|
nir_pop_if(&bld, nif);
|
|
|
|
|
|
|
|
|
|
EXPECT_TRUE(nir_opt_comparison_pre_impl(bld.impl));
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
TEST_F(comparison_pre_test, a_lt_imm_vs_a_minus_imm)
|
|
|
|
|
{
|
|
|
|
|
/* Before:
|
|
|
|
|
*
|
|
|
|
|
* vec4 32 ssa_0 = load_const (-2.0, -1.0, 1.0, 2.0)
|
|
|
|
|
* vec4 32 ssa_1 = load_const ( 2.0, 1.0, -1.0, -2.0)
|
|
|
|
|
* vec4 32 ssa_2 = load_const ( 3.0, 4.0, 5.0, 6.0)
|
|
|
|
|
* vec1 32 ssa_3 = load_const ( 1.0)
|
|
|
|
|
* vec1 32 ssa_4 = load_const (-1.0)
|
|
|
|
|
* vec4 32 ssa_5 = fadd ssa_0, ssa_2
|
|
|
|
|
* vec1 32 ssa_6 = mov ssa_5.x
|
|
|
|
|
* vec1 1 ssa_7 = flt ssa_6, ssa_3
|
|
|
|
|
*
|
|
|
|
|
* if ssa_6 {
|
|
|
|
|
* vec1 32 ssa_8 = fadd ssa_6, ssa_4
|
|
|
|
|
* } else {
|
|
|
|
|
* }
|
|
|
|
|
*
|
|
|
|
|
* After:
|
|
|
|
|
*
|
|
|
|
|
* vec4 32 ssa_0 = load_const (-2.0, -1.0, 1.0, 2.0)
|
|
|
|
|
* vec4 32 ssa_1 = load_const ( 2.0, 1.0, -1.0, -2.0)
|
|
|
|
|
* vec4 32 ssa_2 = load_const ( 3.0, 4.0, 5.0, 6.0)
|
|
|
|
|
* vec1 32 ssa_3 = load_const ( 1.0)
|
|
|
|
|
* vec1 32 ssa_4 = load_const (-1.0)
|
|
|
|
|
* vec4 32 ssa_5 = fadd ssa_0, ssa_2
|
|
|
|
|
* vec1 32 ssa_6 = mov ssa_5.x
|
|
|
|
|
* vec1 32 ssa_9 = fneg ssa_3
|
|
|
|
|
* vec1 32 ssa_10 = fadd ssa_6, ssa_9
|
|
|
|
|
* vec1 32 ssa_11 = load_const ( 0.0)
|
|
|
|
|
* vec1 1 ssa_12 = flt ssa_10, ssa_11
|
|
|
|
|
* vec1 32 ssa_13 = mov ssa_10
|
|
|
|
|
* vec1 1 ssa_14 = mov ssa_12
|
|
|
|
|
*
|
|
|
|
|
* if ssa_14 {
|
|
|
|
|
* } else {
|
|
|
|
|
* }
|
|
|
|
|
*/
|
|
|
|
|
nir_ssa_def *one = nir_imm_float(&bld, 1.0f);
|
|
|
|
|
nir_ssa_def *neg_one = nir_imm_float(&bld, -1.0f);
|
|
|
|
|
nir_ssa_def *a = nir_channel(&bld, nir_fadd(&bld, v1, v3), 0);
|
|
|
|
|
|
|
|
|
|
nir_ssa_def *flt = nir_flt(&bld, a, one);
|
|
|
|
|
|
|
|
|
|
nir_if *nif = nir_push_if(&bld, flt);
|
|
|
|
|
|
|
|
|
|
nir_fadd(&bld, a, neg_one);
|
|
|
|
|
|
|
|
|
|
nir_pop_if(&bld, nif);
|
|
|
|
|
|
|
|
|
|
EXPECT_TRUE(nir_opt_comparison_pre_impl(bld.impl));
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
TEST_F(comparison_pre_test, neg_imm_lt_a_vs_a_plus_imm)
|
|
|
|
|
{
|
|
|
|
|
/* Before:
|
|
|
|
|
*
|
|
|
|
|
* vec4 32 ssa_0 = load_const (-2.0, -1.0, 1.0, 2.0)
|
|
|
|
|
* vec4 32 ssa_1 = load_const ( 2.0, 1.0, -1.0, -2.0)
|
|
|
|
|
* vec4 32 ssa_2 = load_const ( 3.0, 4.0, 5.0, 6.0)
|
|
|
|
|
* vec1 32 ssa_3 = load_const ( 1.0)
|
|
|
|
|
* vec1 32 ssa_4 = load_const (-1.0)
|
|
|
|
|
* vec4 32 ssa_5 = fadd ssa_0, ssa_2
|
|
|
|
|
* vec1 32 ssa_6 = mov ssa_5.x
|
|
|
|
|
* vec1 1 ssa_7 = flt ssa_4, ssa_6
|
|
|
|
|
*
|
|
|
|
|
* if ssa_7 {
|
|
|
|
|
* vec1 32 ssa_8 = fadd ssa_6, ssa_3
|
|
|
|
|
* } else {
|
|
|
|
|
* }
|
|
|
|
|
*
|
|
|
|
|
* After:
|
|
|
|
|
*
|
|
|
|
|
* vec4 32 ssa_0 = load_const (-2.0, -1.0, 1.0, 2.0)
|
|
|
|
|
* vec4 32 ssa_1 = load_const ( 2.0, 1.0, -1.0, -2.0)
|
|
|
|
|
* vec4 32 ssa_2 = load_const ( 3.0, 4.0, 5.0, 6.0)
|
|
|
|
|
* vec1 32 ssa_3 = load_const ( 1.0)
|
|
|
|
|
* vec1 32 ssa_4 = load_const (-1.0)
|
|
|
|
|
* vec4 32 ssa_5 = fadd ssa_0, ssa_2
|
|
|
|
|
* vec1 32 ssa_6 = mov ssa_5.x
|
|
|
|
|
* vec1 32 ssa_9 = fneg ssa_4
|
|
|
|
|
* vec1 32 ssa_10 = fadd ssa_6, ssa_9
|
|
|
|
|
* vec1 32 ssa_11 = load_const ( 0.0)
|
|
|
|
|
* vec1 1 ssa_12 = flt ssa_11, ssa_10
|
|
|
|
|
* vec1 32 ssa_13 = mov ssa_10
|
|
|
|
|
* vec1 1 ssa_14 = mov ssa_12
|
|
|
|
|
*
|
|
|
|
|
* if ssa_14 {
|
|
|
|
|
* } else {
|
|
|
|
|
* }
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
nir_ssa_def *one = nir_imm_float(&bld, 1.0f);
|
|
|
|
|
nir_ssa_def *neg_one = nir_imm_float(&bld, -1.0f);
|
|
|
|
|
nir_ssa_def *a = nir_channel(&bld, nir_fadd(&bld, v1, v3), 0);
|
|
|
|
|
|
|
|
|
|
nir_ssa_def *flt = nir_flt(&bld, neg_one, a);
|
|
|
|
|
|
|
|
|
|
nir_if *nif = nir_push_if(&bld, flt);
|
|
|
|
|
|
|
|
|
|
nir_fadd(&bld, a, one);
|
|
|
|
|
|
|
|
|
|
nir_pop_if(&bld, nif);
|
|
|
|
|
|
|
|
|
|
EXPECT_TRUE(nir_opt_comparison_pre_impl(bld.impl));
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
TEST_F(comparison_pre_test, a_lt_neg_imm_vs_a_plus_imm)
|
|
|
|
|
{
|
|
|
|
|
/* Before:
|
|
|
|
|
*
|
|
|
|
|
* vec4 32 ssa_0 = load_const (-2.0, -1.0, 1.0, 2.0)
|
|
|
|
|
* vec4 32 ssa_1 = load_const ( 2.0, 1.0, -1.0, -2.0)
|
|
|
|
|
* vec4 32 ssa_2 = load_const ( 3.0, 4.0, 5.0, 6.0)
|
|
|
|
|
* vec1 32 ssa_3 = load_const ( 1.0)
|
|
|
|
|
* vec1 32 ssa_4 = load_const (-1.0)
|
|
|
|
|
* vec4 32 ssa_5 = fadd ssa_0, ssa_2
|
|
|
|
|
* vec1 32 ssa_6 = mov ssa_5.x
|
|
|
|
|
* vec1 1 ssa_7 = flt ssa_6, ssa_4
|
|
|
|
|
*
|
|
|
|
|
* if ssa_7 {
|
|
|
|
|
* vec1 32 ssa_8 = fadd ssa_6, ssa_3
|
|
|
|
|
* } else {
|
|
|
|
|
* }
|
|
|
|
|
*
|
|
|
|
|
* After:
|
|
|
|
|
*
|
|
|
|
|
* vec4 32 ssa_0 = load_const (-2.0, -1.0, 1.0, 2.0)
|
|
|
|
|
* vec4 32 ssa_1 = load_const ( 2.0, 1.0, -1.0, -2.0)
|
|
|
|
|
* vec4 32 ssa_2 = load_const ( 3.0, 4.0, 5.0, 6.0)
|
|
|
|
|
* vec1 32 ssa_3 = load_const ( 1.0)
|
|
|
|
|
* vec1 32 ssa_4 = load_const (-1.0)
|
|
|
|
|
* vec4 32 ssa_5 = fadd ssa_0, ssa_2
|
|
|
|
|
* vec1 32 ssa_6 = mov ssa_5.x
|
|
|
|
|
* vec1 32 ssa_9 = fneg ssa_4
|
|
|
|
|
* vec1 32 ssa_10 = fadd ssa_6, ssa_9
|
|
|
|
|
* vec1 32 ssa_11 = load_const ( 0.0)
|
|
|
|
|
* vec1 1 ssa_12 = flt ssa_10, ssa_11
|
|
|
|
|
* vec1 32 ssa_13 = mov ssa_10
|
|
|
|
|
* vec1 1 ssa_14 = mov ssa_12
|
|
|
|
|
*
|
|
|
|
|
* if ssa_14 {
|
|
|
|
|
* } else {
|
|
|
|
|
* }
|
|
|
|
|
*/
|
|
|
|
|
nir_ssa_def *one = nir_imm_float(&bld, 1.0f);
|
|
|
|
|
nir_ssa_def *neg_one = nir_imm_float(&bld, -1.0f);
|
|
|
|
|
nir_ssa_def *a = nir_channel(&bld, nir_fadd(&bld, v1, v3), 0);
|
|
|
|
|
|
|
|
|
|
nir_ssa_def *flt = nir_flt(&bld, a, neg_one);
|
|
|
|
|
|
|
|
|
|
nir_if *nif = nir_push_if(&bld, flt);
|
|
|
|
|
|
|
|
|
|
nir_fadd(&bld, a, one);
|
|
|
|
|
|
|
|
|
|
nir_pop_if(&bld, nif);
|
|
|
|
|
|
|
|
|
|
EXPECT_TRUE(nir_opt_comparison_pre_impl(bld.impl));
|
|
|
|
|
}
|
|
|
|
|
|
nir: Handle swizzle in nir_alu_srcs_negative_equal
When I added this function, I was not sure if swizzles of immediate
values were a thing that occurred in NIR. The only existing user of
these functions is the partial redundancy elimination for compares.
Since comparison instructions are inherently scalar, this does not
occur.
However, a couple later patches, "nir/algebraic: Recognize
open-coded flrp(-1, 1, a) and flrp(1, -1, a)" combined with "intel/vec4:
Try to emit a single load for multiple 3-src instruction operands",
collaborate to create a few thousand instances.
No shader-db changes on any Intel platform.
v2: Handle the swizzle in nir_alu_srcs_negative_equal and leave
nir_const_value_negative_equal unchanged. Suggested by Jason.
v3: Correctly handle write masks. Add note (and assertion) that the
caller is responsible for various compatibility checks. The single
existing caller only calls this for combinations of scalar fadd and
float comparison instructions, so all of the requirements are met. A
later patch (intel/vec4: Try to emit a single load for multiple 3-src
instruction operands) will call this for sources of the same
instruction, so all of the requirements are met.
v4: Add unit test for nir_opt_comparison_pre that is fixed by this
commit.
Reviewed-by: Matt Turner <mattst88@gmail.com>
2019-06-10 15:05:14 -07:00
|
|
|
TEST_F(comparison_pre_test, swizzle_of_same_immediate_vector)
|
|
|
|
|
{
|
|
|
|
|
/* Before:
|
|
|
|
|
*
|
|
|
|
|
* vec4 32 ssa_0 = load_const (-2.0, -1.0, 1.0, 2.0)
|
|
|
|
|
* vec4 32 ssa_1 = load_const ( 2.0, 1.0, -1.0, -2.0)
|
|
|
|
|
* vec4 32 ssa_2 = load_const ( 3.0, 4.0, 5.0, 6.0)
|
|
|
|
|
* vec4 32 ssa_3 = fadd ssa_0, ssa_2
|
|
|
|
|
* vec1 1 ssa_4 = flt ssa_0.x, ssa_3.x
|
|
|
|
|
*
|
|
|
|
|
* if ssa_4 {
|
|
|
|
|
* vec1 32 ssa_5 = fadd ssa_0.w, ssa_3.x
|
|
|
|
|
* } else {
|
|
|
|
|
* }
|
|
|
|
|
*/
|
|
|
|
|
nir_ssa_def *a = nir_fadd(&bld, v1, v3);
|
|
|
|
|
|
|
|
|
|
nir_alu_instr *flt = nir_alu_instr_create(bld.shader, nir_op_flt);
|
|
|
|
|
|
|
|
|
|
flt->src[0].src = nir_src_for_ssa(v1);
|
|
|
|
|
flt->src[1].src = nir_src_for_ssa(a);
|
|
|
|
|
|
|
|
|
|
memcpy(&flt->src[0].swizzle, xxxx, sizeof(xxxx));
|
|
|
|
|
memcpy(&flt->src[1].swizzle, xxxx, sizeof(xxxx));
|
|
|
|
|
|
|
|
|
|
nir_builder_alu_instr_finish_and_insert(&bld, flt);
|
|
|
|
|
|
|
|
|
|
flt->dest.dest.ssa.num_components = 1;
|
|
|
|
|
flt->dest.write_mask = 1;
|
|
|
|
|
|
|
|
|
|
nir_if *nif = nir_push_if(&bld, &flt->dest.dest.ssa);
|
|
|
|
|
|
|
|
|
|
nir_alu_instr *fadd = nir_alu_instr_create(bld.shader, nir_op_fadd);
|
|
|
|
|
|
|
|
|
|
fadd->src[0].src = nir_src_for_ssa(v1);
|
|
|
|
|
fadd->src[1].src = nir_src_for_ssa(a);
|
|
|
|
|
|
|
|
|
|
memcpy(&fadd->src[0].swizzle, wwww, sizeof(wwww));
|
|
|
|
|
memcpy(&fadd->src[1].swizzle, xxxx, sizeof(xxxx));
|
|
|
|
|
|
|
|
|
|
nir_builder_alu_instr_finish_and_insert(&bld, fadd);
|
|
|
|
|
|
|
|
|
|
fadd->dest.dest.ssa.num_components = 1;
|
|
|
|
|
fadd->dest.write_mask = 1;
|
|
|
|
|
|
|
|
|
|
nir_pop_if(&bld, nif);
|
|
|
|
|
|
|
|
|
|
EXPECT_TRUE(nir_opt_comparison_pre_impl(bld.impl));
|
|
|
|
|
}
|
|
|
|
|
|
2019-06-17 16:27:37 -07:00
|
|
|
TEST_F(comparison_pre_test, non_scalar_add_result)
|
|
|
|
|
{
|
|
|
|
|
/* The optimization pass should not do anything because the result of the
|
|
|
|
|
* fadd is not a scalar.
|
|
|
|
|
*
|
|
|
|
|
* Before:
|
|
|
|
|
*
|
|
|
|
|
* vec4 32 ssa_0 = load_const (-2.0, -1.0, 1.0, 2.0)
|
|
|
|
|
* vec4 32 ssa_1 = load_const ( 2.0, 1.0, -1.0, -2.0)
|
|
|
|
|
* vec4 32 ssa_2 = load_const ( 3.0, 4.0, 5.0, 6.0)
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* vec4 32 ssa_3 = fadd ssa_0, ssa_2
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* vec1 1 ssa_4 = flt ssa_0.x, ssa_3.x
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*
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* if ssa_4 {
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* vec2 32 ssa_5 = fadd ssa_1.xx, ssa_3.xx
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* } else {
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* }
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*
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* After:
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*
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* No change.
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*/
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nir_ssa_def *a = nir_fadd(&bld, v1, v3);
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nir_alu_instr *flt = nir_alu_instr_create(bld.shader, nir_op_flt);
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flt->src[0].src = nir_src_for_ssa(v1);
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flt->src[1].src = nir_src_for_ssa(a);
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memcpy(&flt->src[0].swizzle, xxxx, sizeof(xxxx));
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memcpy(&flt->src[1].swizzle, xxxx, sizeof(xxxx));
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nir_builder_alu_instr_finish_and_insert(&bld, flt);
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flt->dest.dest.ssa.num_components = 1;
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flt->dest.write_mask = 1;
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nir_if *nif = nir_push_if(&bld, &flt->dest.dest.ssa);
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nir_alu_instr *fadd = nir_alu_instr_create(bld.shader, nir_op_fadd);
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fadd->src[0].src = nir_src_for_ssa(v2);
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fadd->src[1].src = nir_src_for_ssa(a);
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memcpy(&fadd->src[0].swizzle, xxxx, sizeof(xxxx));
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memcpy(&fadd->src[1].swizzle, xxxx, sizeof(xxxx));
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nir_builder_alu_instr_finish_and_insert(&bld, fadd);
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fadd->dest.dest.ssa.num_components = 2;
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fadd->dest.write_mask = 3;
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nir_pop_if(&bld, nif);
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EXPECT_FALSE(nir_opt_comparison_pre_impl(bld.impl));
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}
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