2018-12-17 09:17:06 +01:00
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/*
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* Copyright © 2018 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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2023-11-01 12:51:33 -07:00
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#include "intel_nir.h"
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2018-12-17 09:17:06 +01:00
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#include "compiler/nir/nir_builder.h"
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static void
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2022-11-01 17:47:20 -07:00
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split_conversion(nir_builder *b, nir_alu_instr *alu, nir_alu_type src_type,
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2023-10-04 14:34:39 +01:00
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nir_alu_type tmp_type, nir_alu_type dst_type)
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2018-12-17 09:17:06 +01:00
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{
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b->cursor = nir_before_instr(&alu->instr);
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2023-08-12 16:17:15 -04:00
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nir_def *src = nir_ssa_for_alu_src(b, alu, 0);
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nir_def *tmp = nir_type_convert(b, src, src_type, tmp_type, nir_rounding_mode_undef);
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2023-10-04 14:34:39 +01:00
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nir_def *res = nir_type_convert(b, tmp, tmp_type, dst_type, nir_rounding_mode_undef);
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2024-06-20 12:07:26 -04:00
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nir_def_replace(&alu->def, res);
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2018-12-17 09:17:06 +01:00
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}
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static bool
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2021-08-06 13:58:06 +02:00
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lower_alu_instr(nir_builder *b, nir_alu_instr *alu)
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2018-12-17 09:17:06 +01:00
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{
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unsigned src_bit_size = nir_src_bit_size(alu->src[0].src);
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nir_alu_type src_type = nir_op_infos[alu->op].input_types[0];
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nir_alu_type src_full_type = (nir_alu_type) (src_type | src_bit_size);
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2023-08-14 11:43:35 -05:00
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unsigned dst_bit_size = alu->def.bit_size;
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2018-12-17 09:17:06 +01:00
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nir_alu_type dst_full_type = nir_op_infos[alu->op].output_type;
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nir_alu_type dst_type = nir_alu_type_get_base_type(dst_full_type);
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/* BDW PRM, vol02, Command Reference Instructions, mov - MOVE:
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*
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* "There is no direct conversion from HF to DF or DF to HF.
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* Use two instructions and F (Float) as an intermediate type.
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*
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* There is no direct conversion from HF to Q/UQ or Q/UQ to HF.
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* Use two instructions and F (Float) or a word integer type
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* or a DWord integer type as an intermediate type."
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*
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* It is important that the intermediate conversion happens through a
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* 32-bit float type so we don't lose range when we convert from
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* a 64-bit integer.
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*/
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2023-10-04 14:34:39 +01:00
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unsigned int64_types = nir_type_int64 | nir_type_uint64;
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if ((src_full_type == nir_type_float16 && (dst_full_type & int64_types)) ||
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((src_full_type & int64_types) && dst_full_type == nir_type_float16)) {
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2022-11-01 17:47:20 -07:00
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split_conversion(b, alu, src_type, nir_type_float | 32,
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2023-10-04 14:34:39 +01:00
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dst_type | dst_bit_size);
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2018-12-17 09:17:06 +01:00
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return true;
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}
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/* SKL PRM, vol 02a, Command Reference: Instructions, Move:
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*
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* "There is no direct conversion from B/UB to DF or DF to B/UB. Use
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* two instructions and a word or DWord intermediate type."
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*
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* "There is no direct conversion from B/UB to Q/UQ or Q/UQ to B/UB.
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* Use two instructions and a word or DWord intermediate integer
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* type."
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*
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* It is important that we use a 32-bit integer matching the sign of the
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* destination as the intermediate type so we avoid any chance of rtne
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* rounding happening before the conversion to integer (which is expected
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* to round towards zero) in double to byte conversions.
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*/
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if ((src_bit_size == 8 && dst_bit_size == 64) ||
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(src_bit_size == 64 && dst_bit_size == 8)) {
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2023-10-04 14:34:39 +01:00
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split_conversion(b, alu, src_type, dst_type | 32, dst_type | dst_bit_size);
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2018-12-17 09:17:06 +01:00
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return true;
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}
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return false;
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}
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static bool
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2021-08-06 13:58:06 +02:00
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lower_instr(nir_builder *b, nir_instr *instr, UNUSED void *cb_data)
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2018-12-17 09:17:06 +01:00
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{
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2021-08-06 13:58:06 +02:00
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if (instr->type != nir_instr_type_alu)
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return false;
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2018-12-17 09:17:06 +01:00
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2021-08-06 13:58:06 +02:00
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nir_alu_instr *alu = nir_instr_as_alu(instr);
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2018-12-17 09:17:06 +01:00
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2021-08-06 13:58:06 +02:00
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if (!nir_op_infos[alu->op].is_conversion)
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return false;
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2018-12-17 09:17:06 +01:00
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2021-08-06 13:58:06 +02:00
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return lower_alu_instr(b, alu);
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2018-12-17 09:17:06 +01:00
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}
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bool
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2023-11-01 15:15:43 -07:00
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intel_nir_lower_conversions(nir_shader *shader)
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2018-12-17 09:17:06 +01:00
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{
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2021-08-06 13:58:06 +02:00
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return nir_shader_instructions_pass(shader, lower_instr,
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2024-06-16 16:32:01 -04:00
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nir_metadata_control_flow,
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2021-08-06 13:58:06 +02:00
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NULL);
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2018-12-17 09:17:06 +01:00
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}
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