2016-10-07 09:16:09 +10:00
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/*
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* Copyright 2014 Advanced Micro Devices, Inc.
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*
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2023-05-18 17:22:27 -04:00
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* SPDX-License-Identifier: MIT
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2016-10-07 09:16:09 +10:00
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*/
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2017-03-20 16:04:04 +00:00
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#ifndef AC_BINARY_H
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#define AC_BINARY_H
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2016-10-07 09:16:09 +10:00
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2020-09-07 09:58:36 +02:00
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#include <stdbool.h>
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2018-05-22 13:29:27 +02:00
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#include <stddef.h>
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2016-10-07 09:16:09 +10:00
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#include <stdint.h>
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2018-07-04 01:11:47 -04:00
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#ifdef __cplusplus
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extern "C" {
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#endif
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2020-01-28 23:35:49 -05:00
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struct radeon_info;
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2016-10-07 09:16:09 +10:00
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struct ac_shader_config {
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2020-09-07 09:58:36 +02:00
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unsigned num_sgprs;
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unsigned num_vgprs;
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unsigned num_shared_vgprs; /* GFX10: number of VGPRs shared between half-waves */
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unsigned spilled_sgprs;
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unsigned spilled_vgprs;
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unsigned lds_size; /* in HW allocation units; i.e 256 bytes on SI, 512 bytes on CI+ */
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unsigned spi_ps_input_ena;
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unsigned spi_ps_input_addr;
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unsigned float_mode;
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unsigned scratch_bytes_per_wave;
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unsigned rsrc1;
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unsigned rsrc2;
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unsigned rsrc3;
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2016-10-07 09:16:09 +10:00
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};
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2020-09-07 09:58:36 +02:00
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void ac_parse_shader_binary_config(const char *data, size_t nbytes, unsigned wave_size,
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2022-04-28 01:14:39 -04:00
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const struct radeon_info *info, struct ac_shader_config *conf);
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2017-03-20 16:04:04 +00:00
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2023-04-23 17:23:23 +08:00
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unsigned ac_align_shader_binary_for_prefetch(const struct radeon_info *info, unsigned size);
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2018-07-04 01:11:47 -04:00
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#ifdef __cplusplus
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}
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#endif
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2017-03-20 16:04:04 +00:00
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#endif /* AC_BINARY_H */
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