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8cc2d09c29
On GFX6-GFX12, except GFX9, SMEM loads on NULL PRT pages would just fault and hang the GPU. The better workaround that we found is to split the address space in two equal parts "LOW"/"HIGH", here's more details: To workaround that, the driver splits the total VA space in half, so that a single bit controls whether it's the "HIGH" or the "LOW" address space. Every sparse residency buffer allocations that might be used with SMEM get two allocations: - the "HIGH" address space is mapped normally and its VA is returned to the application. - the "LOW" address space is explicitly mapped to a zero-initialized buffer when it's allocated or when it's unmapped. Other buffer allocations are always allocated in the "LOW" address. The driver also creates a zero-allocated BO that will be used to map partially resident buffers at creation and when explicitly unmapped. The size is arbitrary but it seems that allocating 8MiB is perfectly reasonable and fast enough in most cases. This BO is marked as read-only for the GPU because the backend compilers don't use SMEM stores. For example this makes the "LOW" half of the HIGH VA range like [0xffff800100000000,0xffffbfffffbfe000], and the "HIGH" half is left for PRT. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
55 lines
1.8 KiB
C
55 lines
1.8 KiB
C
/*
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* Copyright 2014 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef _UTIL_MATH_H_
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#define _UTIL_MATH_H_
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#define MIN2( A, B ) ( (A)<(B) ? (A) : (B) )
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#define MAX2( A, B ) ( (A)>(B) ? (A) : (B) )
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#define MAX3( A, B, C ) ((A) > (B) ? MAX2(A, C) : MAX2(B, C))
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#define __align_mask(value, mask) (((value) + (mask)) & ~(mask))
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#define ALIGN(value, alignment) __align_mask(value, (__typeof__(value))((alignment) - 1))
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static inline unsigned
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util_last_bit64(uint64_t u)
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{
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#if defined(HAVE___BUILTIN_CLZLL)
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return u == 0 ? 0 : 64 - __builtin_clzll(u);
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#elif defined(_MSC_VER) && (_M_AMD64 || _M_ARM64 || _M_IA64)
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unsigned long index;
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if (_BitScanReverse64(&index, u))
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return index + 1;
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else
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return 0;
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#else
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unsigned r = 0;
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while (u) {
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r++;
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u >>= 1;
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}
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return r;
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#endif
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}
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#endif /*_UTIL_MATH_H_*/
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