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404 lines
13 KiB
C
404 lines
13 KiB
C
/* r128_drv.h -- Private header for r128 driver -*- linux-c -*-
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* Created: Mon Dec 13 09:51:11 1999 by faith@precisioninsight.com
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*
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* Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
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* Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
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* All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*
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* Authors: Rickard E. (Rik) Faith <faith@valinux.com>
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* Kevin E. Martin <martin@valinux.com>
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*
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*/
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#ifndef _R128_DRV_H_
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#define _R128_DRV_H_
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typedef struct drm_r128_freelist {
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unsigned int age;
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drm_buf_t *buf;
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struct drm_r128_freelist *next;
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struct drm_r128_freelist *prev;
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} drm_r128_freelist_t;
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typedef struct drm_r128_ring_buffer {
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__volatile__ u32 *read_ptr;
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u32 start;
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u32 end;
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int size;
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int size_l2qw;
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u32 *virtual_start;
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int head;
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int tail;
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u32 tail_mask;
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int space;
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} drm_r128_ring_buffer_t;
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typedef struct drm_r128_private {
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__volatile__ u32 *ring_read_ptr;
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drm_r128_sarea_t *sarea_priv;
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u32 *ring_start;
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u32 *ring_end;
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int ring_size;
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int ring_sizel2qw;
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int ring_entries;
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int cce_mode;
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int cce_fifo_size;
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int cce_is_bm_mode;
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int cce_secure;
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u32 *cce_buffer;
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drm_r128_freelist_t *head;
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drm_r128_freelist_t *tail;
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unsigned int submit_age;
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int usec_timeout;
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int is_pci;
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drm_map_t *sarea;
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drm_map_t *fb;
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drm_map_t *agp_ring;
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drm_map_t *agp_read_ptr;
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drm_map_t *agp_vertbufs;
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drm_map_t *agp_indbufs;
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drm_map_t *agp_textures;
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drm_map_t *mmio;
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} drm_r128_private_t;
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typedef struct drm_r128_buf_priv {
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u32 age;
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int discard;
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int dispatched;
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drm_r128_freelist_t *my_freelist;
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} drm_r128_buf_priv_t;
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/* r128_drv.c */
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extern int r128_version(struct inode *inode, struct file *filp,
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unsigned int cmd, unsigned long arg);
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extern int r128_open(struct inode *inode, struct file *filp);
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extern int r128_release(struct inode *inode, struct file *filp);
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extern int r128_ioctl(struct inode *inode, struct file *filp,
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unsigned int cmd, unsigned long arg);
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extern int r128_lock(struct inode *inode, struct file *filp,
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unsigned int cmd, unsigned long arg);
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extern int r128_unlock(struct inode *inode, struct file *filp,
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unsigned int cmd, unsigned long arg);
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/* r128_dma.c */
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extern int r128_init_cce(struct inode *inode, struct file *filp,
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unsigned int cmd, unsigned long arg);
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extern int r128_eng_reset(struct inode *inode, struct file *filp,
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unsigned int cmd, unsigned long arg);
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extern int r128_eng_flush(struct inode *inode, struct file *filp,
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unsigned int cmd, unsigned long arg);
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extern int r128_cce_packet(struct inode *inode, struct file *filp,
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unsigned int cmd, unsigned long arg);
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extern int r128_cce_idle(struct inode *inode, struct file *filp,
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unsigned int cmd, unsigned long arg);
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extern void r128_flush_write_combine( void );
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extern int r128_do_wait_for_idle( drm_r128_private_t *dev_priv );
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extern int r128_do_submit_packet( drm_r128_private_t *dev_priv,
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u32 *buffer, int count );
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extern drm_buf_t *r128_freelist_get( drm_device_t *dev );
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/* r128_state.c */
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extern int r128_cce_vertex(struct inode *inode, struct file *filp,
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unsigned int cmd, unsigned long arg);
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/* r128_bufs.c */
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extern int r128_addbufs(struct inode *inode, struct file *filp,
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unsigned int cmd, unsigned long arg);
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extern int r128_mapbufs(struct inode *inode, struct file *filp,
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unsigned int cmd, unsigned long arg);
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/* r128_context.c */
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extern int r128_resctx(struct inode *inode, struct file *filp,
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unsigned int cmd, unsigned long arg);
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extern int r128_addctx(struct inode *inode, struct file *filp,
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unsigned int cmd, unsigned long arg);
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extern int r128_modctx(struct inode *inode, struct file *filp,
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unsigned int cmd, unsigned long arg);
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extern int r128_getctx(struct inode *inode, struct file *filp,
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unsigned int cmd, unsigned long arg);
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extern int r128_switchctx(struct inode *inode, struct file *filp,
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unsigned int cmd, unsigned long arg);
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extern int r128_newctx(struct inode *inode, struct file *filp,
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unsigned int cmd, unsigned long arg);
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extern int r128_rmctx(struct inode *inode, struct file *filp,
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unsigned int cmd, unsigned long arg);
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extern int r128_context_switch(drm_device_t *dev, int old, int new);
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extern int r128_context_switch_complete(drm_device_t *dev, int new);
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/* Register definitions, register access macros and drmAddMap constants
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* for Rage 128 kernel driver.
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*/
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#define R128_AUX_SC_CNTL 0x1660
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# define R128_AUX1_SC_EN (1 << 0)
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# define R128_AUX1_SC_MODE_OR (0 << 1)
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# define R128_AUX1_SC_MODE_NAND (1 << 1)
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# define R128_AUX2_SC_EN (1 << 2)
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# define R128_AUX2_SC_MODE_OR (0 << 3)
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# define R128_AUX2_SC_MODE_NAND (1 << 3)
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# define R128_AUX3_SC_EN (1 << 4)
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# define R128_AUX3_SC_MODE_OR (0 << 5)
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# define R128_AUX3_SC_MODE_NAND (1 << 5)
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#define R128_AUX1_SC_LEFT 0x1664
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#define R128_AUX1_SC_RIGHT 0x1668
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#define R128_AUX1_SC_TOP 0x166c
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#define R128_AUX1_SC_BOTTOM 0x1670
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#define R128_AUX2_SC_LEFT 0x1674
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#define R128_AUX2_SC_RIGHT 0x1678
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#define R128_AUX2_SC_TOP 0x167c
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#define R128_AUX2_SC_BOTTOM 0x1680
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#define R128_AUX3_SC_LEFT 0x1684
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#define R128_AUX3_SC_RIGHT 0x1688
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#define R128_AUX3_SC_TOP 0x168c
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#define R128_AUX3_SC_BOTTOM 0x1690
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#define R128_CLOCK_CNTL_INDEX 0x0008
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#define R128_CLOCK_CNTL_DATA 0x000c
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# define R128_PLL_WR_EN (1 << 7)
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#define R128_CONSTANT_COLOR_C 0x1d34
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#define R128_DP_WRITE_MASK 0x16cc
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#define R128_DST_PITCH_OFFSET_C 0x1c80
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#define R128_GEN_RESET_CNTL 0x00f0
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# define R128_SOFT_RESET_GUI (1 << 0)
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#define R128_GUI_SCRATCH_REG0 0x15e0
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#define R128_GUI_SCRATCH_REG1 0x15e4
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#define R128_GUI_SCRATCH_REG2 0x15e8
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#define R128_GUI_SCRATCH_REG3 0x15ec
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#define R128_GUI_SCRATCH_REG4 0x15f0
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#define R128_GUI_SCRATCH_REG5 0x15f4
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#define R128_GUI_STAT 0x1740
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# define R128_GUI_FIFOCNT_MASK 0x0fff
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# define R128_GUI_ACTIVE (1 << 31)
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#define R128_MCLK_CNTL 0x000f
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# define R128_FORCE_GCP (1 << 16)
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# define R128_FORCE_PIPE3D_CP (1 << 17)
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# define R128_FORCE_RCP (1 << 18)
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#define R128_PC_NGUI_CTLSTAT 0x0184
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# define R128_PC_FLUSH_ALL 0x00ff
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# define R128_PC_BUSY (1 << 31)
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#define R128_PM4_BUFFER_CNTL 0x0704
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# define R128_PM4_NONPM4 (0 << 28)
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# define R128_PM4_192PIO (1 << 28)
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# define R128_PM4_192BM (2 << 28)
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# define R128_PM4_128PIO_64INDBM (3 << 28)
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# define R128_PM4_128BM_64INDBM (4 << 28)
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# define R128_PM4_64PIO_128INDBM (5 << 28)
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# define R128_PM4_64BM_128INDBM (6 << 28)
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# define R128_PM4_64PIO_64VCBM_64INDBM (7 << 28)
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# define R128_PM4_64BM_64VCBM_64INDBM (8 << 28)
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# define R128_PM4_64PIO_64VCPIO_64INDPIO (15 << 28)
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#define R128_PM4_BUFFER_DL_RPTR 0x0710
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#define R128_PM4_BUFFER_DL_WPTR 0x0714
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# define R128_PM4_BUFFER_DL_DONE (1 << 31)
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#define R128_PM4_VC_FPU_SETUP 0x071c
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#define R128_PM4_STAT 0x07b8
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# define R128_PM4_FIFOCNT_MASK 0x0fff
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# define R128_PM4_BUSY (1 << 16)
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# define R128_PM4_GUI_ACTIVE (1 << 31)
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#define R128_PM4_BUFFER_ADDR 0x07f0
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#define R128_PM4_MICRO_CNTL 0x07fc
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# define R128_PM4_MICRO_FREERUN (1 << 30)
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#define R128_PM4_FIFO_DATA_EVEN 0x1000
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#define R128_PM4_FIFO_DATA_ODD 0x1004
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#define R128_PRIM_TEX_CNTL_C 0x1cb0
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#define R128_SCALE_3D_CNTL 0x1a00
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#define R128_SEC_TEX_CNTL_C 0x1d00
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#define R128_SEC_TEXTURE_BORDER_COLOR_C 0x1d3c
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#define R128_SETUP_CNTL 0x1bc4
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#define R128_STEN_REF_MASK_C 0x1d40
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#define R128_TEX_CNTL_C 0x1c9c
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# define R128_TEX_CACHE_FLUSH (1 << 23)
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#define R128_WINDOW_XY_OFFSET 0x1bcc
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/* CCE command packets
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*/
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#define R128_CCE_PACKET0 0x00000000
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#define R128_CCE_PACKET1 0x40000000
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#define R128_CCE_PACKET2 0x80000000
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#define R128_CCE_PACKET3 0xC0000000
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# define R128_3D_RNDR_GEN_INDX_PRIM 0x00002300
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#define R128_CCE_PACKET_MASK 0xC0000000
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#define R128_CCE_PACKET_COUNT_MASK 0x3fff0000
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#define R128_CCE_PACKET0_REG_MASK 0x000007ff
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#define R128_CCE_PACKET1_REG0_MASK 0x000007ff
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#define R128_CCE_PACKET1_REG1_MASK 0x003ff800
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#define R128_CCE_VC_CNTL_PRIM_TYPE_NONE 0x00000000
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#define R128_CCE_VC_CNTL_PRIM_TYPE_POINT 0x00000001
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#define R128_CCE_VC_CNTL_PRIM_TYPE_LINE 0x00000002
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#define R128_CCE_VC_CNTL_PRIM_TYPE_POLY_LINE 0x00000003
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#define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_LIST 0x00000004
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#define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_FAN 0x00000005
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#define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_STRIP 0x00000006
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#define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_TYPE2 0x00000007
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#define R128_CCE_VC_CNTL_PRIM_WALK_IND 0x00000010
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#define R128_CCE_VC_CNTL_PRIM_WALK_LIST 0x00000020
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#define R128_CCE_VC_CNTL_PRIM_WALK_RING 0x00000030
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#define R128_CCE_VC_CNTL_NUM_SHIFT 16
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#define R128_MAX_USEC_TIMEOUT 100000 /* 100 ms */
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#define R128_MAX_VB_AGE 0xffffffff
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#define R128_VB_AGE_REG R128_GUI_SCRATCH_REG0
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#define R128_BASE(reg) ((unsigned long)(dev_priv->mmio->handle))
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#define R128_ADDR(reg) (R128_BASE(reg) + reg)
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#define R128_DEREF(reg) *(__volatile__ int *)R128_ADDR(reg)
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#define R128_READ(reg) R128_DEREF(reg)
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#define R128_WRITE(reg,val) do { R128_DEREF(reg) = val; } while (0)
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#define R128_DEREF8(reg) *(__volatile__ char *)R128_ADDR(reg)
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#define R128_READ8(reg) R128_DEREF8(reg)
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#define R128_WRITE8(reg,val) do { R128_DEREF8(reg) = val; } while (0)
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#define R128_WRITE_PLL(addr,val) \
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do { \
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R128_WRITE8(R128_CLOCK_CNTL_INDEX, ((addr) & 0x1f) | R128_PLL_WR_EN); \
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R128_WRITE(R128_CLOCK_CNTL_DATA, (val)); \
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} while (0)
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extern int R128_READ_PLL(drm_device_t *dev, int addr);
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#define R128CCE0(p,r,n) ((p) | ((n) << 16) | ((r) >> 2))
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#define R128CCE1(p,r1,r2) ((p) | (((r2) >> 2) << 11) | ((r1) >> 2))
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#define R128CCE2(p) ((p))
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#define R128CCE3(p,n) ((p) | ((n) << 16))
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#define CCE_PACKET0( reg, n ) (R128_CCE_PACKET0 | \
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((n) << 16) | ((reg) >> 2))
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#define CCE_PACKET1( reg0, reg1 ) (R128_CCE_PACKET1 | \
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(((reg1) >> 2) << 11) | ((reg0) >> 2))
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#define CCE_PACKET2() (R128_CCE_PACKET2)
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#define CCE_PACKET3( pkt, n ) (R128_CCE_PACKET3 | \
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(pkt) | ((n) << 16))
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#define R128_VERBOSE 0
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#if 0
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#define RING_LOCALS unsigned long outring, ringmask; volatile u32 *virt;
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#define BEGIN_RING( n ) do { \
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if ( R128_VERBOSE ) { \
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DRM_DEBUG( "BEGIN_RING( %d ) in %s\n", \
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n, __FUNCTION__ ); \
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} \
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if ( dev_priv->ring.space < n * sizeof(u32) ) { \
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r128_wait_ring( dev_priv, n * sizeof(u32) ); \
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} \
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dev_priv->ring.space -= n * sizeof(u32); \
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outring = dev_priv->ring.tail; \
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ringmask = dev_priv->ring.tail_mask; \
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virt = dev_priv->->ring.virtual_start; \
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} while (0)
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#define ADVANCE_RING() do { \
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if ( R128_VERBOSE ) { \
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DRM_DEBUG( "ADVANCE_RING()\n" ); \
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} \
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dev_priv->sarea_priv->ring_write = write;
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R128_WRITE( R128_PM4_BUFFER_DL_WPTR, write );
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__ret = r128_do_submit_packet( dev_priv, buffer, outring ); \
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if ( __ret < 0 ) { \
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DRM_ERROR( "ADVANCE_RING fucked up!\n" ); \
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} \
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} while (0)
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#define OUT_RING( x ) do { \
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if ( R128_VERBOSE ) { \
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DRM_DEBUG( " OUT_RING( 0x%08x )\n", \
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(unsigned int)(x) ); \
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} \
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buffer[outring++] = x; \
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} while (0)
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#else
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#define RING_LOCALS unsigned long outring; u32 *buffer; int __ret;
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#define BEGIN_RING( n ) do { \
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if ( R128_VERBOSE ) { \
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DRM_DEBUG( "BEGIN_RING( %d ) in %s\n", \
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n, __FUNCTION__ ); \
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} \
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outring = 0; \
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buffer = dev_priv->cce_buffer; \
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} while (0)
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#define ADVANCE_RING() do { \
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if ( R128_VERBOSE ) { \
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DRM_DEBUG( "ADVANCE_RING()\n" ); \
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} \
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__ret = r128_do_submit_packet( dev_priv, buffer, outring ); \
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if ( __ret < 0 ) { \
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DRM_ERROR( "ADVANCE_RING fucked up!\n" ); \
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} \
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} while (0)
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#define OUT_RING( x ) do { \
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if ( R128_VERBOSE ) { \
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DRM_DEBUG( " OUT_RING( 0x%08x )\n", \
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(unsigned int)(x) ); \
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} \
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buffer[outring++] = x; \
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} while (0)
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#endif
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#endif
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