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https://gitlab.freedesktop.org/mesa/drm.git
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674cefd4fe
The PGRAPH init for the various cards will need cleaning up at some point, a lot of the values written there are per-context state left over from the all the hardcoding done in the ddx. It's possible some cards get broken by this commit, let me know. Tested on: NV5, NV18, NV28, NV35, NV40, NV4E
56 lines
1 KiB
C
56 lines
1 KiB
C
#include "drmP.h"
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#include "drm.h"
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#include "nouveau_drv.h"
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#include "nouveau_drm.h"
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int
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nv40_fb_init(drm_device_t *dev)
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{
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drm_nouveau_private_t *dev_priv = dev->dev_private;
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uint32_t fb_bar_size, tmp;
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int num_tiles;
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int i;
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switch (dev_priv->chipset) {
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case 0x40:
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case 0x45:
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tmp = NV_READ(NV10_PFB_CLOSE_PAGE2);
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NV_WRITE(NV10_PFB_CLOSE_PAGE2, tmp & ~(1<<15));
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num_tiles = NV10_PFB_TILE__SIZE;
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break;
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case 0x46: /* G72 */
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case 0x47: /* G70 */
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case 0x49: /* G71 */
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case 0x4b: /* G73 */
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case 0x4c: /* C51 (G7X version) */
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num_tiles = NV40_PFB_TILE__SIZE_1;
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break;
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default:
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num_tiles = NV40_PFB_TILE__SIZE_0;
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break;
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}
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fb_bar_size = drm_get_resource_len(dev, 0) - 1;
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switch (dev_priv->chipset) {
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case 0x40:
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for (i=0; i<num_tiles; i++) {
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NV_WRITE(NV10_PFB_TILE(i), 0);
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NV_WRITE(NV10_PFB_TLIMIT(i), fb_bar_size);
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}
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break;
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default:
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for (i=0; i<num_tiles; i++) {
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NV_WRITE(NV40_PFB_TILE(i), 0);
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NV_WRITE(NV40_PFB_TLIMIT(i), fb_bar_size);
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}
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break;
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}
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return 0;
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}
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void
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nv40_fb_takedown(drm_device_t *dev)
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{
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}
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