mirror of
https://gitlab.freedesktop.org/mesa/drm.git
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2f2d8b9688
These two structures were used as the request and reply for certain ioctls. Having a different type for an ioctl's input and output is just wierd. In addition, each structure contained fields (e.g., pid) that had no business being there. This change requires updates to user-space.
351 lines
11 KiB
C
351 lines
11 KiB
C
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/****************************************************************************
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* Copyright (C) 2003-2006 by XGI Technology, Taiwan.
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* *
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* All Rights Reserved. *
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* *
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* Permission is hereby granted, free of charge, to any person obtaining
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* a copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation on the rights to use, copy, modify, merge,
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* publish, distribute, sublicense, and/or sell copies of the Software,
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* and to permit persons to whom the Software is furnished to do so,
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* subject to the following conditions:
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* *
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial
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* portions of the Software.
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* *
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NON-INFRINGEMENT. IN NO EVENT SHALL XGI AND/OR
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* ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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***************************************************************************/
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#include "xgi_types.h"
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#include "xgi_linux.h"
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#include "xgi_drv.h"
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#include "xgi_regs.h"
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#include "xgi_misc.h"
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#include "xgi_cmdlist.h"
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struct xgi_cmdring_info s_cmdring;
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static void addFlush2D(struct xgi_info * info);
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static unsigned int getCurBatchBeginPort(struct xgi_cmd_info * pCmdInfo);
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static void triggerHWCommandList(struct xgi_info * info, U32 triggerCounter);
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static void xgi_cmdlist_reset(void);
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int xgi_cmdlist_initialize(struct xgi_info * info, size_t size)
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{
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struct xgi_mem_alloc mem_alloc = {
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.size = size,
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.owner = PCIE_2D,
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};
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xgi_pcie_alloc(info, &mem_alloc, 0);
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if ((mem_alloc.size == 0) && (mem_alloc.hw_addr == 0)) {
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return -1;
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}
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s_cmdring._cmdRingSize = mem_alloc.size;
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s_cmdring._cmdRingBuffer = mem_alloc.hw_addr;
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s_cmdring._cmdRingBusAddr = mem_alloc.bus_addr;
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s_cmdring._lastBatchStartAddr = 0;
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s_cmdring._cmdRingOffset = 0;
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return 1;
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}
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void xgi_submit_cmdlist(struct xgi_info * info, struct xgi_cmd_info * pCmdInfo)
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{
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unsigned int beginPort;
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/** XGI_INFO("Jong-xgi_submit_cmdlist-Begin \n"); **/
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/* Jong 05/25/2006 */
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/* return; */
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beginPort = getCurBatchBeginPort(pCmdInfo);
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XGI_INFO("Jong-xgi_submit_cmdlist-After getCurBatchBeginPort() \n");
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/* Jong 05/25/2006 */
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/* return; */
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if (s_cmdring._lastBatchStartAddr == 0) {
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unsigned int portOffset;
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/* Jong 06/13/2006; remove marked for system hang test */
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/* xgi_waitfor_pci_idle(info); */
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/* Jong 06132006; BASE_3D_ENG=0x2800 */
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/* beginPort: 2D: 0x30 */
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portOffset = BASE_3D_ENG + beginPort;
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// Enable PCI Trigger Mode
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XGI_INFO("Jong-xgi_submit_cmdlist-Enable PCI Trigger Mode \n");
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/* Jong 05/25/2006 */
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/* return; */
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/* Jong 06/13/2006; M2REG_AUTO_LINK_SETTING_ADDRESS=0x10 */
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XGI_INFO("Jong-M2REG_AUTO_LINK_SETTING_ADDRESS=0x%lx \n",
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M2REG_AUTO_LINK_SETTING_ADDRESS);
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XGI_INFO("Jong-M2REG_CLEAR_COUNTERS_MASK=0x%lx \n",
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M2REG_CLEAR_COUNTERS_MASK);
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XGI_INFO
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("Jong-(M2REG_AUTO_LINK_SETTING_ADDRESS << 22)=0x%lx \n",
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(M2REG_AUTO_LINK_SETTING_ADDRESS << 22));
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XGI_INFO("Jong-M2REG_PCI_TRIGGER_MODE_MASK=0x%lx \n\n",
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M2REG_PCI_TRIGGER_MODE_MASK);
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/* Jong 06/14/2006; 0x400001a */
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XGI_INFO
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("Jong-(M2REG_AUTO_LINK_SETTING_ADDRESS << 22)|M2REG_CLEAR_COUNTERS_MASK|0x08|M2REG_PCI_TRIGGER_MODE_MASK=0x%lx \n",
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(M2REG_AUTO_LINK_SETTING_ADDRESS << 22) |
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M2REG_CLEAR_COUNTERS_MASK | 0x08 |
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M2REG_PCI_TRIGGER_MODE_MASK);
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dwWriteReg(BASE_3D_ENG + M2REG_AUTO_LINK_SETTING_ADDRESS,
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(M2REG_AUTO_LINK_SETTING_ADDRESS << 22) |
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M2REG_CLEAR_COUNTERS_MASK | 0x08 |
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M2REG_PCI_TRIGGER_MODE_MASK);
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/* Jong 05/25/2006 */
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XGI_INFO("Jong-xgi_submit_cmdlist-After dwWriteReg() \n");
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/* return; *//* OK */
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/* Jong 06/14/2006; 0x400000a */
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XGI_INFO
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("Jong-(M2REG_AUTO_LINK_SETTING_ADDRESS << 22)|0x08|M2REG_PCI_TRIGGER_MODE_MASK=0x%lx \n",
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(M2REG_AUTO_LINK_SETTING_ADDRESS << 22) | 0x08 |
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M2REG_PCI_TRIGGER_MODE_MASK);
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dwWriteReg(BASE_3D_ENG + M2REG_AUTO_LINK_SETTING_ADDRESS,
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(M2REG_AUTO_LINK_SETTING_ADDRESS << 22) | 0x08 |
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M2REG_PCI_TRIGGER_MODE_MASK);
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// Send PCI begin command
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XGI_INFO("Jong-xgi_submit_cmdlist-Send PCI begin command \n");
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/* return; */
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XGI_INFO("Jong-xgi_submit_cmdlist-portOffset=%d \n",
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portOffset);
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XGI_INFO("Jong-xgi_submit_cmdlist-beginPort=%d \n", beginPort);
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/* beginPort = 48; */
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/* 0xc100000 */
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dwWriteReg(portOffset,
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(beginPort << 22) + (BEGIN_VALID_MASK) +
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pCmdInfo->_curDebugID);
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XGI_INFO("Jong-(beginPort<<22)=0x%lx \n", (beginPort << 22));
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XGI_INFO("Jong-(BEGIN_VALID_MASK)=0x%lx \n", BEGIN_VALID_MASK);
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XGI_INFO("Jong- pCmdInfo->_curDebugID=0x%lx \n",
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pCmdInfo->_curDebugID);
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XGI_INFO
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("Jong- (beginPort<<22) + (BEGIN_VALID_MASK) + pCmdInfo->_curDebugID=0x%lx \n",
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(beginPort << 22) + (BEGIN_VALID_MASK) +
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pCmdInfo->_curDebugID);
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XGI_INFO
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("Jong-xgi_submit_cmdlist-Send PCI begin command- After \n");
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/* return; *//* OK */
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/* 0x80000024 */
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dwWriteReg(portOffset + 4,
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BEGIN_LINK_ENABLE_MASK + pCmdInfo->_firstSize);
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XGI_INFO("Jong- BEGIN_LINK_ENABLE_MASK=0x%lx \n",
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BEGIN_LINK_ENABLE_MASK);
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XGI_INFO("Jong- pCmdInfo->_firstSize=0x%lx \n",
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pCmdInfo->_firstSize);
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XGI_INFO
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("Jong- BEGIN_LINK_ENABLE_MASK + pCmdInfo->_firstSize=0x%lx \n",
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BEGIN_LINK_ENABLE_MASK + pCmdInfo->_firstSize);
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XGI_INFO("Jong-xgi_submit_cmdlist-dwWriteReg-1 \n");
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/* 0x1010000 */
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dwWriteReg(portOffset + 8, (pCmdInfo->_firstBeginAddr >> 4));
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XGI_INFO("Jong- pCmdInfo->_firstBeginAddr=0x%lx \n",
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pCmdInfo->_firstBeginAddr);
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XGI_INFO("Jong- (pCmdInfo->_firstBeginAddr >> 4)=0x%lx \n",
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(pCmdInfo->_firstBeginAddr >> 4));
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XGI_INFO("Jong-xgi_submit_cmdlist-dwWriteReg-2 \n");
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/* Jong 06/13/2006 */
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xgi_dump_register(info);
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/* Jong 06/12/2006; system hang; marked for test */
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dwWriteReg(portOffset + 12, 0);
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XGI_INFO("Jong-xgi_submit_cmdlist-dwWriteReg-3 \n");
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/* Jong 06/13/2006; remove marked for system hang test */
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/* xgi_waitfor_pci_idle(info); */
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} else {
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U32 *lastBatchVirtAddr;
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XGI_INFO
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("Jong-xgi_submit_cmdlist-s_cmdring._lastBatchStartAddr != 0 \n");
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/* Jong 05/25/2006 */
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/* return; */
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if (pCmdInfo->_firstBeginType == BTYPE_3D) {
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addFlush2D(info);
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}
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lastBatchVirtAddr =
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(U32 *) xgi_find_pcie_virt(info,
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s_cmdring._lastBatchStartAddr);
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/* lastBatchVirtAddr should *never* be NULL. However, there
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* are currently some bugs that cause this to happen. The
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* if-statement here prevents some fatal (i.e., hard lock
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* requiring the reset button) oopses.
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*/
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if (lastBatchVirtAddr) {
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lastBatchVirtAddr[1] =
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BEGIN_LINK_ENABLE_MASK + pCmdInfo->_firstSize;
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lastBatchVirtAddr[2] = pCmdInfo->_firstBeginAddr >> 4;
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lastBatchVirtAddr[3] = 0;
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//barrier();
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lastBatchVirtAddr[0] =
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(beginPort << 22) + (BEGIN_VALID_MASK) +
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(0xffff & pCmdInfo->_curDebugID);
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/* Jong 06/12/2006; system hang; marked for test */
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triggerHWCommandList(info, pCmdInfo->_beginCount);
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}
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XGI_INFO
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("Jong-xgi_submit_cmdlist-s_cmdring._lastBatchStartAddr != 0 - End\n");
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}
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s_cmdring._lastBatchStartAddr = pCmdInfo->_lastBeginAddr;
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XGI_INFO("Jong-xgi_submit_cmdlist-End \n");
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}
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/*
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state: 0 - console
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1 - graphic
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2 - fb
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3 - logout
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*/
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void xgi_state_change(struct xgi_info * info, struct xgi_state_info * pStateInfo)
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{
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#define STATE_CONSOLE 0
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#define STATE_GRAPHIC 1
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#define STATE_FBTERM 2
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#define STATE_LOGOUT 3
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#define STATE_REBOOT 4
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#define STATE_SHUTDOWN 5
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if ((pStateInfo->_fromState == STATE_GRAPHIC)
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&& (pStateInfo->_toState == STATE_CONSOLE)) {
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XGI_INFO("[kd] I see, now is to leaveVT\n");
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// stop to received batch
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} else if ((pStateInfo->_fromState == STATE_CONSOLE)
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&& (pStateInfo->_toState == STATE_GRAPHIC)) {
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XGI_INFO("[kd] I see, now is to enterVT\n");
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xgi_cmdlist_reset();
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} else if ((pStateInfo->_fromState == STATE_GRAPHIC)
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&& ((pStateInfo->_toState == STATE_LOGOUT)
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|| (pStateInfo->_toState == STATE_REBOOT)
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|| (pStateInfo->_toState == STATE_SHUTDOWN))) {
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XGI_INFO("[kd] I see, not is to exit from X\n");
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// stop to received batch
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} else {
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XGI_ERROR("[kd] Should not happen\n");
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}
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}
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void xgi_cmdlist_reset(void)
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{
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s_cmdring._lastBatchStartAddr = 0;
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s_cmdring._cmdRingOffset = 0;
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}
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void xgi_cmdlist_cleanup(struct xgi_info * info)
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{
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if (s_cmdring._cmdRingBuffer != 0) {
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xgi_pcie_free(info, s_cmdring._cmdRingBusAddr);
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s_cmdring._cmdRingBuffer = 0;
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s_cmdring._cmdRingOffset = 0;
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s_cmdring._cmdRingSize = 0;
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}
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}
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static void triggerHWCommandList(struct xgi_info * info, U32 triggerCounter)
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{
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static unsigned int s_triggerID = 1;
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//Fix me, currently we just trigger one time
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while (triggerCounter--) {
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dwWriteReg(BASE_3D_ENG + M2REG_PCI_TRIGGER_REGISTER_ADDRESS,
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0x05000000 + (0x0ffff & s_triggerID++));
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// xgi_waitfor_pci_idle(info);
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}
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}
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static unsigned int getCurBatchBeginPort(struct xgi_cmd_info * pCmdInfo)
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{
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// Convert the batch type to begin port ID
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switch (pCmdInfo->_firstBeginType) {
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case BTYPE_2D:
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return 0x30;
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case BTYPE_3D:
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return 0x40;
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case BTYPE_FLIP:
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return 0x50;
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case BTYPE_CTRL:
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return 0x20;
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default:
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//ASSERT(0);
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return 0xff;
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}
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}
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static void addFlush2D(struct xgi_info * info)
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{
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U32 *flushBatchVirtAddr;
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U32 flushBatchHWAddr;
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U32 *lastBatchVirtAddr;
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/* check buf is large enough to contain a new flush batch */
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if ((s_cmdring._cmdRingOffset + 0x20) >= s_cmdring._cmdRingSize) {
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s_cmdring._cmdRingOffset = 0;
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}
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flushBatchHWAddr = s_cmdring._cmdRingBuffer + s_cmdring._cmdRingOffset;
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flushBatchVirtAddr = (U32 *) xgi_find_pcie_virt(info, flushBatchHWAddr);
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/* not using memcpy for I assume the address is discrete */
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*(flushBatchVirtAddr + 0) = 0x10000000;
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*(flushBatchVirtAddr + 1) = 0x80000004; /* size = 0x04 dwords */
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*(flushBatchVirtAddr + 2) = 0x00000000;
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*(flushBatchVirtAddr + 3) = 0x00000000;
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*(flushBatchVirtAddr + 4) = FLUSH_2D;
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*(flushBatchVirtAddr + 5) = FLUSH_2D;
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*(flushBatchVirtAddr + 6) = FLUSH_2D;
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*(flushBatchVirtAddr + 7) = FLUSH_2D;
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// ASSERT(s_cmdring._lastBatchStartAddr != NULL);
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lastBatchVirtAddr =
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(U32 *) xgi_find_pcie_virt(info, s_cmdring._lastBatchStartAddr);
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lastBatchVirtAddr[1] = BEGIN_LINK_ENABLE_MASK + 0x08;
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lastBatchVirtAddr[2] = flushBatchHWAddr >> 4;
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lastBatchVirtAddr[3] = 0;
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//barrier();
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// BTYPE_CTRL & NO debugID
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lastBatchVirtAddr[0] = (0x20 << 22) + (BEGIN_VALID_MASK);
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triggerHWCommandList(info, 1);
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s_cmdring._cmdRingOffset += 0x20;
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s_cmdring._lastBatchStartAddr = flushBatchHWAddr;
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}
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