mirror of
https://gitlab.freedesktop.org/mesa/drm.git
synced 2025-12-27 10:30:17 +01:00
graphics objects: - No longer takes flags/dmaobj parameters, requires some major changes to the ddx to setup the object through the FIFO. This change is likely to cause breakages on some cards (tested on NV05,NV28,NV35, NV40 and NV4E). dma objects: - now takes a "class" parameter, not really used yet but we may need it at some point. - parameters are checked, so clients can't randomly create DMA objects pointing at whatever they feel like. misc: - Added FB_SIZE/AGP_SIZE getparams - Read PFIFO_INTR in PFIFO irq handler, not PMC_INTR - Dump PGRAPH trap info on PGRAPH_INTR_NOTIFY if NSOURCE isn't NOTIFICATION_PENDING.
247 lines
6.8 KiB
C
247 lines
6.8 KiB
C
/*
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* Copyright 2005 Stephane Marchesin
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include "drmP.h"
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#include "drm.h"
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#include "drm_sarea.h"
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#include "nouveau_drv.h"
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/* here a client dies, release the stuff that was allocated for its filp */
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void nouveau_preclose(drm_device_t * dev, DRMFILE filp)
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{
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drm_nouveau_private_t *dev_priv = dev->dev_private;
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nouveau_mem_release(filp,dev_priv->fb_heap);
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nouveau_mem_release(filp,dev_priv->agp_heap);
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nouveau_object_cleanup(dev, filp);
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nouveau_fifo_cleanup(dev, filp);
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}
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/* first module load, setup the mmio/fb mapping */
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int nouveau_firstopen(struct drm_device *dev)
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{
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int ret;
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drm_nouveau_private_t *dev_priv = dev->dev_private;
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/* resource 0 is mmio regs */
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/* resource 1 is linear FB */
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/* resource 2 is RAMIN (mmio regs + 0x1000000) */
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/* resource 6 is bios */
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/* map the mmio regs */
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ret = drm_addmap(dev, drm_get_resource_start(dev, 0), drm_get_resource_len(dev, 0),
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_DRM_REGISTERS, _DRM_READ_ONLY, &dev_priv->mmio);
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if (dev_priv->mmio)
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{
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DRM_INFO("regs mapped ok at 0x%lx\n",dev_priv->mmio->offset);
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}
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else
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{
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DRM_ERROR("Unable to initialize the mmio mapping. Please report your setup to " DRIVER_EMAIL "\n");
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return 1;
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}
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DRM_INFO("%lld MB of video ram detected\n",nouveau_mem_fb_amount(dev)>>20);
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/* map larger RAMIN aperture on NV40 cards */
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if (dev_priv->card_type >= NV_40) {
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int ramin_resource = 2;
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if (drm_get_resource_len(dev, ramin_resource) == 0)
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ramin_resource = 3;
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ret = drm_addmap(dev, drm_get_resource_start(dev, ramin_resource),
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drm_get_resource_len(dev, ramin_resource),
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_DRM_REGISTERS,
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_DRM_READ_ONLY,
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&dev_priv->ramin);
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if (ret) {
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DRM_ERROR("Failed to init RAMIN mapping, "
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"limited instance memory available\n");
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dev_priv->ramin = NULL;
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}
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} else
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dev_priv->ramin = NULL;
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/* Determine exact chipset we're running on */
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if (dev_priv->card_type < NV_10)
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dev_priv->chipset = dev_priv->card_type;
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else
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dev_priv->chipset =(NV_READ(NV03_PMC_BOOT_0) & 0x0ff00000) >> 20;
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/* Clear RAMIN
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* Determine locations for RAMHT/FC/RO
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* Initialise PFIFO
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*/
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ret = nouveau_fifo_init(dev);
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if (ret) return ret;
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/* setup a mtrr over the FB */
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dev_priv->fb_mtrr=drm_mtrr_add(drm_get_resource_start(dev, 1),nouveau_mem_fb_amount(dev), DRM_MTRR_WC);
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/* FIXME: doesn't belong here, and have no idea what it's for.. */
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if (dev_priv->card_type >= NV_40)
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nv40_graph_init(dev);
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else if (dev_priv->card_type >= NV_30)
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nv30_graph_init(dev);
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else if (dev_priv->card_type >= NV_20)
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nv20_graph_init(dev);
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else if (dev_priv->card_type >= NV_10)
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nv10_graph_init(dev);
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else if (dev_priv->card_type >= NV_04)
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nv04_graph_init(dev);
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return 0;
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}
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int nouveau_load(struct drm_device *dev, unsigned long flags)
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{
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drm_nouveau_private_t *dev_priv;
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if (flags==NV_UNKNOWN)
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return DRM_ERR(EINVAL);
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dev_priv = drm_alloc(sizeof(drm_nouveau_private_t), DRM_MEM_DRIVER);
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if (!dev_priv)
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return DRM_ERR(ENOMEM);
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memset(dev_priv, 0, sizeof(drm_nouveau_private_t));
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dev_priv->card_type=flags&NOUVEAU_FAMILY;
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dev_priv->flags=flags&NOUVEAU_FLAGS;
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dev->dev_private = (void *)dev_priv;
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return 0;
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}
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void nouveau_lastclose(struct drm_device *dev)
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{
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drm_nouveau_private_t *dev_priv = dev->dev_private;
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if(dev_priv->fb_mtrr>0)
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{
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drm_mtrr_del(dev_priv->fb_mtrr, drm_get_resource_start(dev, 1),nouveau_mem_fb_amount(dev), DRM_MTRR_WC);
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dev_priv->fb_mtrr=0;
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}
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}
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int nouveau_unload(struct drm_device *dev)
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{
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drm_free(dev->dev_private, sizeof(*dev->dev_private), DRM_MEM_DRIVER);
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dev->dev_private = NULL;
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return 0;
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}
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int nouveau_ioctl_getparam(DRM_IOCTL_ARGS)
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{
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DRM_DEVICE;
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drm_nouveau_private_t *dev_priv = dev->dev_private;
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drm_nouveau_getparam_t getparam;
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DRM_COPY_FROM_USER_IOCTL(getparam, (drm_nouveau_getparam_t __user *)data,
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sizeof(getparam));
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switch (getparam.param) {
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case NOUVEAU_GETPARAM_PCI_VENDOR:
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getparam.value=dev->pci_vendor;
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break;
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case NOUVEAU_GETPARAM_PCI_DEVICE:
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getparam.value=dev->pci_device;
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break;
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case NOUVEAU_GETPARAM_BUS_TYPE:
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if (drm_device_is_agp(dev))
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getparam.value=NV_AGP;
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else if (drm_device_is_pcie(dev))
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getparam.value=NV_PCIE;
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else
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getparam.value=NV_PCI;
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break;
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case NOUVEAU_GETPARAM_FB_PHYSICAL:
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getparam.value=dev_priv->fb_phys;
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break;
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case NOUVEAU_GETPARAM_AGP_PHYSICAL:
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getparam.value=dev_priv->agp_phys;
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break;
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case NOUVEAU_GETPARAM_FB_SIZE:
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getparam.value=dev_priv->fb_available_size;
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break;
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case NOUVEAU_GETPARAM_AGP_SIZE:
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getparam.value=dev_priv->agp_available_size;
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break;
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default:
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DRM_ERROR("unknown parameter %lld\n", getparam.param);
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return DRM_ERR(EINVAL);
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}
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DRM_COPY_TO_USER_IOCTL((drm_nouveau_getparam_t __user *)data, getparam,
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sizeof(getparam));
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return 0;
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}
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int nouveau_ioctl_setparam(DRM_IOCTL_ARGS)
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{
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DRM_DEVICE;
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drm_nouveau_private_t *dev_priv = dev->dev_private;
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drm_nouveau_setparam_t setparam;
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DRM_COPY_FROM_USER_IOCTL(setparam, (drm_nouveau_setparam_t __user *)data,
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sizeof(setparam));
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switch (setparam.param) {
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case NOUVEAU_SETPARAM_CMDBUF_LOCATION:
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switch (setparam.value) {
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case NOUVEAU_MEM_AGP:
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case NOUVEAU_MEM_FB:
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break;
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default:
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DRM_ERROR("invalid CMDBUF_LOCATION value=%lld\n",
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setparam.value);
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return DRM_ERR(EINVAL);
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}
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dev_priv->config.cmdbuf.location = setparam.value;
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break;
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case NOUVEAU_SETPARAM_CMDBUF_SIZE:
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dev_priv->config.cmdbuf.size = setparam.value;
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break;
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default:
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DRM_ERROR("unknown parameter %lld\n", setparam.param);
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return DRM_ERR(EINVAL);
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}
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return 0;
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}
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/* waits for idle */
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void nouveau_wait_for_idle(struct drm_device *dev)
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{
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drm_nouveau_private_t *dev_priv=dev->dev_private;
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switch(dev_priv->card_type)
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{
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case NV_03:
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while(NV_READ(NV03_PGRAPH_STATUS));
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break;
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default:
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while(NV_READ(NV04_PGRAPH_STATUS));
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break;
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}
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}
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