mirror of
https://gitlab.freedesktop.org/mesa/drm.git
synced 2025-12-20 07:00:11 +01:00
591c1d72ab
Whiskey Lake uses the same gen graphics as Coffe Lake, including some
ids that were previously marked as reserved on Coffe Lake, but that
now are moved to WHL page.
So, let's just move them to WHL macros that will feed into CFL macro
just to keep it better organized to make easier future code review
but it will be handled as a CFL.
This is a copy of merged i915's
commit b9be78531d27 ("drm/i915/whl: Introducing Whiskey Lake platform")
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
576 lines
22 KiB
C
576 lines
22 KiB
C
/*
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*
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* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sub license, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
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* IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
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* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef _INTEL_CHIPSET_H
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#define _INTEL_CHIPSET_H
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#define PCI_CHIP_I810 0x7121
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#define PCI_CHIP_I810_DC100 0x7123
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#define PCI_CHIP_I810_E 0x7125
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#define PCI_CHIP_I815 0x1132
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#define PCI_CHIP_I830_M 0x3577
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#define PCI_CHIP_845_G 0x2562
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#define PCI_CHIP_I855_GM 0x3582
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#define PCI_CHIP_I865_G 0x2572
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#define PCI_CHIP_I915_G 0x2582
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#define PCI_CHIP_E7221_G 0x258A
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#define PCI_CHIP_I915_GM 0x2592
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#define PCI_CHIP_I945_G 0x2772
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#define PCI_CHIP_I945_GM 0x27A2
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#define PCI_CHIP_I945_GME 0x27AE
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#define PCI_CHIP_Q35_G 0x29B2
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#define PCI_CHIP_G33_G 0x29C2
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#define PCI_CHIP_Q33_G 0x29D2
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#define PCI_CHIP_IGD_GM 0xA011
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#define PCI_CHIP_IGD_G 0xA001
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#define IS_IGDGM(devid) ((devid) == PCI_CHIP_IGD_GM)
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#define IS_IGDG(devid) ((devid) == PCI_CHIP_IGD_G)
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#define IS_IGD(devid) (IS_IGDG(devid) || IS_IGDGM(devid))
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#define PCI_CHIP_I965_G 0x29A2
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#define PCI_CHIP_I965_Q 0x2992
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#define PCI_CHIP_I965_G_1 0x2982
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#define PCI_CHIP_I946_GZ 0x2972
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#define PCI_CHIP_I965_GM 0x2A02
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#define PCI_CHIP_I965_GME 0x2A12
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#define PCI_CHIP_GM45_GM 0x2A42
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#define PCI_CHIP_IGD_E_G 0x2E02
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#define PCI_CHIP_Q45_G 0x2E12
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#define PCI_CHIP_G45_G 0x2E22
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#define PCI_CHIP_G41_G 0x2E32
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#define PCI_CHIP_ILD_G 0x0042
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#define PCI_CHIP_ILM_G 0x0046
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#define PCI_CHIP_SANDYBRIDGE_GT1 0x0102 /* desktop */
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#define PCI_CHIP_SANDYBRIDGE_GT2 0x0112
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#define PCI_CHIP_SANDYBRIDGE_GT2_PLUS 0x0122
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#define PCI_CHIP_SANDYBRIDGE_M_GT1 0x0106 /* mobile */
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#define PCI_CHIP_SANDYBRIDGE_M_GT2 0x0116
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#define PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS 0x0126
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#define PCI_CHIP_SANDYBRIDGE_S 0x010A /* server */
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#define PCI_CHIP_IVYBRIDGE_GT1 0x0152 /* desktop */
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#define PCI_CHIP_IVYBRIDGE_GT2 0x0162
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#define PCI_CHIP_IVYBRIDGE_M_GT1 0x0156 /* mobile */
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#define PCI_CHIP_IVYBRIDGE_M_GT2 0x0166
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#define PCI_CHIP_IVYBRIDGE_S 0x015a /* server */
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#define PCI_CHIP_IVYBRIDGE_S_GT2 0x016a /* server */
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#define PCI_CHIP_HASWELL_GT1 0x0402 /* Desktop */
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#define PCI_CHIP_HASWELL_GT2 0x0412
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#define PCI_CHIP_HASWELL_GT3 0x0422
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#define PCI_CHIP_HASWELL_M_GT1 0x0406 /* Mobile */
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#define PCI_CHIP_HASWELL_M_GT2 0x0416
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#define PCI_CHIP_HASWELL_M_GT3 0x0426
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#define PCI_CHIP_HASWELL_S_GT1 0x040A /* Server */
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#define PCI_CHIP_HASWELL_S_GT2 0x041A
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#define PCI_CHIP_HASWELL_S_GT3 0x042A
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#define PCI_CHIP_HASWELL_B_GT1 0x040B /* Reserved */
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#define PCI_CHIP_HASWELL_B_GT2 0x041B
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#define PCI_CHIP_HASWELL_B_GT3 0x042B
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#define PCI_CHIP_HASWELL_E_GT1 0x040E /* Reserved */
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#define PCI_CHIP_HASWELL_E_GT2 0x041E
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#define PCI_CHIP_HASWELL_E_GT3 0x042E
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#define PCI_CHIP_HASWELL_SDV_GT1 0x0C02 /* Desktop */
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#define PCI_CHIP_HASWELL_SDV_GT2 0x0C12
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#define PCI_CHIP_HASWELL_SDV_GT3 0x0C22
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#define PCI_CHIP_HASWELL_SDV_M_GT1 0x0C06 /* Mobile */
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#define PCI_CHIP_HASWELL_SDV_M_GT2 0x0C16
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#define PCI_CHIP_HASWELL_SDV_M_GT3 0x0C26
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#define PCI_CHIP_HASWELL_SDV_S_GT1 0x0C0A /* Server */
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#define PCI_CHIP_HASWELL_SDV_S_GT2 0x0C1A
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#define PCI_CHIP_HASWELL_SDV_S_GT3 0x0C2A
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#define PCI_CHIP_HASWELL_SDV_B_GT1 0x0C0B /* Reserved */
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#define PCI_CHIP_HASWELL_SDV_B_GT2 0x0C1B
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#define PCI_CHIP_HASWELL_SDV_B_GT3 0x0C2B
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#define PCI_CHIP_HASWELL_SDV_E_GT1 0x0C0E /* Reserved */
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#define PCI_CHIP_HASWELL_SDV_E_GT2 0x0C1E
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#define PCI_CHIP_HASWELL_SDV_E_GT3 0x0C2E
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#define PCI_CHIP_HASWELL_ULT_GT1 0x0A02 /* Desktop */
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#define PCI_CHIP_HASWELL_ULT_GT2 0x0A12
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#define PCI_CHIP_HASWELL_ULT_GT3 0x0A22
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#define PCI_CHIP_HASWELL_ULT_M_GT1 0x0A06 /* Mobile */
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#define PCI_CHIP_HASWELL_ULT_M_GT2 0x0A16
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#define PCI_CHIP_HASWELL_ULT_M_GT3 0x0A26
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#define PCI_CHIP_HASWELL_ULT_S_GT1 0x0A0A /* Server */
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#define PCI_CHIP_HASWELL_ULT_S_GT2 0x0A1A
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#define PCI_CHIP_HASWELL_ULT_S_GT3 0x0A2A
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#define PCI_CHIP_HASWELL_ULT_B_GT1 0x0A0B /* Reserved */
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#define PCI_CHIP_HASWELL_ULT_B_GT2 0x0A1B
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#define PCI_CHIP_HASWELL_ULT_B_GT3 0x0A2B
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#define PCI_CHIP_HASWELL_ULT_E_GT1 0x0A0E /* Reserved */
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#define PCI_CHIP_HASWELL_ULT_E_GT2 0x0A1E
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#define PCI_CHIP_HASWELL_ULT_E_GT3 0x0A2E
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#define PCI_CHIP_HASWELL_CRW_GT1 0x0D02 /* Desktop */
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#define PCI_CHIP_HASWELL_CRW_GT2 0x0D12
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#define PCI_CHIP_HASWELL_CRW_GT3 0x0D22
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#define PCI_CHIP_HASWELL_CRW_M_GT1 0x0D06 /* Mobile */
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#define PCI_CHIP_HASWELL_CRW_M_GT2 0x0D16
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#define PCI_CHIP_HASWELL_CRW_M_GT3 0x0D26
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#define PCI_CHIP_HASWELL_CRW_S_GT1 0x0D0A /* Server */
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#define PCI_CHIP_HASWELL_CRW_S_GT2 0x0D1A
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#define PCI_CHIP_HASWELL_CRW_S_GT3 0x0D2A
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#define PCI_CHIP_HASWELL_CRW_B_GT1 0x0D0B /* Reserved */
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#define PCI_CHIP_HASWELL_CRW_B_GT2 0x0D1B
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#define PCI_CHIP_HASWELL_CRW_B_GT3 0x0D2B
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#define PCI_CHIP_HASWELL_CRW_E_GT1 0x0D0E /* Reserved */
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#define PCI_CHIP_HASWELL_CRW_E_GT2 0x0D1E
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#define PCI_CHIP_HASWELL_CRW_E_GT3 0x0D2E
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#define BDW_SPARE 0x2
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#define BDW_ULT 0x6
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#define BDW_SERVER 0xa
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#define BDW_IRIS 0xb
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#define BDW_WORKSTATION 0xd
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#define BDW_ULX 0xe
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#define PCI_CHIP_VALLEYVIEW_PO 0x0f30 /* VLV PO board */
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#define PCI_CHIP_VALLEYVIEW_1 0x0f31
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#define PCI_CHIP_VALLEYVIEW_2 0x0f32
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#define PCI_CHIP_VALLEYVIEW_3 0x0f33
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#define PCI_CHIP_CHERRYVIEW_0 0x22b0
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#define PCI_CHIP_CHERRYVIEW_1 0x22b1
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#define PCI_CHIP_CHERRYVIEW_2 0x22b2
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#define PCI_CHIP_CHERRYVIEW_3 0x22b3
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#define PCI_CHIP_SKYLAKE_DT_GT1 0x1902
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#define PCI_CHIP_SKYLAKE_ULT_GT1 0x1906
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#define PCI_CHIP_SKYLAKE_SRV_GT1 0x190A /* Reserved */
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#define PCI_CHIP_SKYLAKE_H_GT1 0x190B
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#define PCI_CHIP_SKYLAKE_ULX_GT1 0x190E /* Reserved */
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#define PCI_CHIP_SKYLAKE_DT_GT2 0x1912
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#define PCI_CHIP_SKYLAKE_FUSED0_GT2 0x1913 /* Reserved */
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#define PCI_CHIP_SKYLAKE_FUSED1_GT2 0x1915 /* Reserved */
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#define PCI_CHIP_SKYLAKE_ULT_GT2 0x1916
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#define PCI_CHIP_SKYLAKE_FUSED2_GT2 0x1917 /* Reserved */
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#define PCI_CHIP_SKYLAKE_SRV_GT2 0x191A /* Reserved */
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#define PCI_CHIP_SKYLAKE_HALO_GT2 0x191B
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#define PCI_CHIP_SKYLAKE_WKS_GT2 0x191D
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#define PCI_CHIP_SKYLAKE_ULX_GT2 0x191E
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#define PCI_CHIP_SKYLAKE_MOBILE_GT2 0x1921 /* Reserved */
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#define PCI_CHIP_SKYLAKE_ULT_GT3_0 0x1923
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#define PCI_CHIP_SKYLAKE_ULT_GT3_1 0x1926
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#define PCI_CHIP_SKYLAKE_ULT_GT3_2 0x1927
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#define PCI_CHIP_SKYLAKE_SRV_GT4 0x192A
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#define PCI_CHIP_SKYLAKE_HALO_GT3 0x192B /* Reserved */
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#define PCI_CHIP_SKYLAKE_SRV_GT3 0x192D
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#define PCI_CHIP_SKYLAKE_DT_GT4 0x1932
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#define PCI_CHIP_SKYLAKE_SRV_GT4X 0x193A
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#define PCI_CHIP_SKYLAKE_H_GT4 0x193B
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#define PCI_CHIP_SKYLAKE_WKS_GT4 0x193D
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#define PCI_CHIP_KABYLAKE_ULT_GT2 0x5916
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#define PCI_CHIP_KABYLAKE_ULT_GT1_5 0x5913
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#define PCI_CHIP_KABYLAKE_ULT_GT1 0x5906
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#define PCI_CHIP_KABYLAKE_ULT_GT3_0 0x5923
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#define PCI_CHIP_KABYLAKE_ULT_GT3_1 0x5926
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#define PCI_CHIP_KABYLAKE_ULT_GT3_2 0x5927
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#define PCI_CHIP_KABYLAKE_ULT_GT2F 0x5921
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#define PCI_CHIP_KABYLAKE_ULX_GT1_5 0x5915
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#define PCI_CHIP_KABYLAKE_ULX_GT1 0x590E
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#define PCI_CHIP_KABYLAKE_ULX_GT2_0 0x591E
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#define PCI_CHIP_KABYLAKE_ULX_GT2_1 0x591C
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#define PCI_CHIP_KABYLAKE_DT_GT2 0x5912
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#define PCI_CHIP_KABYLAKE_M_GT2 0x5917
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#define PCI_CHIP_KABYLAKE_DT_GT1 0x5902
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#define PCI_CHIP_KABYLAKE_HALO_GT2 0x591B
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#define PCI_CHIP_KABYLAKE_HALO_GT4 0x593B
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#define PCI_CHIP_KABYLAKE_HALO_GT1_0 0x5908
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#define PCI_CHIP_KABYLAKE_HALO_GT1_1 0x590B
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#define PCI_CHIP_KABYLAKE_SRV_GT2 0x591A
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#define PCI_CHIP_KABYLAKE_SRV_GT1 0x590A
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#define PCI_CHIP_KABYLAKE_WKS_GT2 0x591D
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#define PCI_CHIP_BROXTON_0 0x0A84
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#define PCI_CHIP_BROXTON_1 0x1A84
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#define PCI_CHIP_BROXTON_2 0x5A84
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#define PCI_CHIP_BROXTON_3 0x1A85
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#define PCI_CHIP_BROXTON_4 0x5A85
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#define PCI_CHIP_GLK 0x3184
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#define PCI_CHIP_GLK_2X6 0x3185
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#define PCI_CHIP_COFFEELAKE_S_GT1_1 0x3E90
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#define PCI_CHIP_COFFEELAKE_S_GT1_2 0x3E93
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#define PCI_CHIP_COFFEELAKE_S_GT1_3 0x3E99
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#define PCI_CHIP_COFFEELAKE_S_GT2_1 0x3E91
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#define PCI_CHIP_COFFEELAKE_S_GT2_2 0x3E92
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#define PCI_CHIP_COFFEELAKE_S_GT2_3 0x3E96
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#define PCI_CHIP_COFFEELAKE_S_GT2_4 0x3E9A
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#define PCI_CHIP_COFFEELAKE_H_GT2_1 0x3E9B
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#define PCI_CHIP_COFFEELAKE_H_GT2_2 0x3E94
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#define PCI_CHIP_COFFEELAKE_U_GT2_1 0x3EA9
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#define PCI_CHIP_COFFEELAKE_U_GT3_1 0x3EA5
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#define PCI_CHIP_COFFEELAKE_U_GT3_2 0x3EA6
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#define PCI_CHIP_COFFEELAKE_U_GT3_3 0x3EA7
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#define PCI_CHIP_COFFEELAKE_U_GT3_4 0x3EA8
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#define PCI_CHIP_WHISKEYLAKE_U_GT1_1 0x3EA1
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#define PCI_CHIP_WHISKEYLAKE_U_GT2_1 0x3EA0
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#define PCI_CHIP_WHISKEYLAKE_U_GT3_1 0x3EA2
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#define PCI_CHIP_WHISKEYLAKE_U_GT3_2 0x3EA3
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#define PCI_CHIP_WHISKEYLAKE_U_GT3_3 0x3EA4
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#define PCI_CHIP_CANNONLAKE_0 0x5A51
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#define PCI_CHIP_CANNONLAKE_1 0x5A59
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#define PCI_CHIP_CANNONLAKE_2 0x5A41
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#define PCI_CHIP_CANNONLAKE_3 0x5A49
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#define PCI_CHIP_CANNONLAKE_4 0x5A52
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#define PCI_CHIP_CANNONLAKE_5 0x5A5A
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#define PCI_CHIP_CANNONLAKE_6 0x5A42
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#define PCI_CHIP_CANNONLAKE_7 0x5A4A
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#define PCI_CHIP_CANNONLAKE_8 0x5A50
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#define PCI_CHIP_CANNONLAKE_9 0x5A40
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#define PCI_CHIP_CANNONLAKE_10 0x5A54
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#define PCI_CHIP_CANNONLAKE_11 0x5A5C
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#define PCI_CHIP_CANNONLAKE_12 0x5A44
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#define PCI_CHIP_CANNONLAKE_13 0x5A4C
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#define PCI_CHIP_ICELAKE_11_0 0x8A50
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#define PCI_CHIP_ICELAKE_11_1 0x8A51
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#define PCI_CHIP_ICELAKE_11_2 0x8A5C
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#define PCI_CHIP_ICELAKE_11_3 0x8A5D
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#define PCI_CHIP_ICELAKE_11_4 0x8A52
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#define PCI_CHIP_ICELAKE_11_5 0x8A5A
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#define PCI_CHIP_ICELAKE_11_6 0x8A5B
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#define PCI_CHIP_ICELAKE_11_7 0x8A71
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#define PCI_CHIP_ICELAKE_11_8 0x8A70
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#define IS_MOBILE(devid) ((devid) == PCI_CHIP_I855_GM || \
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(devid) == PCI_CHIP_I915_GM || \
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(devid) == PCI_CHIP_I945_GM || \
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(devid) == PCI_CHIP_I945_GME || \
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(devid) == PCI_CHIP_I965_GM || \
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(devid) == PCI_CHIP_I965_GME || \
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(devid) == PCI_CHIP_GM45_GM || IS_IGD(devid) || \
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(devid) == PCI_CHIP_IVYBRIDGE_M_GT1 || \
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(devid) == PCI_CHIP_IVYBRIDGE_M_GT2)
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#define IS_G45(devid) ((devid) == PCI_CHIP_IGD_E_G || \
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(devid) == PCI_CHIP_Q45_G || \
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(devid) == PCI_CHIP_G45_G || \
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(devid) == PCI_CHIP_G41_G)
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#define IS_GM45(devid) ((devid) == PCI_CHIP_GM45_GM)
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#define IS_G4X(devid) (IS_G45(devid) || IS_GM45(devid))
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#define IS_ILD(devid) ((devid) == PCI_CHIP_ILD_G)
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#define IS_ILM(devid) ((devid) == PCI_CHIP_ILM_G)
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#define IS_915(devid) ((devid) == PCI_CHIP_I915_G || \
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(devid) == PCI_CHIP_E7221_G || \
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(devid) == PCI_CHIP_I915_GM)
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#define IS_945GM(devid) ((devid) == PCI_CHIP_I945_GM || \
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(devid) == PCI_CHIP_I945_GME)
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#define IS_945(devid) ((devid) == PCI_CHIP_I945_G || \
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(devid) == PCI_CHIP_I945_GM || \
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(devid) == PCI_CHIP_I945_GME || \
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IS_G33(devid))
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#define IS_G33(devid) ((devid) == PCI_CHIP_G33_G || \
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(devid) == PCI_CHIP_Q33_G || \
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(devid) == PCI_CHIP_Q35_G || IS_IGD(devid))
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#define IS_GEN2(devid) ((devid) == PCI_CHIP_I830_M || \
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(devid) == PCI_CHIP_845_G || \
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(devid) == PCI_CHIP_I855_GM || \
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(devid) == PCI_CHIP_I865_G)
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#define IS_GEN3(devid) (IS_945(devid) || IS_915(devid))
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#define IS_GEN4(devid) ((devid) == PCI_CHIP_I965_G || \
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(devid) == PCI_CHIP_I965_Q || \
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(devid) == PCI_CHIP_I965_G_1 || \
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(devid) == PCI_CHIP_I965_GM || \
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(devid) == PCI_CHIP_I965_GME || \
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(devid) == PCI_CHIP_I946_GZ || \
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IS_G4X(devid))
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#define IS_GEN5(devid) (IS_ILD(devid) || IS_ILM(devid))
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#define IS_GEN6(devid) ((devid) == PCI_CHIP_SANDYBRIDGE_GT1 || \
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(devid) == PCI_CHIP_SANDYBRIDGE_GT2 || \
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(devid) == PCI_CHIP_SANDYBRIDGE_GT2_PLUS || \
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(devid) == PCI_CHIP_SANDYBRIDGE_M_GT1 || \
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(devid) == PCI_CHIP_SANDYBRIDGE_M_GT2 || \
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(devid) == PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS || \
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(devid) == PCI_CHIP_SANDYBRIDGE_S)
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#define IS_GEN7(devid) (IS_IVYBRIDGE(devid) || \
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IS_HASWELL(devid) || \
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IS_VALLEYVIEW(devid))
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#define IS_IVYBRIDGE(devid) ((devid) == PCI_CHIP_IVYBRIDGE_GT1 || \
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(devid) == PCI_CHIP_IVYBRIDGE_GT2 || \
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(devid) == PCI_CHIP_IVYBRIDGE_M_GT1 || \
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(devid) == PCI_CHIP_IVYBRIDGE_M_GT2 || \
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(devid) == PCI_CHIP_IVYBRIDGE_S || \
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(devid) == PCI_CHIP_IVYBRIDGE_S_GT2)
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#define IS_VALLEYVIEW(devid) ((devid) == PCI_CHIP_VALLEYVIEW_PO || \
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(devid) == PCI_CHIP_VALLEYVIEW_1 || \
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(devid) == PCI_CHIP_VALLEYVIEW_2 || \
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(devid) == PCI_CHIP_VALLEYVIEW_3)
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#define IS_HSW_GT1(devid) ((devid) == PCI_CHIP_HASWELL_GT1 || \
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(devid) == PCI_CHIP_HASWELL_M_GT1 || \
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(devid) == PCI_CHIP_HASWELL_S_GT1 || \
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(devid) == PCI_CHIP_HASWELL_B_GT1 || \
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(devid) == PCI_CHIP_HASWELL_E_GT1 || \
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(devid) == PCI_CHIP_HASWELL_SDV_GT1 || \
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(devid) == PCI_CHIP_HASWELL_SDV_M_GT1 || \
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(devid) == PCI_CHIP_HASWELL_SDV_S_GT1 || \
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(devid) == PCI_CHIP_HASWELL_SDV_B_GT1 || \
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(devid) == PCI_CHIP_HASWELL_SDV_E_GT1 || \
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(devid) == PCI_CHIP_HASWELL_ULT_GT1 || \
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(devid) == PCI_CHIP_HASWELL_ULT_M_GT1 || \
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(devid) == PCI_CHIP_HASWELL_ULT_S_GT1 || \
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(devid) == PCI_CHIP_HASWELL_ULT_B_GT1 || \
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(devid) == PCI_CHIP_HASWELL_ULT_E_GT1 || \
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(devid) == PCI_CHIP_HASWELL_CRW_GT1 || \
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(devid) == PCI_CHIP_HASWELL_CRW_M_GT1 || \
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(devid) == PCI_CHIP_HASWELL_CRW_S_GT1 || \
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(devid) == PCI_CHIP_HASWELL_CRW_B_GT1 || \
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(devid) == PCI_CHIP_HASWELL_CRW_E_GT1)
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#define IS_HSW_GT2(devid) ((devid) == PCI_CHIP_HASWELL_GT2 || \
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(devid) == PCI_CHIP_HASWELL_M_GT2 || \
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(devid) == PCI_CHIP_HASWELL_S_GT2 || \
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(devid) == PCI_CHIP_HASWELL_B_GT2 || \
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(devid) == PCI_CHIP_HASWELL_E_GT2 || \
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(devid) == PCI_CHIP_HASWELL_SDV_GT2 || \
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(devid) == PCI_CHIP_HASWELL_SDV_M_GT2 || \
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(devid) == PCI_CHIP_HASWELL_SDV_S_GT2 || \
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(devid) == PCI_CHIP_HASWELL_SDV_B_GT2 || \
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(devid) == PCI_CHIP_HASWELL_SDV_E_GT2 || \
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(devid) == PCI_CHIP_HASWELL_ULT_GT2 || \
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(devid) == PCI_CHIP_HASWELL_ULT_M_GT2 || \
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(devid) == PCI_CHIP_HASWELL_ULT_S_GT2 || \
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(devid) == PCI_CHIP_HASWELL_ULT_B_GT2 || \
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(devid) == PCI_CHIP_HASWELL_ULT_E_GT2 || \
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(devid) == PCI_CHIP_HASWELL_CRW_GT2 || \
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(devid) == PCI_CHIP_HASWELL_CRW_M_GT2 || \
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(devid) == PCI_CHIP_HASWELL_CRW_S_GT2 || \
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(devid) == PCI_CHIP_HASWELL_CRW_B_GT2 || \
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(devid) == PCI_CHIP_HASWELL_CRW_E_GT2)
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#define IS_HSW_GT3(devid) ((devid) == PCI_CHIP_HASWELL_GT3 || \
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(devid) == PCI_CHIP_HASWELL_M_GT3 || \
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(devid) == PCI_CHIP_HASWELL_S_GT3 || \
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(devid) == PCI_CHIP_HASWELL_B_GT3 || \
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(devid) == PCI_CHIP_HASWELL_E_GT3 || \
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(devid) == PCI_CHIP_HASWELL_SDV_GT3 || \
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(devid) == PCI_CHIP_HASWELL_SDV_M_GT3 || \
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(devid) == PCI_CHIP_HASWELL_SDV_S_GT3 || \
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(devid) == PCI_CHIP_HASWELL_SDV_B_GT3 || \
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(devid) == PCI_CHIP_HASWELL_SDV_E_GT3 || \
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(devid) == PCI_CHIP_HASWELL_ULT_GT3 || \
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(devid) == PCI_CHIP_HASWELL_ULT_M_GT3 || \
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(devid) == PCI_CHIP_HASWELL_ULT_S_GT3 || \
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(devid) == PCI_CHIP_HASWELL_ULT_B_GT3 || \
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(devid) == PCI_CHIP_HASWELL_ULT_E_GT3 || \
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(devid) == PCI_CHIP_HASWELL_CRW_GT3 || \
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(devid) == PCI_CHIP_HASWELL_CRW_M_GT3 || \
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(devid) == PCI_CHIP_HASWELL_CRW_S_GT3 || \
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(devid) == PCI_CHIP_HASWELL_CRW_B_GT3 || \
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(devid) == PCI_CHIP_HASWELL_CRW_E_GT3)
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#define IS_HASWELL(devid) (IS_HSW_GT1(devid) || \
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IS_HSW_GT2(devid) || \
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IS_HSW_GT3(devid))
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#define IS_BROADWELL(devid) (((devid & 0xff00) != 0x1600) ? 0 : \
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(((devid & 0x00f0) >> 4) > 3) ? 0 : \
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((devid & 0x000f) == BDW_SPARE) ? 1 : \
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((devid & 0x000f) == BDW_ULT) ? 1 : \
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((devid & 0x000f) == BDW_IRIS) ? 1 : \
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((devid & 0x000f) == BDW_SERVER) ? 1 : \
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((devid & 0x000f) == BDW_WORKSTATION) ? 1 : \
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((devid & 0x000f) == BDW_ULX) ? 1 : 0)
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#define IS_CHERRYVIEW(devid) ((devid) == PCI_CHIP_CHERRYVIEW_0 || \
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(devid) == PCI_CHIP_CHERRYVIEW_1 || \
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(devid) == PCI_CHIP_CHERRYVIEW_2 || \
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(devid) == PCI_CHIP_CHERRYVIEW_3)
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#define IS_GEN8(devid) (IS_BROADWELL(devid) || \
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IS_CHERRYVIEW(devid))
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#define IS_SKL_GT1(devid) ((devid) == PCI_CHIP_SKYLAKE_DT_GT1 || \
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(devid) == PCI_CHIP_SKYLAKE_ULT_GT1 || \
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(devid) == PCI_CHIP_SKYLAKE_SRV_GT1 || \
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(devid) == PCI_CHIP_SKYLAKE_H_GT1 || \
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(devid) == PCI_CHIP_SKYLAKE_ULX_GT1)
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#define IS_SKL_GT2(devid) ((devid) == PCI_CHIP_SKYLAKE_DT_GT2 || \
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(devid) == PCI_CHIP_SKYLAKE_FUSED0_GT2 || \
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(devid) == PCI_CHIP_SKYLAKE_FUSED1_GT2 || \
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(devid) == PCI_CHIP_SKYLAKE_ULT_GT2 || \
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(devid) == PCI_CHIP_SKYLAKE_FUSED2_GT2 || \
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(devid) == PCI_CHIP_SKYLAKE_SRV_GT2 || \
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(devid) == PCI_CHIP_SKYLAKE_HALO_GT2 || \
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(devid) == PCI_CHIP_SKYLAKE_WKS_GT2 || \
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(devid) == PCI_CHIP_SKYLAKE_ULX_GT2 || \
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(devid) == PCI_CHIP_SKYLAKE_MOBILE_GT2)
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#define IS_SKL_GT3(devid) ((devid) == PCI_CHIP_SKYLAKE_ULT_GT3_0 || \
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(devid) == PCI_CHIP_SKYLAKE_ULT_GT3_1 || \
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(devid) == PCI_CHIP_SKYLAKE_ULT_GT3_2 || \
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(devid) == PCI_CHIP_SKYLAKE_HALO_GT3 || \
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(devid) == PCI_CHIP_SKYLAKE_SRV_GT3)
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#define IS_SKL_GT4(devid) ((devid) == PCI_CHIP_SKYLAKE_SRV_GT4 || \
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(devid) == PCI_CHIP_SKYLAKE_DT_GT4 || \
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(devid) == PCI_CHIP_SKYLAKE_SRV_GT4X || \
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(devid) == PCI_CHIP_SKYLAKE_H_GT4 || \
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(devid) == PCI_CHIP_SKYLAKE_WKS_GT4)
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#define IS_KBL_GT1(devid) ((devid) == PCI_CHIP_KABYLAKE_ULT_GT1_5 || \
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(devid) == PCI_CHIP_KABYLAKE_ULX_GT1_5 || \
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(devid) == PCI_CHIP_KABYLAKE_ULT_GT1 || \
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(devid) == PCI_CHIP_KABYLAKE_ULX_GT1 || \
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(devid) == PCI_CHIP_KABYLAKE_DT_GT1 || \
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(devid) == PCI_CHIP_KABYLAKE_HALO_GT1_0 || \
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(devid) == PCI_CHIP_KABYLAKE_HALO_GT1_1 || \
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(devid) == PCI_CHIP_KABYLAKE_SRV_GT1)
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#define IS_KBL_GT2(devid) ((devid) == PCI_CHIP_KABYLAKE_ULT_GT2 || \
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(devid) == PCI_CHIP_KABYLAKE_ULT_GT2F || \
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(devid) == PCI_CHIP_KABYLAKE_ULX_GT2_0 || \
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(devid) == PCI_CHIP_KABYLAKE_ULX_GT2_1 || \
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(devid) == PCI_CHIP_KABYLAKE_DT_GT2 || \
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(devid) == PCI_CHIP_KABYLAKE_M_GT2 || \
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(devid) == PCI_CHIP_KABYLAKE_HALO_GT2 || \
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(devid) == PCI_CHIP_KABYLAKE_SRV_GT2 || \
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(devid) == PCI_CHIP_KABYLAKE_WKS_GT2)
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#define IS_KBL_GT3(devid) ((devid) == PCI_CHIP_KABYLAKE_ULT_GT3_0 || \
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(devid) == PCI_CHIP_KABYLAKE_ULT_GT3_1 || \
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(devid) == PCI_CHIP_KABYLAKE_ULT_GT3_2)
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#define IS_KBL_GT4(devid) ((devid) == PCI_CHIP_KABYLAKE_HALO_GT4)
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#define IS_KABYLAKE(devid) (IS_KBL_GT1(devid) || \
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IS_KBL_GT2(devid) || \
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IS_KBL_GT3(devid) || \
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IS_KBL_GT4(devid))
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#define IS_SKYLAKE(devid) (IS_SKL_GT1(devid) || \
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IS_SKL_GT2(devid) || \
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IS_SKL_GT3(devid) || \
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IS_SKL_GT4(devid))
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#define IS_BROXTON(devid) ((devid) == PCI_CHIP_BROXTON_0 || \
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(devid) == PCI_CHIP_BROXTON_1 || \
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(devid) == PCI_CHIP_BROXTON_2 || \
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(devid) == PCI_CHIP_BROXTON_3 || \
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(devid) == PCI_CHIP_BROXTON_4)
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#define IS_GEMINILAKE(devid) ((devid) == PCI_CHIP_GLK || \
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(devid) == PCI_CHIP_GLK_2X6)
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#define IS_CFL_S(devid) ((devid) == PCI_CHIP_COFFEELAKE_S_GT1_1 || \
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(devid) == PCI_CHIP_COFFEELAKE_S_GT1_2 || \
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(devid) == PCI_CHIP_COFFEELAKE_S_GT1_3 || \
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(devid) == PCI_CHIP_COFFEELAKE_S_GT2_1 || \
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(devid) == PCI_CHIP_COFFEELAKE_S_GT2_2 || \
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(devid) == PCI_CHIP_COFFEELAKE_S_GT2_3 || \
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(devid) == PCI_CHIP_COFFEELAKE_S_GT2_4)
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#define IS_CFL_H(devid) ((devid) == PCI_CHIP_COFFEELAKE_H_GT2_1 || \
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(devid) == PCI_CHIP_COFFEELAKE_H_GT2_2)
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#define IS_CFL_U(devid) ((devid) == PCI_CHIP_COFFEELAKE_U_GT2_1 || \
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(devid) == PCI_CHIP_COFFEELAKE_U_GT3_1 || \
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(devid) == PCI_CHIP_COFFEELAKE_U_GT3_2 || \
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(devid) == PCI_CHIP_COFFEELAKE_U_GT3_3 || \
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(devid) == PCI_CHIP_COFFEELAKE_U_GT3_4 || \
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(devid) == PCI_CHIP_WHISKEYLAKE_U_GT1_1 || \
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(devid) == PCI_CHIP_WHISKEYLAKE_U_GT2_1 || \
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(devid) == PCI_CHIP_WHISKEYLAKE_U_GT3_1 || \
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(devid) == PCI_CHIP_WHISKEYLAKE_U_GT3_2 || \
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(devid) == PCI_CHIP_WHISKEYLAKE_U_GT3_3)
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#define IS_COFFEELAKE(devid) (IS_CFL_S(devid) || \
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IS_CFL_H(devid) || \
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IS_CFL_U(devid))
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#define IS_GEN9(devid) (IS_SKYLAKE(devid) || \
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IS_BROXTON(devid) || \
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IS_KABYLAKE(devid) || \
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IS_GEMINILAKE(devid) || \
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IS_COFFEELAKE(devid))
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#define IS_CANNONLAKE(devid) ((devid) == PCI_CHIP_CANNONLAKE_0 || \
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(devid) == PCI_CHIP_CANNONLAKE_1 || \
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(devid) == PCI_CHIP_CANNONLAKE_2 || \
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(devid) == PCI_CHIP_CANNONLAKE_3 || \
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(devid) == PCI_CHIP_CANNONLAKE_4 || \
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(devid) == PCI_CHIP_CANNONLAKE_5 || \
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(devid) == PCI_CHIP_CANNONLAKE_6 || \
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(devid) == PCI_CHIP_CANNONLAKE_7 || \
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(devid) == PCI_CHIP_CANNONLAKE_8 || \
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(devid) == PCI_CHIP_CANNONLAKE_9 || \
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(devid) == PCI_CHIP_CANNONLAKE_10 || \
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(devid) == PCI_CHIP_CANNONLAKE_11 || \
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(devid) == PCI_CHIP_CANNONLAKE_12 || \
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|
(devid) == PCI_CHIP_CANNONLAKE_13)
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#define IS_GEN10(devid) (IS_CANNONLAKE(devid))
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#define IS_ICELAKE_11(devid) ((devid) == PCI_CHIP_ICELAKE_11_0 || \
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(devid) == PCI_CHIP_ICELAKE_11_1 || \
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(devid) == PCI_CHIP_ICELAKE_11_2 || \
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(devid) == PCI_CHIP_ICELAKE_11_3 || \
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(devid) == PCI_CHIP_ICELAKE_11_4 || \
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|
(devid) == PCI_CHIP_ICELAKE_11_5 || \
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|
(devid) == PCI_CHIP_ICELAKE_11_6 || \
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|
(devid) == PCI_CHIP_ICELAKE_11_7 || \
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|
(devid) == PCI_CHIP_ICELAKE_11_8)
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|
#define IS_ICELAKE(devid) (IS_ICELAKE_11(devid))
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#define IS_GEN11(devid) (IS_ICELAKE_11(devid))
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|
#define IS_9XX(dev) (IS_GEN3(dev) || \
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|
IS_GEN4(dev) || \
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|
IS_GEN5(dev) || \
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|
IS_GEN6(dev) || \
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|
IS_GEN7(dev) || \
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|
IS_GEN8(dev) || \
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|
IS_GEN9(dev) || \
|
|
IS_GEN10(dev) || \
|
|
IS_GEN11(dev))
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|
|
|
#endif /* _INTEL_CHIPSET_H */
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