mirror of
https://gitlab.freedesktop.org/mesa/drm.git
synced 2025-12-21 04:00:13 +01:00
5cc3083179
Conflicts: linux-core/drmP.h linux-core/drm_bo.c linux-core/drm_drv.c linux-core/drm_objects.h shared-core/drm.h shared-core/i915_dma.c shared-core/i915_drv.h shared-core/i915_irq.c Mostly removing typedefs that snuck into the modesetting code and updating to the latest TTM APIs. As of today, the i915 driver builds, but there are likely to be problems, so debugging and bugfixes will come next.
382 lines
12 KiB
C
382 lines
12 KiB
C
/* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
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*/
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/*
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*
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* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sub license, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
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* IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
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* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include "drmP.h"
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#include "drm.h"
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#include "i915_drm.h"
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#include "intel_drv.h"
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#include "i915_drv.h"
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#include "drm_pciids.h"
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static struct pci_device_id pciidlist[] = {
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i915_PCI_IDS
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};
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#ifdef I915_HAVE_FENCE
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static struct drm_fence_driver i915_fence_driver = {
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.num_classes = 1,
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.wrap_diff = (1U << (BREADCRUMB_BITS - 1)),
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.flush_diff = (1U << (BREADCRUMB_BITS - 2)),
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.sequence_mask = BREADCRUMB_MASK,
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.lazy_capable = 1,
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.emit = i915_fence_emit_sequence,
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.poke_flush = i915_poke_flush,
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.has_irq = i915_fence_has_irq,
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};
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#endif
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#ifdef I915_HAVE_BUFFER
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static uint32_t i915_mem_prios[] = {DRM_BO_MEM_VRAM, DRM_BO_MEM_PRIV0, DRM_BO_MEM_TT, DRM_BO_MEM_LOCAL};
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static uint32_t i915_busy_prios[] = {DRM_BO_MEM_TT, DRM_BO_MEM_PRIV0, DRM_BO_MEM_VRAM, DRM_BO_MEM_LOCAL};
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static struct drm_bo_driver i915_bo_driver = {
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.mem_type_prio = i915_mem_prios,
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.mem_busy_prio = i915_busy_prios,
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.num_mem_type_prio = sizeof(i915_mem_prios)/sizeof(uint32_t),
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.num_mem_busy_prio = sizeof(i915_busy_prios)/sizeof(uint32_t),
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.create_ttm_backend_entry = i915_create_ttm_backend_entry,
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.fence_type = i915_fence_types,
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.invalidate_caches = i915_invalidate_caches,
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.init_mem_type = i915_init_mem_type,
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.evict_mask = i915_evict_mask,
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.move = i915_move,
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};
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#endif
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static int i915_suspend(struct pci_dev *pdev, pm_message_t state)
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{
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struct drm_device *dev = pci_get_drvdata(pdev);
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct drm_output *output;
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int i;
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pci_save_state(pdev);
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/* Save video mode information for native mode-setting. */
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dev_priv->saveDSPACNTR = I915_READ(DSPACNTR);
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dev_priv->savePIPEACONF = I915_READ(PIPEACONF);
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dev_priv->savePIPEASRC = I915_READ(PIPEASRC);
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dev_priv->saveFPA0 = I915_READ(FPA0);
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dev_priv->saveFPA1 = I915_READ(FPA1);
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dev_priv->saveDPLL_A = I915_READ(DPLL_A);
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if (IS_I965G(dev))
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dev_priv->saveDPLL_A_MD = I915_READ(DPLL_A_MD);
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dev_priv->saveHTOTAL_A = I915_READ(HTOTAL_A);
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dev_priv->saveHBLANK_A = I915_READ(HBLANK_A);
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dev_priv->saveHSYNC_A = I915_READ(HSYNC_A);
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dev_priv->saveVTOTAL_A = I915_READ(VTOTAL_A);
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dev_priv->saveVBLANK_A = I915_READ(VBLANK_A);
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dev_priv->saveVSYNC_A = I915_READ(VSYNC_A);
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dev_priv->saveDSPASTRIDE = I915_READ(DSPASTRIDE);
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dev_priv->saveDSPASIZE = I915_READ(DSPASIZE);
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dev_priv->saveDSPAPOS = I915_READ(DSPAPOS);
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dev_priv->saveDSPABASE = I915_READ(DSPABASE);
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for(i= 0; i < 256; i++)
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dev_priv->savePaletteA[i] = I915_READ(PALETTE_A + (i << 2));
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if(dev->mode_config.num_crtc == 2) {
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dev_priv->savePIPEBCONF = I915_READ(PIPEBCONF);
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dev_priv->savePIPEBSRC = I915_READ(PIPEBSRC);
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dev_priv->saveDSPBCNTR = I915_READ(DSPBCNTR);
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dev_priv->saveFPB0 = I915_READ(FPB0);
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dev_priv->saveFPB1 = I915_READ(FPB1);
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dev_priv->saveDPLL_B = I915_READ(DPLL_B);
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if (IS_I965G(dev))
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dev_priv->saveDPLL_B_MD = I915_READ(DPLL_B_MD);
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dev_priv->saveHTOTAL_B = I915_READ(HTOTAL_B);
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dev_priv->saveHBLANK_B = I915_READ(HBLANK_B);
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dev_priv->saveHSYNC_B = I915_READ(HSYNC_B);
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dev_priv->saveVTOTAL_B = I915_READ(VTOTAL_B);
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dev_priv->saveVBLANK_B = I915_READ(VBLANK_B);
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dev_priv->saveVSYNC_B = I915_READ(VSYNC_B);
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dev_priv->saveDSPBSTRIDE = I915_READ(DSPBSTRIDE);
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dev_priv->saveDSPBSIZE = I915_READ(DSPBSIZE);
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dev_priv->saveDSPBPOS = I915_READ(DSPBPOS);
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dev_priv->saveDSPBBASE = I915_READ(DSPBBASE);
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for(i= 0; i < 256; i++)
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dev_priv->savePaletteB[i] =
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I915_READ(PALETTE_B + (i << 2));
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}
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if (IS_I965G(dev)) {
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dev_priv->saveDSPASURF = I915_READ(DSPASURF);
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dev_priv->saveDSPBSURF = I915_READ(DSPBSURF);
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}
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dev_priv->saveVCLK_DIVISOR_VGA0 = I915_READ(VCLK_DIVISOR_VGA0);
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dev_priv->saveVCLK_DIVISOR_VGA1 = I915_READ(VCLK_DIVISOR_VGA1);
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dev_priv->saveVCLK_POST_DIV = I915_READ(VCLK_POST_DIV);
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dev_priv->saveVGACNTRL = I915_READ(VGACNTRL);
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for(i = 0; i < 7; i++) {
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dev_priv->saveSWF[i] = I915_READ(SWF0 + (i << 2));
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dev_priv->saveSWF[i+7] = I915_READ(SWF00 + (i << 2));
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}
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dev_priv->saveSWF[14] = I915_READ(SWF30);
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dev_priv->saveSWF[15] = I915_READ(SWF31);
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dev_priv->saveSWF[16] = I915_READ(SWF32);
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if (IS_MOBILE(dev) && !IS_I830(dev))
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dev_priv->saveLVDS = I915_READ(LVDS);
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dev_priv->savePFIT_CONTROL = I915_READ(PFIT_CONTROL);
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list_for_each_entry(output, &dev->mode_config.output_list, head)
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if (output->funcs->save)
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(*output->funcs->save) (output);
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#if 0 /* FIXME: save VGA bits */
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vgaHWUnlock(hwp);
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vgaHWSave(pScrn, vgaReg, VGA_SR_FONTS);
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#endif
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pci_disable_device(pdev);
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pci_set_power_state(pdev, PCI_D3hot);
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return 0;
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}
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static int i915_resume(struct pci_dev *pdev)
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{
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struct drm_device *dev = pci_get_drvdata(pdev);
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct drm_output *output;
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struct drm_crtc *crtc;
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int i;
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pci_set_power_state(pdev, PCI_D0);
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pci_restore_state(pdev);
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if (pci_enable_device(pdev))
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return -1;
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/* Disable outputs */
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list_for_each_entry(output, &dev->mode_config.output_list, head)
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output->funcs->dpms(output, DPMSModeOff);
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i915_driver_wait_next_vblank(dev, 0);
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/* Disable pipes */
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list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
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crtc->funcs->dpms(crtc, DPMSModeOff);
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/* FIXME: wait for vblank on each pipe? */
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i915_driver_wait_next_vblank(dev, 0);
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if (IS_MOBILE(dev) && !IS_I830(dev))
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I915_WRITE(LVDS, dev_priv->saveLVDS);
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if (!IS_I830(dev) && !IS_845G(dev))
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I915_WRITE(PFIT_CONTROL, dev_priv->savePFIT_CONTROL);
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if (dev_priv->saveDPLL_A & DPLL_VCO_ENABLE) {
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I915_WRITE(DPLL_A, dev_priv->saveDPLL_A & ~DPLL_VCO_ENABLE);
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udelay(150);
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}
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I915_WRITE(FPA0, dev_priv->saveFPA0);
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I915_WRITE(FPA1, dev_priv->saveFPA1);
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I915_WRITE(DPLL_A, dev_priv->saveDPLL_A);
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udelay(150);
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if (IS_I965G(dev))
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I915_WRITE(DPLL_A_MD, dev_priv->saveDPLL_A_MD);
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else
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I915_WRITE(DPLL_A, dev_priv->saveDPLL_A);
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udelay(150);
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I915_WRITE(HTOTAL_A, dev_priv->saveHTOTAL_A);
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I915_WRITE(HBLANK_A, dev_priv->saveHBLANK_A);
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I915_WRITE(HSYNC_A, dev_priv->saveHSYNC_A);
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I915_WRITE(VTOTAL_A, dev_priv->saveVTOTAL_A);
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I915_WRITE(VBLANK_A, dev_priv->saveVBLANK_A);
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I915_WRITE(VSYNC_A, dev_priv->saveVSYNC_A);
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I915_WRITE(DSPASTRIDE, dev_priv->saveDSPASTRIDE);
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I915_WRITE(DSPASIZE, dev_priv->saveDSPASIZE);
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I915_WRITE(DSPAPOS, dev_priv->saveDSPAPOS);
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I915_WRITE(PIPEASRC, dev_priv->savePIPEASRC);
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I915_WRITE(DSPABASE, dev_priv->saveDSPABASE);
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if (IS_I965G(dev))
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I915_WRITE(DSPASURF, dev_priv->saveDSPASURF);
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I915_WRITE(PIPEACONF, dev_priv->savePIPEACONF);
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i915_driver_wait_next_vblank(dev, 0);
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I915_WRITE(DSPACNTR, dev_priv->saveDSPACNTR);
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I915_WRITE(DSPABASE, I915_READ(DSPABASE));
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i915_driver_wait_next_vblank(dev, 0);
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if(dev->mode_config.num_crtc == 2) {
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if (dev_priv->saveDPLL_B & DPLL_VCO_ENABLE) {
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I915_WRITE(DPLL_B, dev_priv->saveDPLL_B & ~DPLL_VCO_ENABLE);
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udelay(150);
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}
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I915_WRITE(FPB0, dev_priv->saveFPB0);
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I915_WRITE(FPB1, dev_priv->saveFPB1);
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I915_WRITE(DPLL_B, dev_priv->saveDPLL_B);
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udelay(150);
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if (IS_I965G(dev))
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I915_WRITE(DPLL_B_MD, dev_priv->saveDPLL_B_MD);
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else
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I915_WRITE(DPLL_B, dev_priv->saveDPLL_B);
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udelay(150);
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I915_WRITE(HTOTAL_B, dev_priv->saveHTOTAL_B);
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I915_WRITE(HBLANK_B, dev_priv->saveHBLANK_B);
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I915_WRITE(HSYNC_B, dev_priv->saveHSYNC_B);
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I915_WRITE(VTOTAL_B, dev_priv->saveVTOTAL_B);
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I915_WRITE(VBLANK_B, dev_priv->saveVBLANK_B);
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I915_WRITE(VSYNC_B, dev_priv->saveVSYNC_B);
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I915_WRITE(DSPBSTRIDE, dev_priv->saveDSPBSTRIDE);
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I915_WRITE(DSPBSIZE, dev_priv->saveDSPBSIZE);
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I915_WRITE(DSPBPOS, dev_priv->saveDSPBPOS);
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I915_WRITE(PIPEBSRC, dev_priv->savePIPEBSRC);
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I915_WRITE(DSPBBASE, dev_priv->saveDSPBBASE);
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if (IS_I965G(dev))
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I915_WRITE(DSPBSURF, dev_priv->saveDSPBSURF);
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I915_WRITE(PIPEBCONF, dev_priv->savePIPEBCONF);
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i915_driver_wait_next_vblank(dev, 0);
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I915_WRITE(DSPBCNTR, dev_priv->saveDSPBCNTR);
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I915_WRITE(DSPBBASE, I915_READ(DSPBBASE));
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i915_driver_wait_next_vblank(dev, 0);
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}
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/* Restore outputs */
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list_for_each_entry(output, &dev->mode_config.output_list, head)
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if (output->funcs->restore)
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output->funcs->restore(output);
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I915_WRITE(VGACNTRL, dev_priv->saveVGACNTRL);
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I915_WRITE(VCLK_DIVISOR_VGA0, dev_priv->saveVCLK_DIVISOR_VGA0);
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I915_WRITE(VCLK_DIVISOR_VGA1, dev_priv->saveVCLK_DIVISOR_VGA1);
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I915_WRITE(VCLK_POST_DIV, dev_priv->saveVCLK_POST_DIV);
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for(i = 0; i < 256; i++)
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I915_WRITE(PALETTE_A + (i << 2), dev_priv->savePaletteA[i]);
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if(dev->mode_config.num_crtc == 2)
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for(i= 0; i < 256; i++)
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I915_WRITE(PALETTE_B + (i << 2), dev_priv->savePaletteB[i]);
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for(i = 0; i < 7; i++) {
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I915_WRITE(SWF0 + (i << 2), dev_priv->saveSWF[i]);
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I915_WRITE(SWF00 + (i << 2), dev_priv->saveSWF[i+7]);
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}
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I915_WRITE(SWF30, dev_priv->saveSWF[14]);
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I915_WRITE(SWF31, dev_priv->saveSWF[15]);
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I915_WRITE(SWF32, dev_priv->saveSWF[16]);
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#if 0 /* FIXME: restore VGA bits */
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vgaHWRestore(pScrn, vgaReg, VGA_SR_FONTS);
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vgaHWLock(hwp);
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#endif
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return 0;
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}
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static int probe(struct pci_dev *pdev, const struct pci_device_id *ent);
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static struct drm_driver driver = {
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/* don't use mtrr's here, the Xserver or user space app should
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* deal with them for intel hardware.
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*/
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.driver_features =
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DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | /* DRIVER_USE_MTRR | */
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DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_IRQ_VBL |
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DRIVER_IRQ_VBL2,
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.load = i915_driver_load,
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.unload = i915_driver_unload,
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.lastclose = i915_driver_lastclose,
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.preclose = i915_driver_preclose,
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.device_is_agp = i915_driver_device_is_agp,
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.vblank_wait = i915_driver_vblank_wait,
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.vblank_wait2 = i915_driver_vblank_wait2,
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.irq_preinstall = i915_driver_irq_preinstall,
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.irq_postinstall = i915_driver_irq_postinstall,
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.irq_uninstall = i915_driver_irq_uninstall,
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.irq_handler = i915_driver_irq_handler,
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.reclaim_buffers = drm_core_reclaim_buffers,
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.get_map_ofs = drm_core_get_map_ofs,
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.get_reg_ofs = drm_core_get_reg_ofs,
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.fb_probe = intelfb_probe,
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.fb_remove = intelfb_remove,
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.ioctls = i915_ioctls,
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.fops = {
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.owner = THIS_MODULE,
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.open = drm_open,
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.release = drm_release,
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.ioctl = drm_ioctl,
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.mmap = drm_mmap,
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.poll = drm_poll,
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.fasync = drm_fasync,
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#if defined(CONFIG_COMPAT) && LINUX_VERSION_CODE > KERNEL_VERSION(2,6,9)
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.compat_ioctl = i915_compat_ioctl,
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#endif
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},
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.pci_driver = {
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.name = DRIVER_NAME,
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.id_table = pciidlist,
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.probe = probe,
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.remove = __devexit_p(drm_cleanup_pci),
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.suspend = i915_suspend,
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.resume = i915_resume,
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},
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#ifdef I915_HAVE_FENCE
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.fence_driver = &i915_fence_driver,
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#endif
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#ifdef I915_HAVE_BUFFER
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.bo_driver = &i915_bo_driver,
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#endif
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.name = DRIVER_NAME,
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.desc = DRIVER_DESC,
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.date = DRIVER_DATE,
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.major = DRIVER_MAJOR,
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.minor = DRIVER_MINOR,
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.patchlevel = DRIVER_PATCHLEVEL,
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};
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static int probe(struct pci_dev *pdev, const struct pci_device_id *ent)
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{
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return drm_get_dev(pdev, ent, &driver);
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}
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static int __init i915_init(void)
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{
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driver.num_ioctls = i915_max_ioctl;
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return drm_init(&driver, pciidlist);
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}
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static void __exit i915_exit(void)
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{
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drm_exit(&driver);
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}
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module_init(i915_init);
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module_exit(i915_exit);
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MODULE_AUTHOR(DRIVER_AUTHOR);
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MODULE_DESCRIPTION(DRIVER_DESC);
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MODULE_LICENSE("GPL and additional rights");
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