mirror of
https://gitlab.freedesktop.org/mesa/drm.git
synced 2025-12-20 10:30:11 +01:00
dbffeadcfc
No idea what this reg does.. NVIDIA put 0x802 into it on some chips, the criteria aren't too clear on when they do that however. Hopefully 0x800 will work everywhere...
338 lines
7.8 KiB
C
338 lines
7.8 KiB
C
/*
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* Copyright (C) 2007 Ben Skeggs.
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining
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* a copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sublicense, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial
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* portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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* IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
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* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
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* OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
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* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include "drmP.h"
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#include "drm.h"
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#include "nouveau_drv.h"
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#include "nv50_grctx.h"
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#define IS_G80 ((dev_priv->chipset & 0xf0) == 0x50)
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static void
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nv50_graph_init_reset(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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uint32_t pmc_e = NV_PMC_ENABLE_PGRAPH | (1 << 21);
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DRM_DEBUG("\n");
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NV_WRITE(NV03_PMC_ENABLE, NV_READ(NV03_PMC_ENABLE) & ~pmc_e);
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NV_WRITE(NV03_PMC_ENABLE, NV_READ(NV03_PMC_ENABLE) | pmc_e);
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}
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static void
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nv50_graph_init_intr(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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DRM_DEBUG("\n");
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NV_WRITE(NV03_PGRAPH_INTR, 0xffffffff);
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NV_WRITE(0x400138, 0xffffffff);
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NV_WRITE(NV40_PGRAPH_INTR_EN, 0xffffffff);
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}
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static void
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nv50_graph_init_regs__nv(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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DRM_DEBUG("\n");
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NV_WRITE(0x400804, 0xc0000000);
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NV_WRITE(0x406800, 0xc0000000);
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NV_WRITE(0x400c04, 0xc0000000);
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NV_WRITE(0x401804, 0xc0000000);
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NV_WRITE(0x405018, 0xc0000000);
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NV_WRITE(0x402000, 0xc0000000);
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NV_WRITE(0x400108, 0xffffffff);
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NV_WRITE(0x400824, 0x00004000);
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NV_WRITE(0x400500, 0x00010001);
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}
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static void
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nv50_graph_init_regs(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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DRM_DEBUG("\n");
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NV_WRITE(NV04_PGRAPH_DEBUG_3, (1<<2) /* HW_CONTEXT_SWITCH_ENABLED */);
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NV_WRITE(0x402ca8, 0x800);
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}
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static int
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nv50_graph_init_ctxctl(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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uint32_t *voodoo = NULL;
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DRM_DEBUG("\n");
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switch (dev_priv->chipset) {
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case 0x50:
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voodoo = nv50_ctxprog;
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break;
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case 0x84:
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voodoo = nv84_ctxprog;
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break;
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case 0x86:
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voodoo = nv86_ctxprog;
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break;
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case 0x92:
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voodoo = nv92_ctxprog;
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break;
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case 0x94:
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case 0x96:
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voodoo = nv94_ctxprog;
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break;
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case 0x98:
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voodoo = nv98_ctxprog;
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break;
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case 0xa0:
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voodoo = nva0_ctxprog;
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break;
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case 0xaa:
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voodoo = nvaa_ctxprog;
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break;
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default:
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DRM_ERROR("no ctxprog for chipset NV%02x\n", dev_priv->chipset);
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return -EINVAL;
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}
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NV_WRITE(NV40_PGRAPH_CTXCTL_UCODE_INDEX, 0);
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while (*voodoo != ~0) {
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NV_WRITE(NV40_PGRAPH_CTXCTL_UCODE_DATA, *voodoo);
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voodoo++;
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}
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NV_WRITE(0x400320, 4);
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NV_WRITE(NV40_PGRAPH_CTXCTL_CUR, 0);
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NV_WRITE(NV20_PGRAPH_CHANNEL_CTX_POINTER, 0);
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return 0;
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}
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int
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nv50_graph_init(struct drm_device *dev)
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{
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int ret;
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DRM_DEBUG("\n");
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nv50_graph_init_reset(dev);
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nv50_graph_init_intr(dev);
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nv50_graph_init_regs__nv(dev);
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nv50_graph_init_regs(dev);
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ret = nv50_graph_init_ctxctl(dev);
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if (ret)
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return ret;
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return 0;
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}
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void
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nv50_graph_takedown(struct drm_device *dev)
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{
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DRM_DEBUG("\n");
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}
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int
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nv50_graph_create_context(struct nouveau_channel *chan)
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{
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struct drm_device *dev = chan->dev;
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_gpuobj *ramin = chan->ramin->gpuobj;
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struct nouveau_gpuobj *ctx;
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struct nouveau_engine *engine = &dev_priv->Engine;
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uint32_t *ctxvals = NULL;
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int grctx_size = 0x70000, hdr;
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int ret;
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DRM_DEBUG("ch%d\n", chan->id);
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ret = nouveau_gpuobj_new_ref(dev, chan, NULL, 0, grctx_size, 0x1000,
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NVOBJ_FLAG_ZERO_ALLOC |
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NVOBJ_FLAG_ZERO_FREE, &chan->ramin_grctx);
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if (ret)
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return ret;
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ctx = chan->ramin_grctx->gpuobj;
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hdr = IS_G80 ? 0x200 : 0x20;
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INSTANCE_WR(ramin, (hdr + 0x00)/4, 0x00190002);
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INSTANCE_WR(ramin, (hdr + 0x04)/4, chan->ramin_grctx->instance +
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grctx_size - 1);
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INSTANCE_WR(ramin, (hdr + 0x08)/4, chan->ramin_grctx->instance);
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INSTANCE_WR(ramin, (hdr + 0x0c)/4, 0);
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INSTANCE_WR(ramin, (hdr + 0x10)/4, 0);
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INSTANCE_WR(ramin, (hdr + 0x14)/4, 0x00010000);
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switch (dev_priv->chipset) {
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case 0x50:
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ctxvals = nv50_ctxvals;
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break;
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case 0x84:
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ctxvals = nv84_ctxvals;
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break;
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case 0x86:
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ctxvals = nv86_ctxvals;
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break;
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case 0x92:
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ctxvals = nv92_ctxvals;
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break;
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case 0x94:
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ctxvals = nv94_ctxvals;
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break;
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case 0x96:
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ctxvals = nv96_ctxvals;
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break;
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case 0x98:
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ctxvals = nv98_ctxvals;
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break;
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case 0xa0:
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ctxvals = nva0_ctxvals;
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break;
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case 0xaa:
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ctxvals = nvaa_ctxvals;
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break;
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default:
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break;
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}
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if (ctxvals) {
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int pos = 0;
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while (*ctxvals) {
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int cnt = *ctxvals++;
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while (cnt--)
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INSTANCE_WR(ctx, pos++, *ctxvals);
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ctxvals++;
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}
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} else {
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/* This is complete crack, it accidently used to make at
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* least some G8x cards work partially somehow, though there's
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* no good reason why - and it stopped working as the rest
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* of the code got off the drugs..
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*/
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ret = engine->graph.load_context(chan);
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if (ret) {
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DRM_ERROR("Error hacking up context: %d\n", ret);
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return ret;
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}
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}
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INSTANCE_WR(ctx, 0x00000/4, chan->ramin->instance >> 12);
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if ((dev_priv->chipset & 0xf0) == 0xa0)
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INSTANCE_WR(ctx, 0x00004/4, 0x00000002);
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else
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INSTANCE_WR(ctx, 0x0011c/4, 0x00000002);
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return 0;
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}
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void
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nv50_graph_destroy_context(struct nouveau_channel *chan)
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{
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struct drm_device *dev = chan->dev;
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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int i, hdr;
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DRM_DEBUG("ch%d\n", chan->id);
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hdr = IS_G80 ? 0x200 : 0x20;
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for (i=hdr; i<hdr+24; i+=4)
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INSTANCE_WR(chan->ramin->gpuobj, i/4, 0);
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nouveau_gpuobj_ref_del(dev, &chan->ramin_grctx);
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}
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static int
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nv50_graph_transfer_context(struct drm_device *dev, uint32_t inst, int save)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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uint32_t old_cp, tv = 20000;
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int i;
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DRM_DEBUG("inst=0x%08x, save=%d\n", inst, save);
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old_cp = NV_READ(NV20_PGRAPH_CHANNEL_CTX_POINTER);
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NV_WRITE(NV20_PGRAPH_CHANNEL_CTX_POINTER, inst);
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NV_WRITE(0x400824, NV_READ(0x400824) |
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(save ? NV40_PGRAPH_CTXCTL_0310_XFER_SAVE :
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NV40_PGRAPH_CTXCTL_0310_XFER_LOAD));
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NV_WRITE(NV40_PGRAPH_CTXCTL_0304, NV40_PGRAPH_CTXCTL_0304_XFER_CTX);
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for (i = 0; i < tv; i++) {
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if (NV_READ(NV40_PGRAPH_CTXCTL_030C) == 0)
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break;
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}
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NV_WRITE(NV20_PGRAPH_CHANNEL_CTX_POINTER, old_cp);
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if (i == tv) {
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DRM_ERROR("failed: inst=0x%08x save=%d\n", inst, save);
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DRM_ERROR("0x40030C = 0x%08x\n",
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NV_READ(NV40_PGRAPH_CTXCTL_030C));
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return -EBUSY;
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}
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return 0;
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}
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int
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nv50_graph_load_context(struct nouveau_channel *chan)
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{
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struct drm_device *dev = chan->dev;
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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uint32_t inst = chan->ramin->instance >> 12;
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int ret; (void)ret;
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DRM_DEBUG("ch%d\n", chan->id);
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#if 0
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if ((ret = nv50_graph_transfer_context(dev, inst, 0)))
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return ret;
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#endif
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NV_WRITE(NV20_PGRAPH_CHANNEL_CTX_POINTER, inst);
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NV_WRITE(0x400320, 4);
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NV_WRITE(NV40_PGRAPH_CTXCTL_CUR, inst | (1<<31));
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return 0;
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}
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int
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nv50_graph_save_context(struct nouveau_channel *chan)
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{
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struct drm_device *dev = chan->dev;
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uint32_t inst = chan->ramin->instance >> 12;
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DRM_DEBUG("ch%d\n", chan->id);
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return nv50_graph_transfer_context(dev, inst, 1);
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}
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