meson: do not mark exynos/omap/tegra as disabled features

Otherwise, using `--auto-features=enabled` wouldn't work because it
only "forces" auto options to be enabled.

This will enable these backends in CI to catch possible build errors.

Closes: https://gitlab.freedesktop.org/mesa/libdrm/-/work_items/128
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

.gitlab-ci.yml

@@ -18,9 +18,9 @@ include:
   - project: 'freedesktop/ci-templates'
     ref: *template_sha
     file:
-    - '/templates/debian.yml'
+      - '/templates/debian.yml'
-    - '/templates/freebsd.yml'
+      - '/templates/freebsd.yml'
-    - '/templates/ci-fairy.yml'
+      - '/templates/ci-fairy.yml'
 
 variables:
   FDO_UPSTREAM_REPO: mesa/libdrm
@@ -39,11 +39,11 @@ stages:
 .os-debian:
   variables:
     BUILD_OS: debian
-    FDO_DISTRIBUTION_VERSION: bookworm
+    FDO_DISTRIBUTION_VERSION: trixie-slim
     FDO_DISTRIBUTION_PACKAGES: 'build-essential docbook-xsl libatomic-ops-dev libcairo2-dev libcunit1-dev libpciaccess-dev meson ninja-build pkg-config python3 python3-pip python3-wheel python3-setuptools python3-docutils valgrind'
     # bump this tag every time you change something which requires rebuilding the
     # base image
-    FDO_DISTRIBUTION_TAG: "2024-06-25.0"
+    FDO_DISTRIBUTION_TAG: "2026-04-27.0"
 
 .debian-x86_64:
   extends:

README.rst

@@ -58,3 +58,6 @@ The AMDGPU driver requires the `amdgpu.ids` file. It is usually located at
 paths at runtime by setting the `AMDGPU_ASIC_ID_TABLE_PATHS` environment
 variable with one or more colon-separated paths where to search for the
 `amdgpu.ids` file.
+
+For this option to be available, the C library must support secure_getenv()
+function. In systems without it (like NetBSD), this option won't be available.

amdgpu/amdgpu-symbols.txt

@@ -76,7 +76,9 @@ amdgpu_query_video_caps_info
 amdgpu_read_mm_registers
 amdgpu_va_manager_alloc
 amdgpu_va_manager_init
+amdgpu_va_manager_init2
 amdgpu_va_manager_deinit
+amdgpu_va_manager_query_sw_info
 amdgpu_va_range_alloc
 amdgpu_va_range_alloc2
 amdgpu_va_range_free

amdgpu/amdgpu.h

@@ -105,6 +105,19 @@ enum amdgpu_gpu_va_range
 
 enum amdgpu_sw_info {
 	amdgpu_sw_info_address32_hi = 0,
+	/** Query the PRT control bit when the half VA range is reserved for
+	 * PRT when the device is initialized. This depends on the GFX version.
+	 * A return value of ~0 should be ignored.
+	 */
+	amdgpu_sw_info_address_prt_wa_control_bit = 1,
+};
+
+enum amdgpu_va_manager_sw_info {
+	/** Query the PRT control bit when the half VA range is reserved for
+	 * PRT with AMDGPU_VA_MGR_RESERVE_HALF_VA_FOR_PRT. The default value of
+	 * ~0 shouldn't be considered a valid value.
+	 */
+	amdgpu_va_manager_sw_info_address_prt_wa_control_bit = 0,
 };
 
 /*--------------------------------------------------------------------------*/
@@ -1467,6 +1480,14 @@ void amdgpu_va_manager_init(amdgpu_va_manager_handle va_mgr,
 			    uint64_t high_va_offset, uint64_t high_va_max,
 			    uint32_t virtual_address_alignment);
 
+#define AMDGPU_VA_MGR_RESERVE_HALF_VA_FOR_PRT 0x1
+
+void amdgpu_va_manager_init2(struct amdgpu_va_manager *va_mgr,
+			     uint64_t low_va_offset, uint64_t low_va_max,
+			     uint64_t high_va_offset, uint64_t high_va_max,
+			     uint32_t virtual_address_alignment,
+			     uint32_t flags);
+
 void amdgpu_va_manager_deinit(amdgpu_va_manager_handle va_mgr);
 
 /**
@@ -1484,6 +1505,21 @@ int amdgpu_va_range_alloc2(amdgpu_va_manager_handle va_mgr,
 			   amdgpu_va_handle *va_range_handle,
 			   uint64_t flags);
 
+/**
+ * Query VA manager information.
+ *
+ * \param   va_mgr  - \c [in] VA manager
+ * \param   info    - \c [in] amdgpu_va_manager_sw_info_*
+ * \param   value   - \c [out] Pointer to the return value.
+ *
+ * \return   0 on success\n
+ *          <0 - Negative POSIX error code
+ *
+*/
+int amdgpu_va_manager_query_sw_info(struct amdgpu_va_manager *va_mgr,
+				    enum amdgpu_va_manager_sw_info info,
+				    void *value);
+
 /**
  *  VA mapping/unmapping for the buffer object
  *

amdgpu/amdgpu_asic_id.c

@@ -165,6 +165,7 @@ static void amdgpu_parse_proc_cpuinfo(struct amdgpu_device *dev)
 	fclose(fp);
 }
 
+#if HAVE_SECURE_GETENV
 static char *join_path(const char *dir, const char *file) {
 	size_t dir_len = strlen(dir);
 	size_t file_len = strlen(file);
@@ -237,7 +238,7 @@ static char *find_asic_id_table(void)
 {
 	// first check the paths in AMDGPU_ASIC_ID_TABLE_PATHS environment variable
 	const char *amdgpu_asic_id_table_paths = secure_getenv("AMDGPU_ASIC_ID_TABLE_PATHS");
-	char *file_name = NULL;
+	const char *file_name = NULL;
 	char *found_path = NULL;
 	char **paths = NULL;
 
@@ -268,6 +269,7 @@ static char *find_asic_id_table(void)
 	split_env_var_free(paths);
 	return found_path;
 }
+#endif
 
 void amdgpu_parse_asic_ids(struct amdgpu_device *dev)
 {
@@ -278,8 +280,12 @@ void amdgpu_parse_asic_ids(struct amdgpu_device *dev)
 	int line_num = 1;
 	int r = 0;
 
-	char *amdgpu_asic_id_table_path = find_asic_id_table();
+	char *amdgpu_asic_id_table_path = NULL;
-
+#if HAVE_SECURE_GETENV
+	// if this system lacks secure_getenv(), don't allow extra paths
+	// for security reasons.
+	amdgpu_asic_id_table_path = find_asic_id_table();
+#endif
 	// if not found, use the default AMDGPU_ASIC_ID_TABLE path
 	if (!amdgpu_asic_id_table_path)
 		amdgpu_asic_id_table_path = strdup(AMDGPU_ASIC_ID_TABLE);

amdgpu/amdgpu_device.c

@@ -144,6 +144,39 @@ static void amdgpu_device_reference(struct amdgpu_device **dst,
 	*dst = src;
 }
 
+static int amdgpu_query_gfx_level_major(amdgpu_device_handle dev,
+					uint8_t *gfx_ip_version_major)
+{
+	struct drm_amdgpu_info_hw_ip ip_info;
+	uint32_t gfx_ip_count = 0;
+	int r;
+
+	*gfx_ip_version_major = 0;
+
+	r = amdgpu_query_hw_ip_count(dev, AMDGPU_HW_IP_GFX, &gfx_ip_count);
+	if (r)
+		return r;
+
+	/* No graphics support. */
+	if (gfx_ip_count == 0)
+		return 0;
+
+	memset(&ip_info, 0, sizeof(ip_info));
+
+	r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_GFX, 0, &ip_info);
+	if (r)
+		return r;
+
+	/* GFX6-8 don't set ip_discovery_version. */
+	if (dev->minor_version >= 48 && ip_info.ip_discovery_version) {
+		*gfx_ip_version_major = (ip_info.ip_discovery_version >> 16) & 0xff;
+	} else {
+		*gfx_ip_version_major = ip_info.hw_ip_version_major;
+	}
+
+	return r;
+}
+
 static int _amdgpu_device_initialize(int fd,
 				     uint32_t *major_version,
 				     uint32_t *minor_version,
@@ -151,11 +184,13 @@ static int _amdgpu_device_initialize(int fd,
 				     bool deduplicate_device)
 {
 	struct amdgpu_device *dev = NULL;
+	uint8_t gfx_ip_version_major = 0;
 	drmVersionPtr version;
 	int r;
 	int flag_auth = 0;
 	int flag_authexist=0;
 	uint32_t accel_working = 0;
+	uint32_t va_mgr_flags = 0;
 
 	*device_handle = NULL;
 
@@ -244,12 +279,25 @@ static int _amdgpu_device_initialize(int fd,
 		goto cleanup;
 	}
 
-	amdgpu_va_manager_init(&dev->va_mgr,
+	r = amdgpu_query_gfx_level_major(dev, &gfx_ip_version_major);
-			       dev->dev_info.virtual_address_offset,
+	if (!r) {
-			       dev->dev_info.virtual_address_max,
+		/* Split the HIGH addr space for GFX6-GFX12, except GFX9 to
-			       dev->dev_info.high_va_offset,
+		 * implement a workaround for SMEM loads with NULL PRT pages.
-			       dev->dev_info.high_va_max,
+		 * This is silently ignored if querying the GFX level failed.
-			       dev->dev_info.virtual_address_alignment);
+		 */
+		if (gfx_ip_version_major >= 6 && gfx_ip_version_major <= 12 &&
+		    gfx_ip_version_major != 9) {
+			va_mgr_flags |= AMDGPU_VA_MGR_RESERVE_HALF_VA_FOR_PRT;
+		}
+	}
+
+	amdgpu_va_manager_init2(&dev->va_mgr,
+				dev->dev_info.virtual_address_offset,
+				dev->dev_info.virtual_address_max,
+				dev->dev_info.high_va_offset,
+				dev->dev_info.high_va_max,
+				dev->dev_info.virtual_address_alignment,
+				va_mgr_flags);
 
 	amdgpu_parse_asic_ids(dev);
 
@@ -322,6 +370,9 @@ drm_public int amdgpu_query_sw_info(amdgpu_device_handle dev,
 		else
 			*val32 = (dev->va_mgr.vamgr_32.va_max - 1) >> 32;
 		return 0;
+	case amdgpu_sw_info_address_prt_wa_control_bit:
+		*val32 = dev->va_mgr.address_prt_wa_control_bit;
+		return 0;
 	}
 	return -EINVAL;
 }

amdgpu/amdgpu_internal.h

@@ -72,6 +72,11 @@ struct amdgpu_va_manager {
 	struct amdgpu_bo_va_mgr vamgr_high;
 	/** The VA manager for the 32bit high address space */
 	struct amdgpu_bo_va_mgr vamgr_high_32;
+
+	/** The bit to control whether it's the "LOW" or "HIGH" halves, when
+	 *  half of the address space is reserved for PRT to implement a SW
+	 *  workaround. */
+	unsigned address_prt_wa_control_bit;
 };
 
 struct amdgpu_device {

amdgpu/amdgpu_vamgr.c

@@ -323,19 +323,42 @@ drm_public amdgpu_va_manager_handle amdgpu_va_manager_alloc(void)
 }
 
 drm_public void amdgpu_va_manager_init(struct amdgpu_va_manager *va_mgr,
+				       uint64_t low_va_offset, uint64_t low_va_max,
+				       uint64_t high_va_offset, uint64_t high_va_max,
+				       uint32_t virtual_address_alignment)
+{
+	amdgpu_va_manager_init2(va_mgr, low_va_offset, low_va_max,
+				high_va_offset, high_va_max,
+				virtual_address_alignment, 0);
+}
+
+drm_public void amdgpu_va_manager_init2(struct amdgpu_va_manager *va_mgr,
 					uint64_t low_va_offset, uint64_t low_va_max,
 					uint64_t high_va_offset, uint64_t high_va_max,
-					uint32_t virtual_address_alignment)
+					uint32_t virtual_address_alignment,
+					uint32_t flags)
 {
 	uint64_t start, max;
 
+	va_mgr->address_prt_wa_control_bit = ~0;
+
 	start = low_va_offset;
 	max = MIN2(low_va_max, 0x100000000ULL);
 	amdgpu_vamgr_init(&va_mgr->vamgr_32, start, max,
 			  virtual_address_alignment);
 
 	start = max;
-	max = MAX2(low_va_max, 0x100000000ULL);
+	if ((flags & AMDGPU_VA_MGR_RESERVE_HALF_VA_FOR_PRT) && !high_va_max) {
+		/* Reserve the half VA range for PRT by splitting it in two
+		 * equal halves where one bit controls whether it's the LOW or
+		 * HIGH half.
+		 */
+		va_mgr->address_prt_wa_control_bit = util_last_bit64(low_va_offset ^ low_va_max) - 1;
+		max = low_va_max ^ (1ull << va_mgr->address_prt_wa_control_bit);
+	} else {
+		max = MAX2(low_va_max, 0x100000000ULL);
+	}
+
 	amdgpu_vamgr_init(&va_mgr->vamgr_low, start, max,
 			  virtual_address_alignment);
 
@@ -345,7 +368,17 @@ drm_public void amdgpu_va_manager_init(struct amdgpu_va_manager *va_mgr,
 			  virtual_address_alignment);
 
 	start = max;
-	max = MAX2(high_va_max, (start & ~0xffffffffULL) + 0x100000000ULL);
+	if ((flags & AMDGPU_VA_MGR_RESERVE_HALF_VA_FOR_PRT) && high_va_max) {
+		/* Reserve the half VA range for PRT by splitting it in two
+		 * equal halves where one bit controls whether it's the LOW or
+		 * HIGH half.
+		 */
+		va_mgr->address_prt_wa_control_bit = util_last_bit64(high_va_offset ^ high_va_max) - 1;
+		max = high_va_max ^ (1ull << va_mgr->address_prt_wa_control_bit);
+	} else {
+		max = MAX2(high_va_max, (start & ~0xffffffffULL) + 0x100000000ULL);
+	}
+
 	amdgpu_vamgr_init(&va_mgr->vamgr_high, start, max,
 			  virtual_address_alignment);
 }
@@ -357,3 +390,17 @@ drm_public void amdgpu_va_manager_deinit(struct amdgpu_va_manager *va_mgr)
 	amdgpu_vamgr_deinit(&va_mgr->vamgr_high_32);
 	amdgpu_vamgr_deinit(&va_mgr->vamgr_high);
 }
+
+drm_public int amdgpu_va_manager_query_sw_info(struct amdgpu_va_manager *va_mgr,
+					       enum amdgpu_va_manager_sw_info info,
+					       void *value)
+{
+	uint32_t *val32 = (uint32_t*)value;
+
+	switch (info) {
+	case amdgpu_va_manager_sw_info_address_prt_wa_control_bit:
+		*val32 = va_mgr->address_prt_wa_control_bit;
+		return 0;
+	}
+	return -EINVAL;
+}

data/amdgpu.ids

@@ -8,6 +8,19 @@
 1114,	C3,	AMD Radeon 840M Graphics
 1114,	D2,	AMD Radeon 860M Graphics
 1114,	D3,	AMD Radeon 840M Graphics
+1114,	E2,	AMD Radeon 860M Graphics
+1114,	E4,	AMD Radeon 860M Graphics
+1114,	E5,	AMD Radeon 840M Graphics
+1114,	E9,	AMD Radeon 860M Graphics
+1114,	EA,	AMD Radeon 840M Graphics
+1114,	ED,	AMD Radeon 860M Graphics
+1114,	EE,	AMD Radeon 840M Graphics
+1114,	F2,	AMD Radeon 860M Graphics
+1114,	F3,	AMD Radeon 840M Graphics
+1114,	F9,	AMD Radeon 860M Graphics
+1114,	FA,	AMD Radeon 840M Graphics
+1114,	FC,	AMD Radeon 860M Graphics
+1114,	FD,	AMD Radeon 840M Graphics
 1309,	00,	AMD Radeon R7 Graphics
 130A,	00,	AMD Radeon R6 Graphics
 130B,	00,	AMD Radeon R4 Graphics
@@ -39,23 +52,35 @@
 1506,	C3,	AMD Radeon 610M
 1506,	C4,	AMD Radeon 610M
 150E,	C1,	AMD Radeon 890M Graphics
-150E,	C4,	AMD Radeon 890M Graphics
+150E,	C4,	AMD Radeon 880M Graphics
 150E,	C5,	AMD Radeon 890M Graphics
 150E,	C6,	AMD Radeon 890M Graphics
+150E,	C7,	AMD Radeon 890M Graphics
 150E,	D1,	AMD Radeon 890M Graphics
-150E,	D2,	AMD Radeon 890M Graphics
+150E,	D2,	AMD Radeon 880M Graphics
 150E,	D3,	AMD Radeon 890M Graphics
-1586,	C1,	Radeon 8060S Graphics
+150E,	E1,	AMD Radeon 890M Graphics
-1586,	C2,	Radeon 8050S Graphics
+150E,	E3,	AMD Radeon 890M Graphics
-1586,	C4,	Radeon 8050S Graphics
+150E,	E4,	AMD Radeon 890M Graphics
-1586,	D1,	Radeon 8060S Graphics
+150E,	F1,	AMD Radeon 890M Graphics
-1586,	D2,	Radeon 8050S Graphics
+150E,	F3,	AMD Radeon 890M Graphics
-1586,	D4,	Radeon 8050S Graphics
+1586,	C1,	AMD Radeon 8060S Graphics
-1586,	D5,	Radeon 8040S Graphics
+1586,	C2,	AMD Radeon 8050S Graphics
+1586,	C3,	AMD Radeon 8060S Graphics
+1586,	C4,	AMD Radeon 8050S Graphics
+1586,	C6,	AMD Radeon 8060S Graphics
+1586,	D1,	AMD Radeon 8060S Graphics
+1586,	D2,	AMD Radeon 8050S Graphics
+1586,	D4,	AMD Radeon 8050S Graphics
+1586,	D5,	AMD Radeon 8040S Graphics
 15BF,	00,	AMD Radeon 780M Graphics
 15BF,	01,	AMD Radeon 760M Graphics
 15BF,	02,	AMD Radeon 780M Graphics
 15BF,	03,	AMD Radeon 760M Graphics
+15BF,	05,	AMD Radeon 760M Graphics
+15BF,	06,	AMD Radeon 780M Graphics
+15BF,	07,	AMD Radeon 740M Graphics
+15BF,	08,	AMD Radeon 740M Graphics
 15BF,	C1,	AMD Radeon 780M Graphics
 15BF,	C2,	AMD Radeon 780M Graphics
 15BF,	C3,	AMD Radeon 760M Graphics
@@ -69,6 +94,7 @@
 15BF,	CB,	AMD Radeon 760M Graphics
 15BF,	CC,	AMD Radeon 740M Graphics
 15BF,	CD,	AMD Radeon 760M Graphics
+15BF,	CE,	AMD Radeon 740M Graphics
 15BF,	CF,	AMD Radeon 780M Graphics
 15BF,	D0,	AMD Radeon 780M Graphics
 15BF,	D1,	AMD Radeon 780M Graphics
@@ -91,10 +117,18 @@
 15C8,	C2,	AMD Radeon 740M Graphics
 15C8,	C3,	AMD Radeon 740M Graphics
 15C8,	C4,	AMD Radeon 740M Graphics
+15C8,	C5,	AMD Radeon 740M Graphics
+15C8,	C6,	AMD Radeon 740M Graphics
+15C8,	C7,	AMD Radeon 740M Graphics
+15C8,	C8,	AMD Radeon 740M Graphics
 15C8,	D1,	AMD Radeon 740M Graphics
 15C8,	D2,	AMD Radeon 740M Graphics
 15C8,	D3,	AMD Radeon 740M Graphics
 15C8,	D4,	AMD Radeon 740M Graphics
+15C8,	D5,	AMD Radeon 740M Graphics
+15C8,	D6,	AMD Radeon 740M Graphics
+15C8,	D7,	AMD Radeon 740M Graphics
+15C8,	D8,	AMD Radeon 740M Graphics
 15D8,	00,	AMD Radeon RX Vega 8 Graphics WS
 15D8,	91,	AMD Radeon Vega 3 Graphics
 15D8,	91,	AMD Ryzen Embedded R1606G with Radeon Vega Gfx
@@ -250,6 +284,19 @@
 1901,	D6,	AMD Radeon 740M Graphics
 1901,	D7,	AMD Radeon 740M Graphics
 1901,	D8,	AMD Radeon 740M Graphics
+1902,	C0,	AMD Radeon 840M Graphics
+1902,	C1,	AMD Radeon 840M Graphics
+1902,	C2,	AMD Radeon 820M Graphics
+1902,	C3,	AMD Radeon 840M Graphics
+1902,	C6,	AMD Radeon 820M Graphics
+1902,	C7,	AMD Radeon 840M Graphics
+1902,	C8,	AMD Radeon 840M Graphics
+1902,	C9,	AMD Radeon 820M Graphics
+1902,	CA,	AMD Radeon 840M Graphics
+1902,	D1,	AMD Radeon 840M Graphics
+1902,	D3,	AMD Radeon 840M Graphics
+1902,	D7,	AMD Radeon 840M Graphics
+1902,	D8,	AMD Radeon 840M Graphics
 6600,	00,	AMD Radeon HD 8600 / 8700M
 6600,	81,	AMD Radeon R7 M370
 6601,	00,	AMD Radeon HD 8500M / 8700M
@@ -577,6 +624,7 @@
 7480,	C3,	AMD Radeon RX 7600S
 7480,	C7,	AMD Radeon RX 7600M XT
 7480,	CF,	AMD Radeon RX 7600
+7481,   C7,     AMD Steam Machine
 7483,	CF,	AMD Radeon RX 7600M
 7489,	00,	AMD Radeon Pro W7500
 7499,	00,	AMD Radeon Pro W7400
@@ -595,12 +643,14 @@
 7550,	C2,	AMD Radeon RX 9070 GRE
 7550,	C3,	AMD Radeon RX 9070
 7551,	C0,	AMD Radeon AI PRO R9700
+7551,	C8,	AMD Radeon AI PRO R9600D
 7590,	C0,	AMD Radeon RX 9060 XT
+7590,	C1,	AMD Radeon RX 9060 XT LP
 7590,	C7,	AMD Radeon RX 9060
-75A0,	C0,	AMD Instinct MI350X
+75A0,	00,	AMD Instinct MI350X
-75A3,	C0,	AMD Instinct MI355X
+75A3,	00,	AMD Instinct MI355X
-75B0,	C0,	AMD Instinct MI350X VF
+75B0,	00,	AMD Instinct MI350X VF
-75B3,	C0,	AMD Instinct MI355X VF
+75B3,	00,	AMD Instinct MI355X VF
 9830,	00,	AMD Radeon HD 8400 / R3 Series
 9831,	00,	AMD Radeon HD 8400E
 9832,	00,	AMD Radeon HD 8330

gen_table_fourcc.py

@@ -34,7 +34,7 @@ towrite = sys.argv[2]
 
 fm_re = {
     'intel': r'^#define I915_FORMAT_MOD_(\w+)',
-    'others': r'^#define DRM_FORMAT_MOD_((?:ARM|SAMSUNG|QCOM|VIVANTE|NVIDIA|BROADCOM|ALLWINNER)\w+)\s',
+    'others': r'^#define DRM_FORMAT_MOD_((?:ARM|APPLE|SAMSUNG|QCOM|VIVANTE|NVIDIA|BROADCOM|ALLWINNER)\w+)\s',
     'vendors': r'^#define DRM_FORMAT_MOD_VENDOR_(\w+)'
 }
 

meson.build

@@ -26,7 +26,7 @@
 project(
   'libdrm',
   ['c'],
-  version : '2.4.130',
+  version : '2.4.133',
   license : 'MIT',
   meson_version : '>= 0.59',
   default_options : ['buildtype=debugoptimized', 'c_std=c11'],
@@ -51,6 +51,8 @@ dep_threads = dependency('threads')
 
 cc = meson.get_compiler('c')
 
+config.set10('HAVE_SECURE_GETENV', cc.has_function('secure_getenv'))
+
 android = cc.compiles('''int func() { return __ANDROID__; }''')
 
 # Solaris / Illumos

meson_options.txt

@@ -46,13 +46,11 @@ option(
 option(
   'omap',
   type : 'feature',
-  value : 'disabled',
   description : '''Enable support for OMAP's experimental KMS API.''',
 )
 option(
   'exynos',
   type : 'feature',
-  value : 'disabled',
   description : '''Enable support for EXYNOS's experimental KMS API.''',
 )
 option(
@@ -63,7 +61,6 @@ option(
 option(
   'tegra',
   type : 'feature',
-  value : 'disabled',
   description : '''Enable support for Tegra's experimental KMS API.''',
 )
 option(

omap/omap_drm.c

@@ -27,7 +27,6 @@
  */
 
 #include <stdlib.h>
-#include <linux/types.h>
 #include <errno.h>
 #include <sys/mman.h>
 #include <fcntl.h>

tests/modetest/modetest.c

@@ -1974,7 +1974,8 @@ static int parse_connector(struct pipe_arg *pipe, const char *arg)
 	unsigned int len;
 	unsigned int i;
 	const char *p;
-	char *endp;
+	const char *endp;
+	char *endp_tok;
 
 	pipe->vrefresh = 0;
 	pipe->crtc_id = (uint32_t)-1;
@@ -2012,7 +2013,8 @@ static int parse_connector(struct pipe_arg *pipe, const char *arg)
 		return -1;
 	if (*endp == '@') {
 		arg = endp + 1;
-		pipe->crtc_id = strtoul(arg, &endp, 10);
+		pipe->crtc_id = strtoul(arg, &endp_tok, 10);
+		endp = endp_tok;
 	}
 	if (*endp != ':')
 		return -1;
@@ -2028,8 +2030,8 @@ static int parse_connector(struct pipe_arg *pipe, const char *arg)
 	pipe->mode_str[len] = '\0';
 
 	if (*p == '-') {
-		pipe->vrefresh = strtof(p + 1, &endp);
+		pipe->vrefresh = strtof(p + 1, &endp_tok);
-		p = endp;
+		p = endp_tok;
 	}
 
 	if (*p == '@') {

util_math.h

@@ -24,6 +24,8 @@
 #ifndef _UTIL_MATH_H_
 #define _UTIL_MATH_H_
 
+#include <stdint.h>
+
 #define MIN2( A, B )   ( (A)<(B) ? (A) : (B) )
 #define MAX2( A, B )   ( (A)>(B) ? (A) : (B) )
 #define MAX3( A, B, C ) ((A) > (B) ? MAX2(A, C) : MAX2(B, C))
@@ -31,4 +33,25 @@
 #define __align_mask(value, mask)  (((value) + (mask)) & ~(mask))
 #define ALIGN(value, alignment)    __align_mask(value, (__typeof__(value))((alignment) - 1))
 
+static inline unsigned
+util_last_bit64(uint64_t u)
+{
+#if defined(HAVE___BUILTIN_CLZLL)
+	return u == 0 ? 0 : 64 - __builtin_clzll(u);
+#elif defined(_MSC_VER) && (_M_AMD64 || _M_ARM64 || _M_IA64)
+	unsigned long index;
+	if (_BitScanReverse64(&index, u))
+		return index + 1;
+	else
+		return 0;
+#else
+	unsigned r = 0;
+	while (u) {
+		r++;
+		u >>= 1;
+	}
+	return r;
+#endif
+}
+
 #endif /*_UTIL_MATH_H_*/

xf86drm.c

@@ -348,9 +348,10 @@ drmGetFormatModifierNameFromNvidia(uint64_t modifier)
      * testing against TEGRA_TILE */
     if ((modifier & 0x10) == 0x10) {
         char *mod_nvidia;
-        asprintf(&mod_nvidia, "BLOCK_LINEAR_2D,HEIGHT=%"PRIu64",KIND=%"PRIu64","
+        if (asprintf(&mod_nvidia, "BLOCK_LINEAR_2D,HEIGHT=%"PRIu64",KIND=%"PRIu64","
                  "GEN=%"PRIu64",SECTOR=%"PRIu64",COMPRESSION=%"PRIu64"", height,
-                 kind, gen, sector, compression);
+                 kind, gen, sector, compression) < 0)
+            mod_nvidia = NULL;
         return mod_nvidia;
     }
 
@@ -542,7 +543,8 @@ drmGetFormatModifierNameFromAmlogic(uint64_t modifier)
     else
         opts_str = "0";
 
-    asprintf(&mod_amlogic, "FBC,LAYOUT=%s,OPTIONS=%s", layout_str, opts_str);
+    if (asprintf(&mod_amlogic, "FBC,LAYOUT=%s,OPTIONS=%s", layout_str, opts_str) < 0)
+        mod_amlogic = NULL;
     return mod_amlogic;
 }
 
@@ -606,7 +608,8 @@ drmGetFormatModifierNameFromVivante(uint64_t modifier)
 	break;
     }
 
-    asprintf(&mod_vivante, "%s%s%s", color_tiling, tile_status, compression);
+    if (asprintf(&mod_vivante, "%s%s%s", color_tiling, tile_status, compression) < 0)
+        mod_vivante = NULL;
     return mod_vivante;
 }