meson: do not mark exynos/omap/tegra as disabled features

Otherwise, using `--auto-features=enabled` wouldn't work because it
only "forces" auto options to be enabled.

This will enable these backends in CI to catch possible build errors.

Closes: https://gitlab.freedesktop.org/mesa/libdrm/-/work_items/128
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

.gitlab-ci.yml

@@ -39,11 +39,11 @@ stages:
 .os-debian:
   variables:
     BUILD_OS: debian
-    FDO_DISTRIBUTION_VERSION: bookworm
+    FDO_DISTRIBUTION_VERSION: trixie-slim
     FDO_DISTRIBUTION_PACKAGES: 'build-essential docbook-xsl libatomic-ops-dev libcairo2-dev libcunit1-dev libpciaccess-dev meson ninja-build pkg-config python3 python3-pip python3-wheel python3-setuptools python3-docutils valgrind'
     # bump this tag every time you change something which requires rebuilding the
     # base image
-    FDO_DISTRIBUTION_TAG: "2024-06-25.0"
+    FDO_DISTRIBUTION_TAG: "2026-04-27.0"
 
 .debian-x86_64:
   extends:

README.rst

@@ -49,3 +49,15 @@ Then use ninja to build and install:
 
 If you are installing into a system location you will need to run install
 separately, and as root.
+
+AMDGPU ASIC table file
+----------------------
+
+The AMDGPU driver requires the `amdgpu.ids` file. It is usually located at
+`$PREFIX/share/libdrm`, but it is possible to specify a set of alternative
+paths at runtime by setting the `AMDGPU_ASIC_ID_TABLE_PATHS` environment
+variable with one or more colon-separated paths where to search for the
+`amdgpu.ids` file.
+
+For this option to be available, the C library must support secure_getenv()
+function. In systems without it (like NetBSD), this option won't be available.

amdgpu/amdgpu-symbols.txt

@@ -76,7 +76,9 @@ amdgpu_query_video_caps_info
 amdgpu_read_mm_registers
 amdgpu_va_manager_alloc
 amdgpu_va_manager_init
+amdgpu_va_manager_init2
 amdgpu_va_manager_deinit
+amdgpu_va_manager_query_sw_info
 amdgpu_va_range_alloc
 amdgpu_va_range_alloc2
 amdgpu_va_range_free

amdgpu/amdgpu.h

@@ -105,6 +105,19 @@ enum amdgpu_gpu_va_range
 
 enum amdgpu_sw_info {
 	amdgpu_sw_info_address32_hi = 0,
+	/** Query the PRT control bit when the half VA range is reserved for
+	 * PRT when the device is initialized. This depends on the GFX version.
+	 * A return value of ~0 should be ignored.
+	 */
+	amdgpu_sw_info_address_prt_wa_control_bit = 1,
+};
+
+enum amdgpu_va_manager_sw_info {
+	/** Query the PRT control bit when the half VA range is reserved for
+	 * PRT with AMDGPU_VA_MGR_RESERVE_HALF_VA_FOR_PRT. The default value of
+	 * ~0 shouldn't be considered a valid value.
+	 */
+	amdgpu_va_manager_sw_info_address_prt_wa_control_bit = 0,
 };
 
 /*--------------------------------------------------------------------------*/
@@ -1467,6 +1480,14 @@ void amdgpu_va_manager_init(amdgpu_va_manager_handle va_mgr,
 			    uint64_t high_va_offset, uint64_t high_va_max,
 			    uint32_t virtual_address_alignment);
 
+#define AMDGPU_VA_MGR_RESERVE_HALF_VA_FOR_PRT 0x1
+
+void amdgpu_va_manager_init2(struct amdgpu_va_manager *va_mgr,
+			     uint64_t low_va_offset, uint64_t low_va_max,
+			     uint64_t high_va_offset, uint64_t high_va_max,
+			     uint32_t virtual_address_alignment,
+			     uint32_t flags);
+
 void amdgpu_va_manager_deinit(amdgpu_va_manager_handle va_mgr);
 
 /**
@@ -1484,6 +1505,21 @@ int amdgpu_va_range_alloc2(amdgpu_va_manager_handle va_mgr,
 			   amdgpu_va_handle *va_range_handle,
 			   uint64_t flags);
 
+/**
+ * Query VA manager information.
+ *
+ * \param   va_mgr  - \c [in] VA manager
+ * \param   info    - \c [in] amdgpu_va_manager_sw_info_*
+ * \param   value   - \c [out] Pointer to the return value.
+ *
+ * \return   0 on success\n
+ *          <0 - Negative POSIX error code
+ *
+*/
+int amdgpu_va_manager_query_sw_info(struct amdgpu_va_manager *va_mgr,
+				    enum amdgpu_va_manager_sw_info info,
+				    void *value);
+
 /**
  *  VA mapping/unmapping for the buffer object
  *

amdgpu/amdgpu_asic_id.c

@@ -22,6 +22,11 @@
  *
  */
 
+// secure_getenv requires _GNU_SOURCE
+#ifndef _GNU_SOURCE
+#define _GNU_SOURCE
+#endif
+
 #include <ctype.h>
 #include <stdio.h>
 #include <stdlib.h>
@@ -160,6 +165,112 @@ static void amdgpu_parse_proc_cpuinfo(struct amdgpu_device *dev)
 	fclose(fp);
 }
 
+#if HAVE_SECURE_GETENV
+static char *join_path(const char *dir, const char *file) {
+	size_t dir_len = strlen(dir);
+	size_t file_len = strlen(file);
+	char *full_path = NULL;
+
+	int need_slash = ((dir_len > 0) && (dir[dir_len - 1] != '/'));
+	size_t total_len = dir_len + (need_slash ? 1 : 0) + file_len + 1; // +1 for null terminator
+
+	if (dir_len == 0) {
+		return strdup(file);
+	}
+
+	full_path = malloc(total_len);
+	if (!full_path) {
+		return NULL; // Memory allocation failed
+	}
+
+	strcpy(full_path, dir);
+	if (need_slash) {
+		full_path[dir_len] = '/';
+		dir_len++;
+	}
+	strcpy(full_path + dir_len, file);
+
+	return full_path;
+}
+
+static char **split_env_var(const char *env_var_content)
+{
+	char **ret = NULL;
+	char *dup_env_val;
+	int elements = 1;
+	int index = 1;
+
+	if (!env_var_content || env_var_content[0] == '\0')
+		return NULL;
+
+	for(char *p = (char *)env_var_content; *p; p++) {
+		if (*p == ':')
+			elements++;
+	}
+
+	dup_env_val = strdup(env_var_content);
+	if (!dup_env_val) {
+		return NULL;
+	}
+	ret = malloc(sizeof(char *) * (elements + 1));
+	ret[0] = dup_env_val;
+	for(char *p = (char *)dup_env_val; *p; p++) {
+		if (*p == ':') {
+			*p = 0;
+			ret[index++] = p + 1;
+		}
+	}
+	ret[index] = NULL; // ensure that the last element in the array is NULL
+	return ret;
+}
+
+static void split_env_var_free(char **split_var)
+{
+	if (split_var) {
+		// remember that the first element also points to the whole duplicated string,
+		// which was modified in place by replacing ':' with '\0' characters
+		free(split_var[0]);
+		free(split_var);
+	}
+}
+
+static char *find_asic_id_table(void)
+{
+	// first check the paths in AMDGPU_ASIC_ID_TABLE_PATHS environment variable
+	const char *amdgpu_asic_id_table_paths = secure_getenv("AMDGPU_ASIC_ID_TABLE_PATHS");
+	const char *file_name = NULL;
+	char *found_path = NULL;
+	char **paths = NULL;
+
+	if (!amdgpu_asic_id_table_paths)
+		return NULL;
+
+	// extract the file name from AMDGPU_ASIC_ID_TABLE
+	file_name = strrchr(AMDGPU_ASIC_ID_TABLE, '/');
+	if (!file_name)
+		return NULL;
+	file_name++; // skip the '/'
+
+	paths = split_env_var(amdgpu_asic_id_table_paths);
+	if (!paths)
+		return NULL;
+
+	// for each path, join with file_name and check if it exists
+	for (int i = 0; paths[i] != NULL; i++) {
+		char *full_path = join_path(paths[i], file_name);
+		if (!full_path) {
+			continue;
+		}
+		if (access(full_path, R_OK) == 0) {
+			found_path = full_path;
+			break;
+		}
+	}
+	split_env_var_free(paths);
+	return found_path;
+}
+#endif
+
 void amdgpu_parse_asic_ids(struct amdgpu_device *dev)
 {
 	FILE *fp;
@@ -169,9 +280,19 @@ void amdgpu_parse_asic_ids(struct amdgpu_device *dev)
 	int line_num = 1;
 	int r = 0;
 
-	fp = fopen(AMDGPU_ASIC_ID_TABLE, "r");
+	char *amdgpu_asic_id_table_path = NULL;
+#if HAVE_SECURE_GETENV
+	// if this system lacks secure_getenv(), don't allow extra paths
+	// for security reasons.
+	amdgpu_asic_id_table_path = find_asic_id_table();
+#endif
+	// if not found, use the default AMDGPU_ASIC_ID_TABLE path
+	if (!amdgpu_asic_id_table_path)
+		amdgpu_asic_id_table_path = strdup(AMDGPU_ASIC_ID_TABLE);
+
+	fp = fopen(amdgpu_asic_id_table_path, "r");
 	if (!fp) {
-		fprintf(stderr, "%s: %s\n", AMDGPU_ASIC_ID_TABLE,
+		fprintf(stderr, "%s: %s\n", amdgpu_asic_id_table_path,
 			strerror(errno));
 		goto get_cpu;
 	}
@@ -188,7 +309,7 @@ void amdgpu_parse_asic_ids(struct amdgpu_device *dev)
 			continue;
 		}
 
-		drmMsg("%s version: %s\n", AMDGPU_ASIC_ID_TABLE, line);
+		drmMsg("%s version: %s\n", amdgpu_asic_id_table_path, line);
 		break;
 	}
 
@@ -206,7 +327,7 @@ void amdgpu_parse_asic_ids(struct amdgpu_device *dev)
 
 	if (r == -EINVAL) {
 		fprintf(stderr, "Invalid format: %s: line %d: %s\n",
-			AMDGPU_ASIC_ID_TABLE, line_num, line);
+			amdgpu_asic_id_table_path, line_num, line);
 	} else if (r && r != -EAGAIN) {
 		fprintf(stderr, "%s: Cannot parse ASIC IDs: %s\n",
 			__func__, strerror(-r));
@@ -216,6 +337,7 @@ void amdgpu_parse_asic_ids(struct amdgpu_device *dev)
 	fclose(fp);
 
 get_cpu:
+	free(amdgpu_asic_id_table_path);
 	if (dev->info.ids_flags & AMDGPU_IDS_FLAGS_FUSION &&
 	    dev->marketing_name == NULL) {
 		amdgpu_parse_proc_cpuinfo(dev);

amdgpu/amdgpu_device.c

@@ -144,6 +144,39 @@ static void amdgpu_device_reference(struct amdgpu_device **dst,
 	*dst = src;
 }
 
+static int amdgpu_query_gfx_level_major(amdgpu_device_handle dev,
+					uint8_t *gfx_ip_version_major)
+{
+	struct drm_amdgpu_info_hw_ip ip_info;
+	uint32_t gfx_ip_count = 0;
+	int r;
+
+	*gfx_ip_version_major = 0;
+
+	r = amdgpu_query_hw_ip_count(dev, AMDGPU_HW_IP_GFX, &gfx_ip_count);
+	if (r)
+		return r;
+
+	/* No graphics support. */
+	if (gfx_ip_count == 0)
+		return 0;
+
+	memset(&ip_info, 0, sizeof(ip_info));
+
+	r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_GFX, 0, &ip_info);
+	if (r)
+		return r;
+
+	/* GFX6-8 don't set ip_discovery_version. */
+	if (dev->minor_version >= 48 && ip_info.ip_discovery_version) {
+		*gfx_ip_version_major = (ip_info.ip_discovery_version >> 16) & 0xff;
+	} else {
+		*gfx_ip_version_major = ip_info.hw_ip_version_major;
+	}
+
+	return r;
+}
+
 static int _amdgpu_device_initialize(int fd,
 				     uint32_t *major_version,
 				     uint32_t *minor_version,
@@ -151,11 +184,13 @@ static int _amdgpu_device_initialize(int fd,
 				     bool deduplicate_device)
 {
 	struct amdgpu_device *dev = NULL;
+	uint8_t gfx_ip_version_major = 0;
 	drmVersionPtr version;
 	int r;
 	int flag_auth = 0;
 	int flag_authexist=0;
 	uint32_t accel_working = 0;
+	uint32_t va_mgr_flags = 0;
 
 	*device_handle = NULL;
 
@@ -244,12 +279,25 @@ static int _amdgpu_device_initialize(int fd,
 		goto cleanup;
 	}
 
-	amdgpu_va_manager_init(&dev->va_mgr,
+	r = amdgpu_query_gfx_level_major(dev, &gfx_ip_version_major);
+	if (!r) {
+		/* Split the HIGH addr space for GFX6-GFX12, except GFX9 to
+		 * implement a workaround for SMEM loads with NULL PRT pages.
+		 * This is silently ignored if querying the GFX level failed.
+		 */
+		if (gfx_ip_version_major >= 6 && gfx_ip_version_major <= 12 &&
+		    gfx_ip_version_major != 9) {
+			va_mgr_flags |= AMDGPU_VA_MGR_RESERVE_HALF_VA_FOR_PRT;
+		}
+	}
+
+	amdgpu_va_manager_init2(&dev->va_mgr,
 				dev->dev_info.virtual_address_offset,
 				dev->dev_info.virtual_address_max,
 				dev->dev_info.high_va_offset,
 				dev->dev_info.high_va_max,
-			       dev->dev_info.virtual_address_alignment);
+				dev->dev_info.virtual_address_alignment,
+				va_mgr_flags);
 
 	amdgpu_parse_asic_ids(dev);
 
@@ -322,6 +370,9 @@ drm_public int amdgpu_query_sw_info(amdgpu_device_handle dev,
 		else
 			*val32 = (dev->va_mgr.vamgr_32.va_max - 1) >> 32;
 		return 0;
+	case amdgpu_sw_info_address_prt_wa_control_bit:
+		*val32 = dev->va_mgr.address_prt_wa_control_bit;
+		return 0;
 	}
 	return -EINVAL;
 }

amdgpu/amdgpu_internal.h

@@ -72,6 +72,11 @@ struct amdgpu_va_manager {
 	struct amdgpu_bo_va_mgr vamgr_high;
 	/** The VA manager for the 32bit high address space */
 	struct amdgpu_bo_va_mgr vamgr_high_32;
+
+	/** The bit to control whether it's the "LOW" or "HIGH" halves, when
+	 *  half of the address space is reserved for PRT to implement a SW
+	 *  workaround. */
+	unsigned address_prt_wa_control_bit;
 };
 
 struct amdgpu_device {

amdgpu/amdgpu_vamgr.c

@@ -326,16 +326,39 @@ drm_public void amdgpu_va_manager_init(struct amdgpu_va_manager *va_mgr,
 				       uint64_t low_va_offset, uint64_t low_va_max,
 				       uint64_t high_va_offset, uint64_t high_va_max,
 				       uint32_t virtual_address_alignment)
+{
+	amdgpu_va_manager_init2(va_mgr, low_va_offset, low_va_max,
+				high_va_offset, high_va_max,
+				virtual_address_alignment, 0);
+}
+
+drm_public void amdgpu_va_manager_init2(struct amdgpu_va_manager *va_mgr,
+					uint64_t low_va_offset, uint64_t low_va_max,
+					uint64_t high_va_offset, uint64_t high_va_max,
+					uint32_t virtual_address_alignment,
+					uint32_t flags)
 {
 	uint64_t start, max;
 
+	va_mgr->address_prt_wa_control_bit = ~0;
+
 	start = low_va_offset;
 	max = MIN2(low_va_max, 0x100000000ULL);
 	amdgpu_vamgr_init(&va_mgr->vamgr_32, start, max,
 			  virtual_address_alignment);
 
 	start = max;
+	if ((flags & AMDGPU_VA_MGR_RESERVE_HALF_VA_FOR_PRT) && !high_va_max) {
+		/* Reserve the half VA range for PRT by splitting it in two
+		 * equal halves where one bit controls whether it's the LOW or
+		 * HIGH half.
+		 */
+		va_mgr->address_prt_wa_control_bit = util_last_bit64(low_va_offset ^ low_va_max) - 1;
+		max = low_va_max ^ (1ull << va_mgr->address_prt_wa_control_bit);
+	} else {
 		max = MAX2(low_va_max, 0x100000000ULL);
+	}
+
 	amdgpu_vamgr_init(&va_mgr->vamgr_low, start, max,
 			  virtual_address_alignment);
 
@@ -345,7 +368,17 @@ drm_public void amdgpu_va_manager_init(struct amdgpu_va_manager *va_mgr,
 			  virtual_address_alignment);
 
 	start = max;
+	if ((flags & AMDGPU_VA_MGR_RESERVE_HALF_VA_FOR_PRT) && high_va_max) {
+		/* Reserve the half VA range for PRT by splitting it in two
+		 * equal halves where one bit controls whether it's the LOW or
+		 * HIGH half.
+		 */
+		va_mgr->address_prt_wa_control_bit = util_last_bit64(high_va_offset ^ high_va_max) - 1;
+		max = high_va_max ^ (1ull << va_mgr->address_prt_wa_control_bit);
+	} else {
 		max = MAX2(high_va_max, (start & ~0xffffffffULL) + 0x100000000ULL);
+	}
+
 	amdgpu_vamgr_init(&va_mgr->vamgr_high, start, max,
 			  virtual_address_alignment);
 }
@@ -357,3 +390,17 @@ drm_public void amdgpu_va_manager_deinit(struct amdgpu_va_manager *va_mgr)
 	amdgpu_vamgr_deinit(&va_mgr->vamgr_high_32);
 	amdgpu_vamgr_deinit(&va_mgr->vamgr_high);
 }
+
+drm_public int amdgpu_va_manager_query_sw_info(struct amdgpu_va_manager *va_mgr,
+					       enum amdgpu_va_manager_sw_info info,
+					       void *value)
+{
+	uint32_t *val32 = (uint32_t*)value;
+
+	switch (info) {
+	case amdgpu_va_manager_sw_info_address_prt_wa_control_bit:
+		*val32 = va_mgr->address_prt_wa_control_bit;
+		return 0;
+	}
+	return -EINVAL;
+}

data/amdgpu.ids

@@ -8,6 +8,19 @@
 1114,	C3,	AMD Radeon 840M Graphics
 1114,	D2,	AMD Radeon 860M Graphics
 1114,	D3,	AMD Radeon 840M Graphics
+1114,	E2,	AMD Radeon 860M Graphics
+1114,	E4,	AMD Radeon 860M Graphics
+1114,	E5,	AMD Radeon 840M Graphics
+1114,	E9,	AMD Radeon 860M Graphics
+1114,	EA,	AMD Radeon 840M Graphics
+1114,	ED,	AMD Radeon 860M Graphics
+1114,	EE,	AMD Radeon 840M Graphics
+1114,	F2,	AMD Radeon 860M Graphics
+1114,	F3,	AMD Radeon 840M Graphics
+1114,	F9,	AMD Radeon 860M Graphics
+1114,	FA,	AMD Radeon 840M Graphics
+1114,	FC,	AMD Radeon 860M Graphics
+1114,	FD,	AMD Radeon 840M Graphics
 1309,	00,	AMD Radeon R7 Graphics
 130A,	00,	AMD Radeon R6 Graphics
 130B,	00,	AMD Radeon R4 Graphics
@@ -39,23 +52,35 @@
 1506,	C3,	AMD Radeon 610M
 1506,	C4,	AMD Radeon 610M
 150E,	C1,	AMD Radeon 890M Graphics
-150E,	C4,	AMD Radeon 890M Graphics
+150E,	C4,	AMD Radeon 880M Graphics
 150E,	C5,	AMD Radeon 890M Graphics
 150E,	C6,	AMD Radeon 890M Graphics
+150E,	C7,	AMD Radeon 890M Graphics
 150E,	D1,	AMD Radeon 890M Graphics
-150E,	D2,	AMD Radeon 890M Graphics
+150E,	D2,	AMD Radeon 880M Graphics
 150E,	D3,	AMD Radeon 890M Graphics
-1586,	C1,	Radeon 8060S Graphics
+150E,	E1,	AMD Radeon 890M Graphics
-1586,	C2,	Radeon 8050S Graphics
+150E,	E3,	AMD Radeon 890M Graphics
-1586,	C4,	Radeon 8050S Graphics
+150E,	E4,	AMD Radeon 890M Graphics
-1586,	D1,	Radeon 8060S Graphics
+150E,	F1,	AMD Radeon 890M Graphics
-1586,	D2,	Radeon 8050S Graphics
+150E,	F3,	AMD Radeon 890M Graphics
-1586,	D4,	Radeon 8050S Graphics
+1586,	C1,	AMD Radeon 8060S Graphics
-1586,	D5,	Radeon 8040S Graphics
+1586,	C2,	AMD Radeon 8050S Graphics
+1586,	C3,	AMD Radeon 8060S Graphics
+1586,	C4,	AMD Radeon 8050S Graphics
+1586,	C6,	AMD Radeon 8060S Graphics
+1586,	D1,	AMD Radeon 8060S Graphics
+1586,	D2,	AMD Radeon 8050S Graphics
+1586,	D4,	AMD Radeon 8050S Graphics
+1586,	D5,	AMD Radeon 8040S Graphics
 15BF,	00,	AMD Radeon 780M Graphics
 15BF,	01,	AMD Radeon 760M Graphics
 15BF,	02,	AMD Radeon 780M Graphics
 15BF,	03,	AMD Radeon 760M Graphics
+15BF,	05,	AMD Radeon 760M Graphics
+15BF,	06,	AMD Radeon 780M Graphics
+15BF,	07,	AMD Radeon 740M Graphics
+15BF,	08,	AMD Radeon 740M Graphics
 15BF,	C1,	AMD Radeon 780M Graphics
 15BF,	C2,	AMD Radeon 780M Graphics
 15BF,	C3,	AMD Radeon 760M Graphics
@@ -69,6 +94,7 @@
 15BF,	CB,	AMD Radeon 760M Graphics
 15BF,	CC,	AMD Radeon 740M Graphics
 15BF,	CD,	AMD Radeon 760M Graphics
+15BF,	CE,	AMD Radeon 740M Graphics
 15BF,	CF,	AMD Radeon 780M Graphics
 15BF,	D0,	AMD Radeon 780M Graphics
 15BF,	D1,	AMD Radeon 780M Graphics
@@ -91,10 +117,18 @@
 15C8,	C2,	AMD Radeon 740M Graphics
 15C8,	C3,	AMD Radeon 740M Graphics
 15C8,	C4,	AMD Radeon 740M Graphics
+15C8,	C5,	AMD Radeon 740M Graphics
+15C8,	C6,	AMD Radeon 740M Graphics
+15C8,	C7,	AMD Radeon 740M Graphics
+15C8,	C8,	AMD Radeon 740M Graphics
 15C8,	D1,	AMD Radeon 740M Graphics
 15C8,	D2,	AMD Radeon 740M Graphics
 15C8,	D3,	AMD Radeon 740M Graphics
 15C8,	D4,	AMD Radeon 740M Graphics
+15C8,	D5,	AMD Radeon 740M Graphics
+15C8,	D6,	AMD Radeon 740M Graphics
+15C8,	D7,	AMD Radeon 740M Graphics
+15C8,	D8,	AMD Radeon 740M Graphics
 15D8,	00,	AMD Radeon RX Vega 8 Graphics WS
 15D8,	91,	AMD Radeon Vega 3 Graphics
 15D8,	91,	AMD Ryzen Embedded R1606G with Radeon Vega Gfx
@@ -250,6 +284,19 @@
 1901,	D6,	AMD Radeon 740M Graphics
 1901,	D7,	AMD Radeon 740M Graphics
 1901,	D8,	AMD Radeon 740M Graphics
+1902,	C0,	AMD Radeon 840M Graphics
+1902,	C1,	AMD Radeon 840M Graphics
+1902,	C2,	AMD Radeon 820M Graphics
+1902,	C3,	AMD Radeon 840M Graphics
+1902,	C6,	AMD Radeon 820M Graphics
+1902,	C7,	AMD Radeon 840M Graphics
+1902,	C8,	AMD Radeon 840M Graphics
+1902,	C9,	AMD Radeon 820M Graphics
+1902,	CA,	AMD Radeon 840M Graphics
+1902,	D1,	AMD Radeon 840M Graphics
+1902,	D3,	AMD Radeon 840M Graphics
+1902,	D7,	AMD Radeon 840M Graphics
+1902,	D8,	AMD Radeon 840M Graphics
 6600,	00,	AMD Radeon HD 8600 / 8700M
 6600,	81,	AMD Radeon R7 M370
 6601,	00,	AMD Radeon HD 8500M / 8700M
@@ -577,6 +624,7 @@
 7480,	C3,	AMD Radeon RX 7600S
 7480,	C7,	AMD Radeon RX 7600M XT
 7480,	CF,	AMD Radeon RX 7600
+7481,   C7,     AMD Steam Machine
 7483,	CF,	AMD Radeon RX 7600M
 7489,	00,	AMD Radeon Pro W7500
 7499,	00,	AMD Radeon Pro W7400
@@ -595,12 +643,14 @@
 7550,	C2,	AMD Radeon RX 9070 GRE
 7550,	C3,	AMD Radeon RX 9070
 7551,	C0,	AMD Radeon AI PRO R9700
+7551,	C8,	AMD Radeon AI PRO R9600D
 7590,	C0,	AMD Radeon RX 9060 XT
+7590,	C1,	AMD Radeon RX 9060 XT LP
 7590,	C7,	AMD Radeon RX 9060
-75A0,	C0,	AMD Instinct MI350X
+75A0,	00,	AMD Instinct MI350X
-75A3,	C0,	AMD Instinct MI355X
+75A3,	00,	AMD Instinct MI355X
-75B0,	C0,	AMD Instinct MI350X VF
+75B0,	00,	AMD Instinct MI350X VF
-75B3,	C0,	AMD Instinct MI355X VF
+75B3,	00,	AMD Instinct MI355X VF
 9830,	00,	AMD Radeon HD 8400 / R3 Series
 9831,	00,	AMD Radeon HD 8400E
 9832,	00,	AMD Radeon HD 8330

gen_table_fourcc.py

@@ -34,7 +34,7 @@ towrite = sys.argv[2]
 
 fm_re = {
     'intel': r'^#define I915_FORMAT_MOD_(\w+)',
-    'others': r'^#define DRM_FORMAT_MOD_((?:ARM|SAMSUNG|QCOM|VIVANTE|NVIDIA|BROADCOM|ALLWINNER)\w+)\s',
+    'others': r'^#define DRM_FORMAT_MOD_((?:ARM|APPLE|SAMSUNG|QCOM|VIVANTE|NVIDIA|BROADCOM|ALLWINNER)\w+)\s',
     'vendors': r'^#define DRM_FORMAT_MOD_VENDOR_(\w+)'
 }
 

include/drm/drm.h

@@ -900,6 +900,21 @@ struct drm_get_cap {
  */
 #define DRM_CLIENT_CAP_CURSOR_PLANE_HOTSPOT	6
 
+/**
+ * DRM_CLIENT_CAP_PLANE_COLOR_PIPELINE
+ *
+ * If set to 1 the DRM core will allow setting the COLOR_PIPELINE
+ * property on a &drm_plane, as well as drm_colorop properties.
+ *
+ * Setting of these plane properties will be rejected when this client
+ * cap is set:
+ * - COLOR_ENCODING
+ * - COLOR_RANGE
+ *
+ * The client must enable &DRM_CLIENT_CAP_ATOMIC first.
+ */
+#define DRM_CLIENT_CAP_PLANE_COLOR_PIPELINE	7
+
 /* DRM_IOCTL_SET_CLIENT_CAP ioctl argument type */
 struct drm_set_client_cap {
 	__u64 capability;

include/drm/drm_fourcc.h

@@ -979,14 +979,20 @@ extern "C" {
  *               2 = Gob Height 8, Turing+ Page Kind mapping
  *               3 = Reserved for future use.
  *
- * 22:22 s     Sector layout.  On Tegra GPUs prior to Xavier, there is a further
+ * 22:22 s     Sector layout.  There is a further bit remapping step that occurs
- *             bit remapping step that occurs at an even lower level than the
+ * 26:27       at an even lower level than the page kind and block linear
- *             page kind and block linear swizzles.  This causes the layout of
+ *             swizzles.  This causes the bit arrangement of surfaces in memory
- *             surfaces mapped in those SOC's GPUs to be incompatible with the
+ *             to differ subtly, and prevents direct sharing of surfaces between
- *             equivalent mapping on other GPUs in the same system.
+ *             GPUs with different layouts.
  *
- *               0 = Tegra K1 - Tegra Parker/TX2 Layout.
+ *               0 = Tegra K1 - Tegra Parker/TX2 Layout
- *               1 = Desktop GPU and Tegra Xavier+ Layout
+ *               1 = Pre-GB20x, GB20x 32+ bpp, GB10, Tegra Xavier-Orin Layout
+ *               2 = GB20x(Blackwell 2)+ 8 bpp surface layout
+ *               3 = GB20x(Blackwell 2)+ 16 bpp surface layout
+ *               4 = Reserved for future use.
+ *               5 = Reserved for future use.
+ *               6 = Reserved for future use.
+ *               7 = Reserved for future use.
  *
  * 25:23 c     Lossless Framebuffer Compression type.
  *
@@ -1001,7 +1007,7 @@ extern "C" {
  *               6 = Reserved for future use
  *               7 = Reserved for future use
  *
- * 55:25 -     Reserved for future use.  Must be zero.
+ * 55:28 -     Reserved for future use.  Must be zero.
  */
 #define DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(c, s, g, k, h) \
 	fourcc_mod_code(NVIDIA, (0x10 | \
@@ -1009,6 +1015,7 @@ extern "C" {
 				 (((k) & 0xff) << 12) | \
 				 (((g) & 0x3) << 20) | \
 				 (((s) & 0x1) << 22) | \
+				 (((s) & 0x6) << 25) | \
 				 (((c) & 0x7) << 23)))
 
 /* To grandfather in prior block linear format modifiers to the above layout,

include/drm/drm_mode.h

@@ -629,6 +629,7 @@ struct drm_mode_connector_set_property {
 #define DRM_MODE_OBJECT_FB 0xfbfbfbfb
 #define DRM_MODE_OBJECT_BLOB 0xbbbbbbbb
 #define DRM_MODE_OBJECT_PLANE 0xeeeeeeee
+#define DRM_MODE_OBJECT_COLOROP 0xfafafafa
 #define DRM_MODE_OBJECT_ANY 0
 
 struct drm_mode_obj_get_properties {
@@ -846,6 +847,20 @@ struct drm_color_ctm {
 	__u64 matrix[9];
 };
 
+struct drm_color_ctm_3x4 {
+	/*
+	 * Conversion matrix with 3x4 dimensions in S31.32 sign-magnitude
+	 * (not two's complement!) format.
+	 *
+	 * out   matrix          in
+	 * |R|   |0  1  2  3 |   | R |
+	 * |G| = |4  5  6  7 | x | G |
+	 * |B|   |8  9  10 11|   | B |
+	 *                       |1.0|
+	 */
+	__u64 matrix[12];
+};
+
 struct drm_color_lut {
 	/*
 	 * Values are mapped linearly to 0.0 - 1.0 range, with 0x0 == 0.0 and
@@ -857,6 +872,125 @@ struct drm_color_lut {
 	__u16 reserved;
 };
 
+/*
+ * struct drm_color_lut32
+ *
+ * 32-bit per channel color LUT entry, similar to drm_color_lut.
+ */
+struct drm_color_lut32 {
+	__u32 red;
+	__u32 green;
+	__u32 blue;
+	__u32 reserved;
+};
+
+/**
+ * enum drm_colorop_type - Type of color operation
+ *
+ * drm_colorops can be of many different types. Each type behaves differently
+ * and defines a different set of properties. This enum defines all types and
+ * gives a high-level description.
+ */
+enum drm_colorop_type {
+	/**
+	 * @DRM_COLOROP_1D_CURVE:
+	 *
+	 * enum string "1D Curve"
+	 *
+	 * A 1D curve that is being applied to all color channels. The
+	 * curve is specified via the CURVE_1D_TYPE colorop property.
+	 */
+	DRM_COLOROP_1D_CURVE,
+
+	/**
+	 * @DRM_COLOROP_1D_LUT:
+	 *
+	 * enum string "1D LUT"
+	 *
+	 * A simple 1D LUT of uniformly spaced &drm_color_lut32 entries,
+	 * packed into a blob via the DATA property. The driver's
+	 * expected LUT size is advertised via the SIZE property.
+	 *
+	 * The DATA blob is an array of struct drm_color_lut32 with size
+	 * of "size".
+	 */
+	DRM_COLOROP_1D_LUT,
+
+	/**
+	 * @DRM_COLOROP_CTM_3X4:
+	 *
+	 * enum string "3x4 Matrix"
+	 *
+	 * A 3x4 matrix. Its values are specified via the
+	 * &drm_color_ctm_3x4 struct provided via the DATA property.
+	 *
+	 * The DATA blob is a float[12]:
+	 * out   matrix          in
+	 * | R |   | 0  1  2  3  |   | R |
+	 * | G | = | 4  5  6  7  | x | G |
+	 * | B |   | 8  9  10 12 |   | B |
+	 */
+	DRM_COLOROP_CTM_3X4,
+
+	/**
+	 * @DRM_COLOROP_MULTIPLIER:
+	 *
+	 * enum string "Multiplier"
+	 *
+	 * A simple multiplier, applied to all color values. The
+	 * multiplier is specified as a S31.32 via the MULTIPLIER
+	 * property.
+	 */
+	DRM_COLOROP_MULTIPLIER,
+
+	/**
+	 * @DRM_COLOROP_3D_LUT:
+	 *
+	 * enum string "3D LUT"
+	 *
+	 * A 3D LUT of &drm_color_lut32 entries,
+	 * packed into a blob via the DATA property. The driver's expected
+	 * LUT size is advertised via the SIZE property, i.e., a 3D LUT with
+	 * 17x17x17 entries will have SIZE set to 17.
+	 *
+	 * The DATA blob is a 3D array of struct drm_color_lut32 with dimension
+	 * length of "size".
+	 * The LUT elements are traversed like so:
+	 *
+	 *   for B in range 0..n
+	 *     for G in range 0..n
+	 *       for R in range 0..n
+	 *        index = R + n * (G + n * B)
+	 *         color = lut3d[index]
+	 */
+	DRM_COLOROP_3D_LUT,
+};
+
+/**
+ * enum drm_colorop_lut3d_interpolation_type - type of 3DLUT interpolation
+ */
+enum drm_colorop_lut3d_interpolation_type {
+	/**
+	 * @DRM_COLOROP_LUT3D_INTERPOLATION_TETRAHEDRAL:
+	 *
+	 * Tetrahedral 3DLUT interpolation
+	 */
+	DRM_COLOROP_LUT3D_INTERPOLATION_TETRAHEDRAL,
+};
+
+/**
+ * enum drm_colorop_lut1d_interpolation_type - type of interpolation for 1D LUTs
+ */
+enum drm_colorop_lut1d_interpolation_type {
+	/**
+	 * @DRM_COLOROP_LUT1D_INTERPOLATION_LINEAR:
+	 *
+	 * Linear interpolation. Values between points of the LUT will be
+	 * linearly interpolated.
+	 */
+	DRM_COLOROP_LUT1D_INTERPOLATION_LINEAR,
+};
+
 /**
  * struct drm_plane_size_hint - Plane size hints
  * @width: The width of the plane in pixel

include/drm/virtgpu_drm.h

@@ -46,12 +46,16 @@ extern "C" {
 #define DRM_VIRTGPU_TRANSFER_TO_HOST 0x07
 #define DRM_VIRTGPU_WAIT     0x08
 #define DRM_VIRTGPU_GET_CAPS  0x09
+#define DRM_VIRTGPU_RESOURCE_CREATE_BLOB 0x0a
+#define DRM_VIRTGPU_CONTEXT_INIT 0x0b
 
 #define VIRTGPU_EXECBUF_FENCE_FD_IN	0x01
 #define VIRTGPU_EXECBUF_FENCE_FD_OUT	0x02
+#define VIRTGPU_EXECBUF_RING_IDX	0x04
 #define VIRTGPU_EXECBUF_FLAGS  (\
 		VIRTGPU_EXECBUF_FENCE_FD_IN |\
 		VIRTGPU_EXECBUF_FENCE_FD_OUT |\
+		VIRTGPU_EXECBUF_RING_IDX |\
 		0)
 
 struct drm_virtgpu_map {
@@ -60,6 +64,17 @@ struct drm_virtgpu_map {
 	__u32 pad;
 };
 
+#define VIRTGPU_EXECBUF_SYNCOBJ_RESET		0x01
+#define VIRTGPU_EXECBUF_SYNCOBJ_FLAGS ( \
+		VIRTGPU_EXECBUF_SYNCOBJ_RESET | \
+		0)
+struct drm_virtgpu_execbuffer_syncobj {
+	__u32 handle;
+	__u32 flags;
+	__u64 point;
+};
+
+/* fence_fd is modified on success if VIRTGPU_EXECBUF_FENCE_FD_OUT flag is set. */
 struct drm_virtgpu_execbuffer {
 	__u32 flags;
 	__u32 size;
@@ -67,10 +82,22 @@ struct drm_virtgpu_execbuffer {
 	__u64 bo_handles;
 	__u32 num_bo_handles;
 	__s32 fence_fd; /* in/out fence fd (see VIRTGPU_EXECBUF_FENCE_FD_IN/OUT) */
+	__u32 ring_idx; /* command ring index (see VIRTGPU_EXECBUF_RING_IDX) */
+	__u32 syncobj_stride; /* size of @drm_virtgpu_execbuffer_syncobj */
+	__u32 num_in_syncobjs;
+	__u32 num_out_syncobjs;
+	__u64 in_syncobjs;
+	__u64 out_syncobjs;
 };
 
 #define VIRTGPU_PARAM_3D_FEATURES 1 /* do we have 3D features in the hw */
 #define VIRTGPU_PARAM_CAPSET_QUERY_FIX 2 /* do we have the capset fix */
+#define VIRTGPU_PARAM_RESOURCE_BLOB 3 /* DRM_VIRTGPU_RESOURCE_CREATE_BLOB */
+#define VIRTGPU_PARAM_HOST_VISIBLE 4 /* Host blob resources are mappable */
+#define VIRTGPU_PARAM_CROSS_DEVICE 5 /* Cross virtio-device resource sharing  */
+#define VIRTGPU_PARAM_CONTEXT_INIT 6 /* DRM_VIRTGPU_CONTEXT_INIT */
+#define VIRTGPU_PARAM_SUPPORTED_CAPSET_IDs 7 /* Bitmask of supported capability set ids */
+#define VIRTGPU_PARAM_EXPLICIT_DEBUG_NAME 8 /* Ability to set debug name from userspace */
 
 struct drm_virtgpu_getparam {
 	__u64 param;
@@ -100,7 +127,7 @@ struct drm_virtgpu_resource_info {
 	__u32 bo_handle;
 	__u32 res_handle;
 	__u32 size;
-	__u32 stride;
+	__u32 blob_mem;
 };
 
 struct drm_virtgpu_3d_box {
@@ -117,6 +144,8 @@ struct drm_virtgpu_3d_transfer_to_host {
 	struct drm_virtgpu_3d_box box;
 	__u32 level;
 	__u32 offset;
+	__u32 stride;
+	__u32 layer_stride;
 };
 
 struct drm_virtgpu_3d_transfer_from_host {
@@ -124,6 +153,8 @@ struct drm_virtgpu_3d_transfer_from_host {
 	struct drm_virtgpu_3d_box box;
 	__u32 level;
 	__u32 offset;
+	__u32 stride;
+	__u32 layer_stride;
 };
 
 #define VIRTGPU_WAIT_NOWAIT 1 /* like it */
@@ -132,6 +163,12 @@ struct drm_virtgpu_3d_wait {
 	__u32 flags;
 };
 
+#define VIRTGPU_DRM_CAPSET_VIRGL 1
+#define VIRTGPU_DRM_CAPSET_VIRGL2 2
+#define VIRTGPU_DRM_CAPSET_GFXSTREAM_VULKAN 3
+#define VIRTGPU_DRM_CAPSET_VENUS 4
+#define VIRTGPU_DRM_CAPSET_CROSS_DOMAIN 5
+#define VIRTGPU_DRM_CAPSET_DRM 6
 struct drm_virtgpu_get_caps {
 	__u32 cap_set_id;
 	__u32 cap_set_ver;
@@ -140,6 +177,55 @@ struct drm_virtgpu_get_caps {
 	__u32 pad;
 };
 
+struct drm_virtgpu_resource_create_blob {
+#define VIRTGPU_BLOB_MEM_GUEST             0x0001
+#define VIRTGPU_BLOB_MEM_HOST3D            0x0002
+#define VIRTGPU_BLOB_MEM_HOST3D_GUEST      0x0003
+
+#define VIRTGPU_BLOB_FLAG_USE_MAPPABLE     0x0001
+#define VIRTGPU_BLOB_FLAG_USE_SHAREABLE    0x0002
+#define VIRTGPU_BLOB_FLAG_USE_CROSS_DEVICE 0x0004
+	/* zero is invalid blob_mem */
+	__u32 blob_mem;
+	__u32 blob_flags;
+	__u32 bo_handle;
+	__u32 res_handle;
+	__u64 size;
+
+	/*
+	 * for 3D contexts with VIRTGPU_BLOB_MEM_HOST3D_GUEST and
+	 * VIRTGPU_BLOB_MEM_HOST3D otherwise, must be zero.
+	 */
+	__u32 pad;
+	__u32 cmd_size;
+	__u64 cmd;
+	__u64 blob_id;
+};
+
+#define VIRTGPU_CONTEXT_PARAM_CAPSET_ID       0x0001
+#define VIRTGPU_CONTEXT_PARAM_NUM_RINGS       0x0002
+#define VIRTGPU_CONTEXT_PARAM_POLL_RINGS_MASK 0x0003
+#define VIRTGPU_CONTEXT_PARAM_DEBUG_NAME      0x0004
+struct drm_virtgpu_context_set_param {
+	__u64 param;
+	__u64 value;
+};
+
+struct drm_virtgpu_context_init {
+	__u32 num_params;
+	__u32 pad;
+
+	/* pointer to drm_virtgpu_context_set_param array */
+	__u64 ctx_set_params;
+};
+
+/*
+ * Event code that's given when VIRTGPU_CONTEXT_PARAM_POLL_RINGS_MASK is in
+ * effect.  The event size is sizeof(drm_event), since there is no additional
+ * payload.
+ */
+#define VIRTGPU_EVENT_FENCE_SIGNALED 0x90000000
+
 #define DRM_IOCTL_VIRTGPU_MAP \
 	DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_MAP, struct drm_virtgpu_map)
 
@@ -175,6 +261,14 @@ struct drm_virtgpu_get_caps {
 	DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_GET_CAPS, \
 	struct drm_virtgpu_get_caps)
 
+#define DRM_IOCTL_VIRTGPU_RESOURCE_CREATE_BLOB				\
+	DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_RESOURCE_CREATE_BLOB,	\
+		struct drm_virtgpu_resource_create_blob)
+
+#define DRM_IOCTL_VIRTGPU_CONTEXT_INIT					\
+	DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_CONTEXT_INIT,		\
+		struct drm_virtgpu_context_init)
+
 #if defined(__cplusplus)
 }
 #endif

meson.build

@@ -26,7 +26,7 @@
 project(
   'libdrm',
   ['c'],
-  version : '2.4.129',
+  version : '2.4.133',
   license : 'MIT',
   meson_version : '>= 0.59',
   default_options : ['buildtype=debugoptimized', 'c_std=c11'],
@@ -51,6 +51,8 @@ dep_threads = dependency('threads')
 
 cc = meson.get_compiler('c')
 
+config.set10('HAVE_SECURE_GETENV', cc.has_function('secure_getenv'))
+
 android = cc.compiles('''int func() { return __ANDROID__; }''')
 
 # Solaris / Illumos

meson_options.txt

@@ -46,13 +46,11 @@ option(
 option(
   'omap',
   type : 'feature',
-  value : 'disabled',
   description : '''Enable support for OMAP's experimental KMS API.''',
 )
 option(
   'exynos',
   type : 'feature',
-  value : 'disabled',
   description : '''Enable support for EXYNOS's experimental KMS API.''',
 )
 option(
@@ -63,7 +61,6 @@ option(
 option(
   'tegra',
   type : 'feature',
-  value : 'disabled',
   description : '''Enable support for Tegra's experimental KMS API.''',
 )
 option(

omap/omap_drm.c

@@ -27,7 +27,6 @@
  */
 
 #include <stdlib.h>
-#include <linux/types.h>
 #include <errno.h>
 #include <sys/mman.h>
 #include <fcntl.h>
@@ -41,10 +40,6 @@
 #include "omap_drm.h"
 #include "omap_drmif.h"
 
-#define __round_mask(x, y) ((__typeof__(x))((y)-1))
-#define round_up(x, y) ((((x)-1) | __round_mask(x, y))+1)
-#define PAGE_SIZE 4096
-
 static pthread_mutex_t table_lock = PTHREAD_MUTEX_INITIALIZER;
 static void * dev_table;
 
@@ -207,12 +202,6 @@ static struct omap_bo * omap_bo_new_impl(struct omap_device *dev,
 	bo = bo_from_handle(dev, req.handle);
 	pthread_mutex_unlock(&table_lock);
 
-	if (flags & OMAP_BO_TILED) {
-		bo->size = round_up(size.tiled.width, PAGE_SIZE) * size.tiled.height;
-	} else {
-		bo->size = size.bytes;
-	}
-
 	return bo;
 
 fail:
@@ -432,7 +421,7 @@ drm_public uint32_t omap_bo_size(struct omap_bo *bo)
 drm_public void *omap_bo_map(struct omap_bo *bo)
 {
 	if (!bo->map) {
-		if (!bo->offset) {
+		if (!bo->size || !bo->offset) {
 			get_buffer_info(bo);
 		}
 

tests/modetest/modetest.c

@@ -1974,7 +1974,8 @@ static int parse_connector(struct pipe_arg *pipe, const char *arg)
 	unsigned int len;
 	unsigned int i;
 	const char *p;
-	char *endp;
+	const char *endp;
+	char *endp_tok;
 
 	pipe->vrefresh = 0;
 	pipe->crtc_id = (uint32_t)-1;
@@ -2012,7 +2013,8 @@ static int parse_connector(struct pipe_arg *pipe, const char *arg)
 		return -1;
 	if (*endp == '@') {
 		arg = endp + 1;
-		pipe->crtc_id = strtoul(arg, &endp, 10);
+		pipe->crtc_id = strtoul(arg, &endp_tok, 10);
+		endp = endp_tok;
 	}
 	if (*endp != ':')
 		return -1;
@@ -2028,8 +2030,8 @@ static int parse_connector(struct pipe_arg *pipe, const char *arg)
 	pipe->mode_str[len] = '\0';
 
 	if (*p == '-') {
-		pipe->vrefresh = strtof(p + 1, &endp);
+		pipe->vrefresh = strtof(p + 1, &endp_tok);
-		p = endp;
+		p = endp_tok;
 	}
 
 	if (*p == '@') {

util_math.h

@@ -24,6 +24,8 @@
 #ifndef _UTIL_MATH_H_
 #define _UTIL_MATH_H_
 
+#include <stdint.h>
+
 #define MIN2( A, B )   ( (A)<(B) ? (A) : (B) )
 #define MAX2( A, B )   ( (A)>(B) ? (A) : (B) )
 #define MAX3( A, B, C ) ((A) > (B) ? MAX2(A, C) : MAX2(B, C))
@@ -31,4 +33,25 @@
 #define __align_mask(value, mask)  (((value) + (mask)) & ~(mask))
 #define ALIGN(value, alignment)    __align_mask(value, (__typeof__(value))((alignment) - 1))
 
+static inline unsigned
+util_last_bit64(uint64_t u)
+{
+#if defined(HAVE___BUILTIN_CLZLL)
+	return u == 0 ? 0 : 64 - __builtin_clzll(u);
+#elif defined(_MSC_VER) && (_M_AMD64 || _M_ARM64 || _M_IA64)
+	unsigned long index;
+	if (_BitScanReverse64(&index, u))
+		return index + 1;
+	else
+		return 0;
+#else
+	unsigned r = 0;
+	while (u) {
+		r++;
+		u >>= 1;
+	}
+	return r;
+#endif
+}
+
 #endif /*_UTIL_MATH_H_*/

xf86drm.c

@@ -348,9 +348,10 @@ drmGetFormatModifierNameFromNvidia(uint64_t modifier)
      * testing against TEGRA_TILE */
     if ((modifier & 0x10) == 0x10) {
         char *mod_nvidia;
-        asprintf(&mod_nvidia, "BLOCK_LINEAR_2D,HEIGHT=%"PRIu64",KIND=%"PRIu64","
+        if (asprintf(&mod_nvidia, "BLOCK_LINEAR_2D,HEIGHT=%"PRIu64",KIND=%"PRIu64","
                  "GEN=%"PRIu64",SECTOR=%"PRIu64",COMPRESSION=%"PRIu64"", height,
-                 kind, gen, sector, compression);
+                 kind, gen, sector, compression) < 0)
+            mod_nvidia = NULL;
         return mod_nvidia;
     }
 
@@ -542,7 +543,8 @@ drmGetFormatModifierNameFromAmlogic(uint64_t modifier)
     else
         opts_str = "0";
 
-    asprintf(&mod_amlogic, "FBC,LAYOUT=%s,OPTIONS=%s", layout_str, opts_str);
+    if (asprintf(&mod_amlogic, "FBC,LAYOUT=%s,OPTIONS=%s", layout_str, opts_str) < 0)
+        mod_amlogic = NULL;
     return mod_amlogic;
 }
 
@@ -606,7 +608,8 @@ drmGetFormatModifierNameFromVivante(uint64_t modifier)
 	break;
     }
 
-    asprintf(&mod_vivante, "%s%s%s", color_tiling, tile_status, compression);
+    if (asprintf(&mod_vivante, "%s%s%s", color_tiling, tile_status, compression) < 0)
+        mod_vivante = NULL;
     return mod_vivante;
 }