amdgpu: update marketing names for strix point revisions

Signed-off-by: Simon Ser <contact@emersion.fr>

README.rst

@@ -49,3 +49,15 @@ Then use ninja to build and install:
 
 If you are installing into a system location you will need to run install
 separately, and as root.
+
+AMDGPU ASIC table file
+----------------------
+
+The AMDGPU driver requires the `amdgpu.ids` file. It is usually located at
+`$PREFIX/share/libdrm`, but it is possible to specify a set of alternative
+paths at runtime by setting the `AMDGPU_ASIC_ID_TABLE_PATHS` environment
+variable with one or more colon-separated paths where to search for the
+`amdgpu.ids` file.
+
+For this option to be available, the C library must support secure_getenv()
+function. In systems without it (like NetBSD), this option won't be available.

amdgpu/amdgpu_asic_id.c

@@ -22,6 +22,11 @@
  *
  */
 
+// secure_getenv requires _GNU_SOURCE
+#ifndef _GNU_SOURCE
+#define _GNU_SOURCE
+#endif
+
 #include <ctype.h>
 #include <stdio.h>
 #include <stdlib.h>
@@ -104,6 +109,168 @@ out:
 	return r;
 }
 
+static void amdgpu_parse_proc_cpuinfo(struct amdgpu_device *dev)
+{
+	const char *search_key = "model name";
+	const char *radeon_key = "Radeon";
+	char *line = NULL;
+	size_t len = 0;
+	FILE *fp;
+
+	fp = fopen("/proc/cpuinfo", "r");
+	if (fp == NULL) {
+		fprintf(stderr, "%s\n", strerror(errno));
+		return;
+	}
+
+	while (getline(&line, &len, fp) != -1) {
+		char *saveptr;
+		char *value;
+
+		if (strncmp(line, search_key, strlen(search_key)))
+			continue;
+
+		/* check for parts that have both CPU and GPU information */
+		value = strstr(line, radeon_key);
+
+		/* get content after the first colon */
+		if (value == NULL) {
+			value = strstr(line, ":");
+			if (value == NULL)
+				continue;
+			value++;
+		}
+
+		/* strip whitespace */
+		while (*value == ' ' || *value == '\t')
+			value++;
+		saveptr = strchr(value, '\n');
+		if (saveptr)
+			*saveptr = '\0';
+
+		/* Add AMD to the new string if it's missing from slicing/dicing */
+		if (strncmp(value, "AMD", 3) != 0) {
+			char *tmp = malloc(strlen(value) + 5);
+
+			if (!tmp)
+				break;
+			sprintf(tmp, "AMD %s", value);
+			dev->marketing_name = tmp;
+		} else
+			dev->marketing_name = strdup(value);
+		break;
+	}
+
+	free(line);
+	fclose(fp);
+}
+
+#if HAVE_SECURE_GETENV
+static char *join_path(const char *dir, const char *file) {
+	size_t dir_len = strlen(dir);
+	size_t file_len = strlen(file);
+	char *full_path = NULL;
+
+	int need_slash = ((dir_len > 0) && (dir[dir_len - 1] != '/'));
+	size_t total_len = dir_len + (need_slash ? 1 : 0) + file_len + 1; // +1 for null terminator
+
+	if (dir_len == 0) {
+		return strdup(file);
+	}
+
+	full_path = malloc(total_len);
+	if (!full_path) {
+		return NULL; // Memory allocation failed
+	}
+
+	strcpy(full_path, dir);
+	if (need_slash) {
+		full_path[dir_len] = '/';
+		dir_len++;
+	}
+	strcpy(full_path + dir_len, file);
+
+	return full_path;
+}
+
+static char **split_env_var(const char *env_var_content)
+{
+	char **ret = NULL;
+	char *dup_env_val;
+	int elements = 1;
+	int index = 1;
+
+	if (!env_var_content || env_var_content[0] == '\0')
+		return NULL;
+
+	for(char *p = (char *)env_var_content; *p; p++) {
+		if (*p == ':')
+			elements++;
+	}
+
+	dup_env_val = strdup(env_var_content);
+	if (!dup_env_val) {
+		return NULL;
+	}
+	ret = malloc(sizeof(char *) * (elements + 1));
+	ret[0] = dup_env_val;
+	for(char *p = (char *)dup_env_val; *p; p++) {
+		if (*p == ':') {
+			*p = 0;
+			ret[index++] = p + 1;
+		}
+	}
+	ret[index] = NULL; // ensure that the last element in the array is NULL
+	return ret;
+}
+
+static void split_env_var_free(char **split_var)
+{
+	if (split_var) {
+		// remember that the first element also points to the whole duplicated string,
+		// which was modified in place by replacing ':' with '\0' characters
+		free(split_var[0]);
+		free(split_var);
+	}
+}
+
+static char *find_asic_id_table(void)
+{
+	// first check the paths in AMDGPU_ASIC_ID_TABLE_PATHS environment variable
+	const char *amdgpu_asic_id_table_paths = secure_getenv("AMDGPU_ASIC_ID_TABLE_PATHS");
+	char *file_name = NULL;
+	char *found_path = NULL;
+	char **paths = NULL;
+
+	if (!amdgpu_asic_id_table_paths)
+		return NULL;
+
+	// extract the file name from AMDGPU_ASIC_ID_TABLE
+	file_name = strrchr(AMDGPU_ASIC_ID_TABLE, '/');
+	if (!file_name)
+		return NULL;
+	file_name++; // skip the '/'
+
+	paths = split_env_var(amdgpu_asic_id_table_paths);
+	if (!paths)
+		return NULL;
+
+	// for each path, join with file_name and check if it exists
+	for (int i = 0; paths[i] != NULL; i++) {
+		char *full_path = join_path(paths[i], file_name);
+		if (!full_path) {
+			continue;
+		}
+		if (access(full_path, R_OK) == 0) {
+			found_path = full_path;
+			break;
+		}
+	}
+	split_env_var_free(paths);
+	return found_path;
+}
+#endif
+
 void amdgpu_parse_asic_ids(struct amdgpu_device *dev)
 {
 	FILE *fp;
@@ -113,11 +280,21 @@ void amdgpu_parse_asic_ids(struct amdgpu_device *dev)
 	int line_num = 1;
 	int r = 0;
 
-	fp = fopen(AMDGPU_ASIC_ID_TABLE, "r");
+	char *amdgpu_asic_id_table_path = NULL;
+#if HAVE_SECURE_GETENV
+	// if this system lacks secure_getenv(), don't allow extra paths
+	// for security reasons.
+	amdgpu_asic_id_table_path = find_asic_id_table();
+#endif
+	// if not found, use the default AMDGPU_ASIC_ID_TABLE path
+	if (!amdgpu_asic_id_table_path)
+		amdgpu_asic_id_table_path = strdup(AMDGPU_ASIC_ID_TABLE);
+
+	fp = fopen(amdgpu_asic_id_table_path, "r");
 	if (!fp) {
-		fprintf(stderr, "%s: %s\n", AMDGPU_ASIC_ID_TABLE,
+		fprintf(stderr, "%s: %s\n", amdgpu_asic_id_table_path,
 			strerror(errno));
-		return;
+		goto get_cpu;
 	}
 
 	/* 1st valid line is file version */
@@ -132,7 +309,7 @@ void amdgpu_parse_asic_ids(struct amdgpu_device *dev)
 			continue;
 		}
 
-		drmMsg("%s version: %s\n", AMDGPU_ASIC_ID_TABLE, line);
+		drmMsg("%s version: %s\n", amdgpu_asic_id_table_path, line);
 		break;
 	}
 
@@ -150,7 +327,7 @@ void amdgpu_parse_asic_ids(struct amdgpu_device *dev)
 
 	if (r == -EINVAL) {
 		fprintf(stderr, "Invalid format: %s: line %d: %s\n",
-			AMDGPU_ASIC_ID_TABLE, line_num, line);
+			amdgpu_asic_id_table_path, line_num, line);
 	} else if (r && r != -EAGAIN) {
 		fprintf(stderr, "%s: Cannot parse ASIC IDs: %s\n",
 			__func__, strerror(-r));
@@ -158,4 +335,11 @@ void amdgpu_parse_asic_ids(struct amdgpu_device *dev)
 
 	free(line);
 	fclose(fp);
+
+get_cpu:
+	free(amdgpu_asic_id_table_path);
+	if (dev->info.ids_flags & AMDGPU_IDS_FLAGS_FUSION &&
+	    dev->marketing_name == NULL) {
+		amdgpu_parse_proc_cpuinfo(dev);
+	}
 }

amdgpu/amdgpu_bo.c

@@ -74,6 +74,9 @@ drm_public int amdgpu_bo_alloc(amdgpu_device_handle dev,
 	union drm_amdgpu_gem_create args;
 	int r;
 
+	if (!alloc_buffer || !buf_handle)
+		return -EINVAL;
+
 	memset(&args, 0, sizeof(args));
 	args.in.bo_size = alloc_buffer->alloc_size;
 	args.in.alignment = alloc_buffer->phys_alignment;
@@ -105,6 +108,9 @@ drm_public int amdgpu_bo_set_metadata(amdgpu_bo_handle bo,
 {
 	struct drm_amdgpu_gem_metadata args = {};
 
+	if (!info)
+		return -EINVAL;
+
 	args.handle = bo->handle;
 	args.op = AMDGPU_GEM_METADATA_OP_SET_METADATA;
 	args.data.flags = info->flags;
@@ -132,7 +138,7 @@ drm_public int amdgpu_bo_query_info(amdgpu_bo_handle bo,
 	int r;
 
 	/* Validate the BO passed in */
-	if (!bo->handle)
+	if (!bo->handle || !info)
 		return -EINVAL;
 
 	/* Query metadata. */
@@ -642,7 +648,7 @@ drm_public int amdgpu_bo_list_create(amdgpu_device_handle dev,
 	unsigned i;
 	int r;
 
-	if (!number_of_resources)
+	if (!number_of_resources || !resources)
 		return -EINVAL;
 
 	/* overflow check for multiplication */

data/amdgpu.ids

@@ -39,11 +39,11 @@
 1506,	C3,	AMD Radeon 610M
 1506,	C4,	AMD Radeon 610M
 150E,	C1,	AMD Radeon 890M Graphics
-150E,	C4,	AMD Radeon 890M Graphics
+150E,	C4,	AMD Radeon 880M Graphics
 150E,	C5,	AMD Radeon 890M Graphics
 150E,	C6,	AMD Radeon 890M Graphics
 150E,	D1,	AMD Radeon 890M Graphics
-150E,	D2,	AMD Radeon 890M Graphics
+150E,	D2,	AMD Radeon 880M Graphics
 150E,	D3,	AMD Radeon 890M Graphics
 1586,	C1,	Radeon 8060S Graphics
 1586,	C2,	Radeon 8050S Graphics
@@ -557,6 +557,7 @@
 7448,	00,	AMD Radeon Pro W7900
 7449,	00,	AMD Radeon Pro W7800 48GB
 744A,	00,	AMD Radeon Pro W7900 Dual Slot
+744B,	00,	AMD Radeon Pro W7900D
 744C,	C8,	AMD Radeon RX 7900 XTX
 744C,	CC,	AMD Radeon RX 7900 XT
 744C,	CE,	AMD Radeon RX 7900 GRE
@@ -567,6 +568,7 @@
 7470,	00,	AMD Radeon Pro W7700
 747E,	C8,	AMD Radeon RX 7800 XT
 747E,	D8,	AMD Radeon RX 7800M
+747E,	DB,	AMD Radeon RX 7700
 747E,	FF,	AMD Radeon RX 7700 XT
 7480,	00,	AMD Radeon Pro W7600
 7480,	C0,	AMD Radeon RX 7600 XT
@@ -575,6 +577,7 @@
 7480,	C3,	AMD Radeon RX 7600S
 7480,	C7,	AMD Radeon RX 7600M XT
 7480,	CF,	AMD Radeon RX 7600
+7481,   C7,     AMD Steam Machine
 7483,	CF,	AMD Radeon RX 7600M
 7489,	00,	AMD Radeon Pro W7500
 7499,	00,	AMD Radeon Pro W7400
@@ -584,6 +587,7 @@
 74A1,	00,	AMD Instinct MI300X
 74A2,	00,	AMD Instinct MI308X
 74A5,	00,	AMD Instinct MI325X
+74A8,	00,	AMD Instinct MI308X HF
 74A9,	00,	AMD Instinct MI300X HF
 74B5,	00,	AMD Instinct MI300X VF
 74B6,	00,	AMD Instinct MI308X
@@ -592,6 +596,12 @@
 7550,	C2,	AMD Radeon RX 9070 GRE
 7550,	C3,	AMD Radeon RX 9070
 7551,	C0,	AMD Radeon AI PRO R9700
+7590,	C0,	AMD Radeon RX 9060 XT
+7590,	C7,	AMD Radeon RX 9060
+75A0,	C0,	AMD Instinct MI350X
+75A3,	C0,	AMD Instinct MI355X
+75B0,	C0,	AMD Instinct MI350X VF
+75B3,	C0,	AMD Instinct MI355X VF
 9830,	00,	AMD Radeon HD 8400 / R3 Series
 9831,	00,	AMD Radeon HD 8400E
 9832,	00,	AMD Radeon HD 8330

include/drm/amdgpu_drm.h

@@ -1484,8 +1484,6 @@ struct drm_amdgpu_info_hw_ip {
 	__u32  available_rings;
 	/** version info: bits 23:16 major, 15:8 minor, 7:0 revision */
 	__u32  ip_discovery_version;
-	/* Userq available slots */
-	__u32  userq_num_slots;
 };
 
 /* GFX metadata BO sizes and alignment info (in bytes) */

include/drm/drm.h

@@ -591,34 +591,65 @@ struct drm_set_version {
 	int drm_dd_minor;
 };
 
-/* DRM_IOCTL_GEM_CLOSE ioctl argument type */
+/**
+ * struct drm_gem_close - Argument for &DRM_IOCTL_GEM_CLOSE ioctl.
+ * @handle: Handle of the object to be closed.
+ * @pad: Padding.
+ *
+ * Releases the handle to an mm object.
+ */
 struct drm_gem_close {
-	/** Handle of the object to be closed. */
 	__u32 handle;
 	__u32 pad;
 };
 
-/* DRM_IOCTL_GEM_FLINK ioctl argument type */
+/**
+ * struct drm_gem_flink - Argument for &DRM_IOCTL_GEM_FLINK ioctl.
+ * @handle: Handle for the object being named.
+ * @name: Returned global name.
+ *
+ * Create a global name for an object, returning the name.
+ *
+ * Note that the name does not hold a reference; when the object
+ * is freed, the name goes away.
+ */
 struct drm_gem_flink {
-	/** Handle for the object being named */
 	__u32 handle;
-
-	/** Returned global name */
 	__u32 name;
 };
 
-/* DRM_IOCTL_GEM_OPEN ioctl argument type */
+/**
+ * struct drm_gem_open - Argument for &DRM_IOCTL_GEM_OPEN ioctl.
+ * @name: Name of object being opened.
+ * @handle: Returned handle for the object.
+ * @size: Returned size of the object
+ *
+ * Open an object using the global name, returning a handle and the size.
+ *
+ * This handle (of course) holds a reference to the object, so the object
+ * will not go away until the handle is deleted.
+ */
 struct drm_gem_open {
-	/** Name of object being opened */
 	__u32 name;
-
-	/** Returned handle for the object */
 	__u32 handle;
-
-	/** Returned size of the object */
 	__u64 size;
 };
 
+/**
+ * struct drm_gem_change_handle - Argument for &DRM_IOCTL_GEM_CHANGE_HANDLE ioctl.
+ * @handle: The handle of a gem object.
+ * @new_handle: An available gem handle.
+ *
+ * This ioctl changes the handle of a GEM object to the specified one.
+ * The new handle must be unused. On success the old handle is closed
+ * and all further IOCTL should refer to the new handle only.
+ * Calls to DRM_IOCTL_PRIME_FD_TO_HANDLE will return the new handle.
+ */
+struct drm_gem_change_handle {
+	__u32 handle;
+	__u32 new_handle;
+};
+
 /**
  * DRM_CAP_DUMB_BUFFER
  *
@@ -869,6 +900,21 @@ struct drm_get_cap {
  */
 #define DRM_CLIENT_CAP_CURSOR_PLANE_HOTSPOT	6
 
+/**
+ * DRM_CLIENT_CAP_PLANE_COLOR_PIPELINE
+ *
+ * If set to 1 the DRM core will allow setting the COLOR_PIPELINE
+ * property on a &drm_plane, as well as drm_colorop properties.
+ *
+ * Setting of these plane properties will be rejected when this client
+ * cap is set:
+ * - COLOR_ENCODING
+ * - COLOR_RANGE
+ *
+ * The client must enable &DRM_CLIENT_CAP_ATOMIC first.
+ */
+#define DRM_CLIENT_CAP_PLANE_COLOR_PIPELINE	7
+
 /* DRM_IOCTL_SET_CLIENT_CAP ioctl argument type */
 struct drm_set_client_cap {
 	__u64 capability;
@@ -1303,6 +1349,14 @@ extern "C" {
  */
 #define DRM_IOCTL_SET_CLIENT_NAME	DRM_IOWR(0xD1, struct drm_set_client_name)
 
+/**
+ * DRM_IOCTL_GEM_CHANGE_HANDLE - Move an object to a different handle
+ *
+ * Some applications (notably CRIU) need objects to have specific gem handles.
+ * This ioctl changes the object at one gem handle to use a new gem handle.
+ */
+#define DRM_IOCTL_GEM_CHANGE_HANDLE    DRM_IOWR(0xD2, struct drm_gem_change_handle)
+
 /*
  * Device specific ioctls should only be in their respective headers
  * The device specific ioctl range is from 0x40 to 0x9f.

include/drm/drm_fourcc.h

@@ -210,6 +210,10 @@ extern "C" {
 #define DRM_FORMAT_RGBA1010102	fourcc_code('R', 'A', '3', '0') /* [31:0] R:G:B:A 10:10:10:2 little endian */
 #define DRM_FORMAT_BGRA1010102	fourcc_code('B', 'A', '3', '0') /* [31:0] B:G:R:A 10:10:10:2 little endian */
 
+/* 48 bpp RGB */
+#define DRM_FORMAT_RGB161616 fourcc_code('R', 'G', '4', '8') /* [47:0] R:G:B 16:16:16 little endian */
+#define DRM_FORMAT_BGR161616 fourcc_code('B', 'G', '4', '8') /* [47:0] B:G:R 16:16:16 little endian */
+
 /* 64 bpp RGB */
 #define DRM_FORMAT_XRGB16161616	fourcc_code('X', 'R', '4', '8') /* [63:0] x:R:G:B 16:16:16:16 little endian */
 #define DRM_FORMAT_XBGR16161616	fourcc_code('X', 'B', '4', '8') /* [63:0] x:B:G:R 16:16:16:16 little endian */
@@ -218,7 +222,7 @@ extern "C" {
 #define DRM_FORMAT_ABGR16161616	fourcc_code('A', 'B', '4', '8') /* [63:0] A:B:G:R 16:16:16:16 little endian */
 
 /*
- * Floating point 64bpp RGB
+ * Half-Floating point - 16b/component
  * IEEE 754-2008 binary16 half-precision float
  * [15:0] sign:exponent:mantissa 1:5:10
  */
@@ -228,6 +232,20 @@ extern "C" {
 #define DRM_FORMAT_ARGB16161616F fourcc_code('A', 'R', '4', 'H') /* [63:0] A:R:G:B 16:16:16:16 little endian */
 #define DRM_FORMAT_ABGR16161616F fourcc_code('A', 'B', '4', 'H') /* [63:0] A:B:G:R 16:16:16:16 little endian */
 
+#define DRM_FORMAT_R16F          fourcc_code('R', ' ', ' ', 'H') /* [15:0] R 16 little endian */
+#define DRM_FORMAT_GR1616F       fourcc_code('G', 'R', ' ', 'H') /* [31:0] G:R 16:16 little endian */
+#define DRM_FORMAT_BGR161616F    fourcc_code('B', 'G', 'R', 'H') /* [47:0] B:G:R 16:16:16 little endian */
+
+/*
+ * Floating point - 32b/component
+ * IEEE 754-2008 binary32 float
+ * [31:0] sign:exponent:mantissa 1:8:23
+ */
+#define DRM_FORMAT_R32F          fourcc_code('R', ' ', ' ', 'F') /* [31:0] R 32 little endian */
+#define DRM_FORMAT_GR3232F       fourcc_code('G', 'R', ' ', 'F') /* [63:0] R:G 32:32 little endian */
+#define DRM_FORMAT_BGR323232F    fourcc_code('B', 'G', 'R', 'F') /* [95:0] R:G:B 32:32:32 little endian */
+#define DRM_FORMAT_ABGR32323232F fourcc_code('A', 'B', '8', 'F') /* [127:0] R:G:B:A 32:32:32:32 little endian */
+
 /*
  * RGBA format with 10-bit components packed in 64-bit per pixel, with 6 bits
  * of unused padding per component:
@@ -961,14 +979,20 @@ extern "C" {
  *               2 = Gob Height 8, Turing+ Page Kind mapping
  *               3 = Reserved for future use.
  *
- * 22:22 s     Sector layout.  On Tegra GPUs prior to Xavier, there is a further
- *             bit remapping step that occurs at an even lower level than the
- *             page kind and block linear swizzles.  This causes the layout of
- *             surfaces mapped in those SOC's GPUs to be incompatible with the
- *             equivalent mapping on other GPUs in the same system.
+ * 22:22 s     Sector layout.  There is a further bit remapping step that occurs
+ * 26:27       at an even lower level than the page kind and block linear
+ *             swizzles.  This causes the bit arrangement of surfaces in memory
+ *             to differ subtly, and prevents direct sharing of surfaces between
+ *             GPUs with different layouts.
  *
- *               0 = Tegra K1 - Tegra Parker/TX2 Layout.
- *               1 = Desktop GPU and Tegra Xavier+ Layout
+ *               0 = Tegra K1 - Tegra Parker/TX2 Layout
+ *               1 = Pre-GB20x, GB20x 32+ bpp, GB10, Tegra Xavier-Orin Layout
+ *               2 = GB20x(Blackwell 2)+ 8 bpp surface layout
+ *               3 = GB20x(Blackwell 2)+ 16 bpp surface layout
+ *               4 = Reserved for future use.
+ *               5 = Reserved for future use.
+ *               6 = Reserved for future use.
+ *               7 = Reserved for future use.
  *
  * 25:23 c     Lossless Framebuffer Compression type.
  *
@@ -983,7 +1007,7 @@ extern "C" {
  *               6 = Reserved for future use
  *               7 = Reserved for future use
  *
- * 55:25 -     Reserved for future use.  Must be zero.
+ * 55:28 -     Reserved for future use.  Must be zero.
  */
 #define DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(c, s, g, k, h) \
 	fourcc_mod_code(NVIDIA, (0x10 | \
@@ -991,6 +1015,7 @@ extern "C" {
 				 (((k) & 0xff) << 12) | \
 				 (((g) & 0x3) << 20) | \
 				 (((s) & 0x1) << 22) | \
+				 (((s) & 0x6) << 25) | \
 				 (((c) & 0x7) << 23)))
 
 /* To grandfather in prior block linear format modifiers to the above layout,

include/drm/drm_mode.h

@@ -629,6 +629,7 @@ struct drm_mode_connector_set_property {
 #define DRM_MODE_OBJECT_FB 0xfbfbfbfb
 #define DRM_MODE_OBJECT_BLOB 0xbbbbbbbb
 #define DRM_MODE_OBJECT_PLANE 0xeeeeeeee
+#define DRM_MODE_OBJECT_COLOROP 0xfafafafa
 #define DRM_MODE_OBJECT_ANY 0
 
 struct drm_mode_obj_get_properties {
@@ -846,6 +847,20 @@ struct drm_color_ctm {
 	__u64 matrix[9];
 };
 
+struct drm_color_ctm_3x4 {
+	/*
+	 * Conversion matrix with 3x4 dimensions in S31.32 sign-magnitude
+	 * (not two's complement!) format.
+	 *
+	 * out   matrix          in
+	 * |R|   |0  1  2  3 |   | R |
+	 * |G| = |4  5  6  7 | x | G |
+	 * |B|   |8  9  10 11|   | B |
+	 *                       |1.0|
+	 */
+	__u64 matrix[12];
+};
+
 struct drm_color_lut {
 	/*
 	 * Values are mapped linearly to 0.0 - 1.0 range, with 0x0 == 0.0 and
@@ -857,6 +872,125 @@ struct drm_color_lut {
 	__u16 reserved;
 };
 
+/*
+ * struct drm_color_lut32
+ *
+ * 32-bit per channel color LUT entry, similar to drm_color_lut.
+ */
+struct drm_color_lut32 {
+	__u32 red;
+	__u32 green;
+	__u32 blue;
+	__u32 reserved;
+};
+
+/**
+ * enum drm_colorop_type - Type of color operation
+ *
+ * drm_colorops can be of many different types. Each type behaves differently
+ * and defines a different set of properties. This enum defines all types and
+ * gives a high-level description.
+ */
+enum drm_colorop_type {
+	/**
+	 * @DRM_COLOROP_1D_CURVE:
+	 *
+	 * enum string "1D Curve"
+	 *
+	 * A 1D curve that is being applied to all color channels. The
+	 * curve is specified via the CURVE_1D_TYPE colorop property.
+	 */
+	DRM_COLOROP_1D_CURVE,
+
+	/**
+	 * @DRM_COLOROP_1D_LUT:
+	 *
+	 * enum string "1D LUT"
+	 *
+	 * A simple 1D LUT of uniformly spaced &drm_color_lut32 entries,
+	 * packed into a blob via the DATA property. The driver's
+	 * expected LUT size is advertised via the SIZE property.
+	 *
+	 * The DATA blob is an array of struct drm_color_lut32 with size
+	 * of "size".
+	 */
+	DRM_COLOROP_1D_LUT,
+
+	/**
+	 * @DRM_COLOROP_CTM_3X4:
+	 *
+	 * enum string "3x4 Matrix"
+	 *
+	 * A 3x4 matrix. Its values are specified via the
+	 * &drm_color_ctm_3x4 struct provided via the DATA property.
+	 *
+	 * The DATA blob is a float[12]:
+	 * out   matrix          in
+	 * | R |   | 0  1  2  3  |   | R |
+	 * | G | = | 4  5  6  7  | x | G |
+	 * | B |   | 8  9  10 12 |   | B |
+	 */
+	DRM_COLOROP_CTM_3X4,
+
+	/**
+	 * @DRM_COLOROP_MULTIPLIER:
+	 *
+	 * enum string "Multiplier"
+	 *
+	 * A simple multiplier, applied to all color values. The
+	 * multiplier is specified as a S31.32 via the MULTIPLIER
+	 * property.
+	 */
+	DRM_COLOROP_MULTIPLIER,
+
+	/**
+	 * @DRM_COLOROP_3D_LUT:
+	 *
+	 * enum string "3D LUT"
+	 *
+	 * A 3D LUT of &drm_color_lut32 entries,
+	 * packed into a blob via the DATA property. The driver's expected
+	 * LUT size is advertised via the SIZE property, i.e., a 3D LUT with
+	 * 17x17x17 entries will have SIZE set to 17.
+	 *
+	 * The DATA blob is a 3D array of struct drm_color_lut32 with dimension
+	 * length of "size".
+	 * The LUT elements are traversed like so:
+	 *
+	 *   for B in range 0..n
+	 *     for G in range 0..n
+	 *       for R in range 0..n
+	 *        index = R + n * (G + n * B)
+	 *         color = lut3d[index]
+	 */
+	DRM_COLOROP_3D_LUT,
+};
+
+/**
+ * enum drm_colorop_lut3d_interpolation_type - type of 3DLUT interpolation
+ */
+enum drm_colorop_lut3d_interpolation_type {
+	/**
+	 * @DRM_COLOROP_LUT3D_INTERPOLATION_TETRAHEDRAL:
+	 *
+	 * Tetrahedral 3DLUT interpolation
+	 */
+	DRM_COLOROP_LUT3D_INTERPOLATION_TETRAHEDRAL,
+};
+
+/**
+ * enum drm_colorop_lut1d_interpolation_type - type of interpolation for 1D LUTs
+ */
+enum drm_colorop_lut1d_interpolation_type {
+	/**
+	 * @DRM_COLOROP_LUT1D_INTERPOLATION_LINEAR:
+	 *
+	 * Linear interpolation. Values between points of the LUT will be
+	 * linearly interpolated.
+	 */
+	DRM_COLOROP_LUT1D_INTERPOLATION_LINEAR,
+};
+
 /**
  * struct drm_plane_size_hint - Plane size hints
  * @width: The width of the plane in pixel
@@ -962,6 +1096,14 @@ struct hdr_output_metadata {
  * Request that the kernel sends back a vblank event (see
  * struct drm_event_vblank) with the &DRM_EVENT_FLIP_COMPLETE type when the
  * page-flip is done.
+ *
+ * When used with atomic uAPI, one event will be delivered per CRTC included in
+ * the atomic commit. A CRTC is included in an atomic commit if one of its
+ * properties is set, or if a property is set on a connector or plane linked
+ * via the CRTC_ID property to the CRTC. At least one CRTC must be included,
+ * and all pulled in CRTCs must be either previously or newly powered on (in
+ * other words, a powered off CRTC which stays off cannot be included in the
+ * atomic commit).
  */
 #define DRM_MODE_PAGE_FLIP_EVENT 0x01
 /**
@@ -1058,7 +1200,7 @@ struct drm_mode_crtc_page_flip_target {
  * struct drm_mode_create_dumb - Create a KMS dumb buffer for scanout.
  * @height: buffer height in pixels
  * @width: buffer width in pixels
- * @bpp: bits per pixel
+ * @bpp: color mode
  * @flags: must be zero
  * @handle: buffer object handle
  * @pitch: number of bytes between two consecutive lines
@@ -1066,6 +1208,54 @@ struct drm_mode_crtc_page_flip_target {
  *
  * User-space fills @height, @width, @bpp and @flags. If the IOCTL succeeds,
  * the kernel fills @handle, @pitch and @size.
+ *
+ * The value of @bpp is a color-mode number describing a specific format
+ * or a variant thereof. The value often corresponds to the number of bits
+ * per pixel for most modes, although there are exceptions. Each color mode
+ * maps to a DRM format plus a number of modes with similar pixel layout.
+ * Framebuffer layout is always linear.
+ *
+ * Support for all modes and formats is optional. Even if dumb-buffer
+ * creation with a certain color mode succeeds, it is not guaranteed that
+ * the DRM driver supports any of the related formats. Most drivers support
+ * a color mode of 32 with a format of DRM_FORMAT_XRGB8888 on their primary
+ * plane.
+ *
+ * +------------+------------------------+------------------------+
+ * | Color mode | Framebuffer format     | Compatible formats     |
+ * +============+========================+========================+
+ * |     32     |  * DRM_FORMAT_XRGB8888 |  * DRM_FORMAT_BGRX8888 |
+ * |            |                        |  * DRM_FORMAT_RGBX8888 |
+ * |            |                        |  * DRM_FORMAT_XBGR8888 |
+ * +------------+------------------------+------------------------+
+ * |     24     |  * DRM_FORMAT_RGB888   |  * DRM_FORMAT_BGR888   |
+ * +------------+------------------------+------------------------+
+ * |     16     |  * DRM_FORMAT_RGB565   |  * DRM_FORMAT_BGR565   |
+ * +------------+------------------------+------------------------+
+ * |     15     |  * DRM_FORMAT_XRGB1555 |  * DRM_FORMAT_BGRX1555 |
+ * |            |                        |  * DRM_FORMAT_RGBX1555 |
+ * |            |                        |  * DRM_FORMAT_XBGR1555 |
+ * +------------+------------------------+------------------------+
+ * |      8     |  * DRM_FORMAT_C8       |  * DRM_FORMAT_D8       |
+ * |            |                        |  * DRM_FORMAT_R8       |
+ * +------------+------------------------+------------------------+
+ * |      4     |  * DRM_FORMAT_C4       |  * DRM_FORMAT_D4       |
+ * |            |                        |  * DRM_FORMAT_R4       |
+ * +------------+------------------------+------------------------+
+ * |      2     |  * DRM_FORMAT_C2       |  * DRM_FORMAT_D2       |
+ * |            |                        |  * DRM_FORMAT_R2       |
+ * +------------+------------------------+------------------------+
+ * |      1     |  * DRM_FORMAT_C1       |  * DRM_FORMAT_D1       |
+ * |            |                        |  * DRM_FORMAT_R1       |
+ * +------------+------------------------+------------------------+
+ *
+ * Color modes of 10, 12, 15, 30 and 64 are only supported for use by
+ * legacy user space. Please don't use them in new code. Other modes
+ * are not support.
+ *
+ * Do not attempt to allocate anything but linear framebuffer memory
+ * with single-plane RGB data. Allocation of other framebuffer
+ * layouts requires dedicated ioctls in the respective DRM driver.
  */
 struct drm_mode_create_dumb {
 	__u32 height;

include/drm/virtgpu_drm.h

@@ -46,12 +46,16 @@ extern "C" {
 #define DRM_VIRTGPU_TRANSFER_TO_HOST 0x07
 #define DRM_VIRTGPU_WAIT     0x08
 #define DRM_VIRTGPU_GET_CAPS  0x09
+#define DRM_VIRTGPU_RESOURCE_CREATE_BLOB 0x0a
+#define DRM_VIRTGPU_CONTEXT_INIT 0x0b
 
 #define VIRTGPU_EXECBUF_FENCE_FD_IN	0x01
 #define VIRTGPU_EXECBUF_FENCE_FD_OUT	0x02
+#define VIRTGPU_EXECBUF_RING_IDX	0x04
 #define VIRTGPU_EXECBUF_FLAGS  (\
 		VIRTGPU_EXECBUF_FENCE_FD_IN |\
 		VIRTGPU_EXECBUF_FENCE_FD_OUT |\
+		VIRTGPU_EXECBUF_RING_IDX |\
 		0)
 
 struct drm_virtgpu_map {
@@ -60,6 +64,17 @@ struct drm_virtgpu_map {
 	__u32 pad;
 };
 
+#define VIRTGPU_EXECBUF_SYNCOBJ_RESET		0x01
+#define VIRTGPU_EXECBUF_SYNCOBJ_FLAGS ( \
+		VIRTGPU_EXECBUF_SYNCOBJ_RESET | \
+		0)
+struct drm_virtgpu_execbuffer_syncobj {
+	__u32 handle;
+	__u32 flags;
+	__u64 point;
+};
+
+/* fence_fd is modified on success if VIRTGPU_EXECBUF_FENCE_FD_OUT flag is set. */
 struct drm_virtgpu_execbuffer {
 	__u32 flags;
 	__u32 size;
@@ -67,10 +82,22 @@ struct drm_virtgpu_execbuffer {
 	__u64 bo_handles;
 	__u32 num_bo_handles;
 	__s32 fence_fd; /* in/out fence fd (see VIRTGPU_EXECBUF_FENCE_FD_IN/OUT) */
+	__u32 ring_idx; /* command ring index (see VIRTGPU_EXECBUF_RING_IDX) */
+	__u32 syncobj_stride; /* size of @drm_virtgpu_execbuffer_syncobj */
+	__u32 num_in_syncobjs;
+	__u32 num_out_syncobjs;
+	__u64 in_syncobjs;
+	__u64 out_syncobjs;
 };
 
 #define VIRTGPU_PARAM_3D_FEATURES 1 /* do we have 3D features in the hw */
 #define VIRTGPU_PARAM_CAPSET_QUERY_FIX 2 /* do we have the capset fix */
+#define VIRTGPU_PARAM_RESOURCE_BLOB 3 /* DRM_VIRTGPU_RESOURCE_CREATE_BLOB */
+#define VIRTGPU_PARAM_HOST_VISIBLE 4 /* Host blob resources are mappable */
+#define VIRTGPU_PARAM_CROSS_DEVICE 5 /* Cross virtio-device resource sharing  */
+#define VIRTGPU_PARAM_CONTEXT_INIT 6 /* DRM_VIRTGPU_CONTEXT_INIT */
+#define VIRTGPU_PARAM_SUPPORTED_CAPSET_IDs 7 /* Bitmask of supported capability set ids */
+#define VIRTGPU_PARAM_EXPLICIT_DEBUG_NAME 8 /* Ability to set debug name from userspace */
 
 struct drm_virtgpu_getparam {
 	__u64 param;
@@ -100,7 +127,7 @@ struct drm_virtgpu_resource_info {
 	__u32 bo_handle;
 	__u32 res_handle;
 	__u32 size;
-	__u32 stride;
+	__u32 blob_mem;
 };
 
 struct drm_virtgpu_3d_box {
@@ -117,6 +144,8 @@ struct drm_virtgpu_3d_transfer_to_host {
 	struct drm_virtgpu_3d_box box;
 	__u32 level;
 	__u32 offset;
+	__u32 stride;
+	__u32 layer_stride;
 };
 
 struct drm_virtgpu_3d_transfer_from_host {
@@ -124,6 +153,8 @@ struct drm_virtgpu_3d_transfer_from_host {
 	struct drm_virtgpu_3d_box box;
 	__u32 level;
 	__u32 offset;
+	__u32 stride;
+	__u32 layer_stride;
 };
 
 #define VIRTGPU_WAIT_NOWAIT 1 /* like it */
@@ -132,6 +163,12 @@ struct drm_virtgpu_3d_wait {
 	__u32 flags;
 };
 
+#define VIRTGPU_DRM_CAPSET_VIRGL 1
+#define VIRTGPU_DRM_CAPSET_VIRGL2 2
+#define VIRTGPU_DRM_CAPSET_GFXSTREAM_VULKAN 3
+#define VIRTGPU_DRM_CAPSET_VENUS 4
+#define VIRTGPU_DRM_CAPSET_CROSS_DOMAIN 5
+#define VIRTGPU_DRM_CAPSET_DRM 6
 struct drm_virtgpu_get_caps {
 	__u32 cap_set_id;
 	__u32 cap_set_ver;
@@ -140,6 +177,55 @@ struct drm_virtgpu_get_caps {
 	__u32 pad;
 };
 
+struct drm_virtgpu_resource_create_blob {
+#define VIRTGPU_BLOB_MEM_GUEST             0x0001
+#define VIRTGPU_BLOB_MEM_HOST3D            0x0002
+#define VIRTGPU_BLOB_MEM_HOST3D_GUEST      0x0003
+
+#define VIRTGPU_BLOB_FLAG_USE_MAPPABLE     0x0001
+#define VIRTGPU_BLOB_FLAG_USE_SHAREABLE    0x0002
+#define VIRTGPU_BLOB_FLAG_USE_CROSS_DEVICE 0x0004
+	/* zero is invalid blob_mem */
+	__u32 blob_mem;
+	__u32 blob_flags;
+	__u32 bo_handle;
+	__u32 res_handle;
+	__u64 size;
+
+	/*
+	 * for 3D contexts with VIRTGPU_BLOB_MEM_HOST3D_GUEST and
+	 * VIRTGPU_BLOB_MEM_HOST3D otherwise, must be zero.
+	 */
+	__u32 pad;
+	__u32 cmd_size;
+	__u64 cmd;
+	__u64 blob_id;
+};
+
+#define VIRTGPU_CONTEXT_PARAM_CAPSET_ID       0x0001
+#define VIRTGPU_CONTEXT_PARAM_NUM_RINGS       0x0002
+#define VIRTGPU_CONTEXT_PARAM_POLL_RINGS_MASK 0x0003
+#define VIRTGPU_CONTEXT_PARAM_DEBUG_NAME      0x0004
+struct drm_virtgpu_context_set_param {
+	__u64 param;
+	__u64 value;
+};
+
+struct drm_virtgpu_context_init {
+	__u32 num_params;
+	__u32 pad;
+
+	/* pointer to drm_virtgpu_context_set_param array */
+	__u64 ctx_set_params;
+};
+
+/*
+ * Event code that's given when VIRTGPU_CONTEXT_PARAM_POLL_RINGS_MASK is in
+ * effect.  The event size is sizeof(drm_event), since there is no additional
+ * payload.
+ */
+#define VIRTGPU_EVENT_FENCE_SIGNALED 0x90000000
+
 #define DRM_IOCTL_VIRTGPU_MAP \
 	DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_MAP, struct drm_virtgpu_map)
 
@@ -175,6 +261,14 @@ struct drm_virtgpu_get_caps {
 	DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_GET_CAPS, \
 	struct drm_virtgpu_get_caps)
 
+#define DRM_IOCTL_VIRTGPU_RESOURCE_CREATE_BLOB				\
+	DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_RESOURCE_CREATE_BLOB,	\
+		struct drm_virtgpu_resource_create_blob)
+
+#define DRM_IOCTL_VIRTGPU_CONTEXT_INIT					\
+	DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_CONTEXT_INIT,		\
+		struct drm_virtgpu_context_init)
+
 #if defined(__cplusplus)
 }
 #endif

meson.build

@@ -26,7 +26,7 @@
 project(
   'libdrm',
   ['c'],
-  version : '2.4.127',
+  version : '2.4.131',
   license : 'MIT',
   meson_version : '>= 0.59',
   default_options : ['buildtype=debugoptimized', 'c_std=c11'],
@@ -51,6 +51,8 @@ dep_threads = dependency('threads')
 
 cc = meson.get_compiler('c')
 
+config.set10('HAVE_SECURE_GETENV', cc.has_function('secure_getenv'))
+
 android = cc.compiles('''int func() { return __ANDROID__; }''')
 
 # Solaris / Illumos
@@ -205,7 +207,6 @@ libdrm_c_args = cc.get_supported_arguments([
   '-Wno-unused-parameter', '-Wno-attributes', '-Wno-long-long',
   '-Wno-missing-field-initializers'])
 
-dep_cunit = dependency('cunit', version : '>= 2.1', required : false)
 dep_cairo = dependency('cairo', required : get_option('cairo-tests'))
 with_cairo_tests = dep_cairo.found()
 

omap/omap_drm.c

@@ -41,10 +41,6 @@
 #include "omap_drm.h"
 #include "omap_drmif.h"
 
-#define __round_mask(x, y) ((__typeof__(x))((y)-1))
-#define round_up(x, y) ((((x)-1) | __round_mask(x, y))+1)
-#define PAGE_SIZE 4096
-
 static pthread_mutex_t table_lock = PTHREAD_MUTEX_INITIALIZER;
 static void * dev_table;
 
@@ -207,12 +203,6 @@ static struct omap_bo * omap_bo_new_impl(struct omap_device *dev,
 	bo = bo_from_handle(dev, req.handle);
 	pthread_mutex_unlock(&table_lock);
 
-	if (flags & OMAP_BO_TILED) {
-		bo->size = round_up(size.tiled.width, PAGE_SIZE) * size.tiled.height;
-	} else {
-		bo->size = size.bytes;
-	}
-
 	return bo;
 
 fail:
@@ -432,7 +422,7 @@ drm_public uint32_t omap_bo_size(struct omap_bo *bo)
 drm_public void *omap_bo_map(struct omap_bo *bo)
 {
 	if (!bo->map) {
-		if (!bo->offset) {
+		if (!bo->size || !bo->offset) {
 			get_buffer_info(bo);
 		}
 

tests/amdgpu/amdgpu_test.c

@@ -1,949 +0,0 @@
-/*
- * Copyright 2014 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
-*/
-
-#include <string.h>
-#include <stdio.h>
-#include <stdlib.h>
-#include <unistd.h>
-#include <string.h>
-#include <ctype.h>
-#include <fcntl.h>
-#include <errno.h>
-#include <signal.h>
-#include <time.h>
-#include <sys/types.h>
-#include <sys/stat.h>
-#include <sys/ioctl.h>
-#include <sys/time.h>
-#include <stdarg.h>
-#include <stdint.h>
-#ifdef __linux__
-#include <linux/limits.h>
-#elif __FreeBSD__
-/* SPECNAMELEN in FreeBSD is defined here: */
-#include <sys/param.h>
-#endif
-#ifdef MAJOR_IN_MKDEV
-#include <sys/mkdev.h>
-#endif
-#ifdef MAJOR_IN_SYSMACROS
-#include <sys/sysmacros.h>
-#endif
-
-#include "drm.h"
-#include "xf86drmMode.h"
-#include "xf86drm.h"
-
-#include "CUnit/Basic.h"
-
-#include "amdgpu_test.h"
-#include "amdgpu_internal.h"
-
-/* Test suite names */
-#define BASIC_TESTS_STR "Basic Tests"
-#define BO_TESTS_STR "BO Tests"
-#define CS_TESTS_STR "CS Tests"
-#define VCE_TESTS_STR "VCE Tests"
-#define VCN_TESTS_STR "VCN Tests"
-#define JPEG_TESTS_STR "JPEG Tests"
-#define UVD_ENC_TESTS_STR "UVD ENC Tests"
-#define DEADLOCK_TESTS_STR "Deadlock Tests"
-#define VM_TESTS_STR "VM Tests"
-#define RAS_TESTS_STR "RAS Tests"
-#define SYNCOBJ_TIMELINE_TESTS_STR "SYNCOBJ TIMELINE Tests"
-#define SECURITY_TESTS_STR "Security Tests"
-#define HOTUNPLUG_TESTS_STR "Hotunplug Tests"
-#define CP_DMA_TESTS_STR "CP DMA Tests"
-
-/**
- *  Open handles for amdgpu devices
- *
- */
-int drm_amdgpu[MAX_CARDS_SUPPORTED];
-
-/** Open render node to test */
-int open_render_node = 0;	/* By default run most tests on primary node */
-
-/** The table of all known test suites to run */
-static CU_SuiteInfo suites[] = {
-	{
-		.pName = BASIC_TESTS_STR,
-		.pInitFunc = suite_basic_tests_init,
-		.pCleanupFunc = suite_basic_tests_clean,
-		.pTests = basic_tests,
-	},
-	{
-		.pName = BO_TESTS_STR,
-		.pInitFunc = suite_bo_tests_init,
-		.pCleanupFunc = suite_bo_tests_clean,
-		.pTests = bo_tests,
-	},
-	{
-		.pName = CS_TESTS_STR,
-		.pInitFunc = suite_cs_tests_init,
-		.pCleanupFunc = suite_cs_tests_clean,
-		.pTests = cs_tests,
-	},
-	{
-		.pName = VCE_TESTS_STR,
-		.pInitFunc = suite_vce_tests_init,
-		.pCleanupFunc = suite_vce_tests_clean,
-		.pTests = vce_tests,
-	},
-	{
-		.pName = VCN_TESTS_STR,
-		.pInitFunc = suite_vcn_tests_init,
-		.pCleanupFunc = suite_vcn_tests_clean,
-		.pTests = vcn_tests,
-	},
-	{
-		.pName = JPEG_TESTS_STR,
-		.pInitFunc = suite_jpeg_tests_init,
-		.pCleanupFunc = suite_jpeg_tests_clean,
-		.pTests = jpeg_tests,
-	},
-	{
-		.pName = UVD_ENC_TESTS_STR,
-		.pInitFunc = suite_uvd_enc_tests_init,
-		.pCleanupFunc = suite_uvd_enc_tests_clean,
-		.pTests = uvd_enc_tests,
-	},
-	{
-		.pName = DEADLOCK_TESTS_STR,
-		.pInitFunc = suite_deadlock_tests_init,
-		.pCleanupFunc = suite_deadlock_tests_clean,
-		.pTests = deadlock_tests,
-	},
-	{
-		.pName = VM_TESTS_STR,
-		.pInitFunc = suite_vm_tests_init,
-		.pCleanupFunc = suite_vm_tests_clean,
-		.pTests = vm_tests,
-	},
-	{
-		.pName = RAS_TESTS_STR,
-		.pInitFunc = suite_ras_tests_init,
-		.pCleanupFunc = suite_ras_tests_clean,
-		.pTests = ras_tests,
-	},
-	{
-		.pName = SYNCOBJ_TIMELINE_TESTS_STR,
-		.pInitFunc = suite_syncobj_timeline_tests_init,
-		.pCleanupFunc = suite_syncobj_timeline_tests_clean,
-		.pTests = syncobj_timeline_tests,
-	},
-	{
-		.pName = SECURITY_TESTS_STR,
-		.pInitFunc = suite_security_tests_init,
-		.pCleanupFunc = suite_security_tests_clean,
-		.pTests = security_tests,
-	},
-	{
-		.pName = HOTUNPLUG_TESTS_STR,
-		.pInitFunc = suite_hotunplug_tests_init,
-		.pCleanupFunc = suite_hotunplug_tests_clean,
-		.pTests = hotunplug_tests,
-	},
-	{
-		.pName = CP_DMA_TESTS_STR,
-		.pInitFunc = suite_cp_dma_tests_init,
-		.pCleanupFunc = suite_cp_dma_tests_clean,
-		.pTests = cp_dma_tests,
-	},
-
-	CU_SUITE_INFO_NULL,
-};
-
-typedef CU_BOOL (*active__stat_func)(void);
-
-typedef struct Suites_Active_Status {
-	char*             pName;
-	active__stat_func pActive;
-}Suites_Active_Status;
-
-static CU_BOOL always_active()
-{
-	return CU_TRUE;
-}
-
-static Suites_Active_Status suites_active_stat[] = {
-		{
-			.pName = BASIC_TESTS_STR,
-			.pActive = suite_basic_tests_enable,
-		},
-		{
-			.pName = BO_TESTS_STR,
-			.pActive = always_active,
-		},
-		{
-			.pName = CS_TESTS_STR,
-			.pActive = suite_cs_tests_enable,
-		},
-		{
-			.pName = VCE_TESTS_STR,
-			.pActive = suite_vce_tests_enable,
-		},
-		{
-			.pName = VCN_TESTS_STR,
-			.pActive = suite_vcn_tests_enable,
-		},
-		{
-			.pName = JPEG_TESTS_STR,
-			.pActive = suite_jpeg_tests_enable,
-		},
-		{
-			.pName = UVD_ENC_TESTS_STR,
-			.pActive = suite_uvd_enc_tests_enable,
-		},
-		{
-			.pName = DEADLOCK_TESTS_STR,
-			.pActive = suite_deadlock_tests_enable,
-		},
-		{
-			.pName = VM_TESTS_STR,
-			.pActive = suite_vm_tests_enable,
-		},
-		{
-			.pName = RAS_TESTS_STR,
-			.pActive = suite_ras_tests_enable,
-		},
-		{
-			.pName = SYNCOBJ_TIMELINE_TESTS_STR,
-			.pActive = suite_syncobj_timeline_tests_enable,
-		},
-		{
-			.pName = SECURITY_TESTS_STR,
-			.pActive = suite_security_tests_enable,
-		},
-		{
-			.pName = HOTUNPLUG_TESTS_STR,
-			.pActive = suite_hotunplug_tests_enable,
-		},
-		{
-			.pName = CP_DMA_TESTS_STR,
-			.pActive = suite_cp_dma_tests_enable,
-		},
-};
-
-
-/*
- * Display information about all  suites and their tests
- *
- * NOTE: Must be run after registry is initialized and suites registered.
- */
-static void display_test_suites(void)
-{
-	int iSuite;
-	int iTest;
-	CU_pSuite pSuite = NULL;
-	CU_pTest  pTest  = NULL;
-
-	printf("%5s: %2s: %8s: %s\n", "What", "ID", "Status", "Name");
-
-	for (iSuite = 0; suites[iSuite].pName != NULL; iSuite++) {
-
-		pSuite = CU_get_suite_by_index((unsigned int) iSuite + 1,
-					       CU_get_registry());
-
-		if (!pSuite) {
-			fprintf(stderr, "Invalid suite id : %d\n", iSuite + 1);
-			continue;
-		}
-
-		printf("Suite: %2d: %8s: %s\n",
-		       iSuite + 1,
-		       pSuite->fActive ? "ENABLED" : "DISABLED",
-		       suites[iSuite].pName);
-
-		if (!pSuite->fActive)
-			continue;
-
-		for (iTest = 0; suites[iSuite].pTests[iTest].pName != NULL;
-		     iTest++) {
-			pTest = CU_get_test_by_index((unsigned int) iTest + 1,
-						     pSuite);
-			if (!pTest) {
-				fprintf(stderr, "Invalid test id : %d\n", iTest + 1);
-				continue;
-			}
-			printf(" Test: %2d: %8s: %s\n",
-			       iTest + 1,
-			       pSuite->fActive && pTest->fActive ? "ENABLED" : "DISABLED",
-			       suites[iSuite].pTests[iTest].pName);
-		}
-	}
-}
-
-/** Help string for command line parameters */
-static const char usage[] =
-	"Usage: %s [-hlpr] [-s <suite id>] [-e <s>[.<t>] [-e ...]] [-t <test id>] [-f] "
-	"[-b <pci_bus_id>] [-d <pci_device_id>]\n"
-	"Where,\n"
-	"  -b      Specify device's PCI bus id to run tests\n"
-	"  -d      Specify device's PCI device id to run tests (optional)\n"
-	"  -e <s>[.<t>]  Disable test <t> of suite <s>. If only <s> is given, then disable\n"
-	"          the whole suite. Can be specified more than once on the command line\n"
-	"          to disable multiple tests or suites.\n"
-	"  -f      Force executing inactive suite or test\n"
-	"  -h      Display this help\n"
-	"  -l      Display all test suites and their tests\n"
-	"  -p      Display information of AMDGPU devices in system\n"
-	"  -r      Run the tests on render node\n"
-	"  -s <s>  Enable only test suite <s>\n"
-	"  -t <t>  Enable only test <t> of test suite <s>\n";
-/** Specified options strings for getopt */
-static const char options[]   = "hlrps:t:e:b:d:f";
-
-/* Open AMD devices.
- * Return the number of AMD device opened.
- */
-static int amdgpu_open_devices(int open_render_node)
-{
-	drmDevicePtr devices[MAX_CARDS_SUPPORTED];
-	int i;
-	int drm_node;
-	int amd_index = 0;
-	int drm_count;
-	int fd;
-	drmVersionPtr version;
-
-	for (i = 0; i < MAX_CARDS_SUPPORTED; i++) {
-		drm_amdgpu[i] = -1;
-	}
-
-	drm_count = drmGetDevices2(0, devices, MAX_CARDS_SUPPORTED);
-
-	if (drm_count < 0) {
-		fprintf(stderr,
-			"drmGetDevices2() returned an error %d\n",
-			drm_count);
-		return 0;
-	}
-
-	for (i = 0; i < drm_count; i++) {
-		/* If this is not PCI device, skip*/
-		if (devices[i]->bustype != DRM_BUS_PCI)
-			continue;
-
-		/* If this is not AMD GPU vender ID, skip*/
-		if (devices[i]->deviceinfo.pci->vendor_id != 0x1002)
-			continue;
-
-		if (open_render_node)
-			drm_node = DRM_NODE_RENDER;
-		else
-			drm_node = DRM_NODE_PRIMARY;
-
-		fd = -1;
-		if (devices[i]->available_nodes & 1 << drm_node)
-			fd = open(
-				devices[i]->nodes[drm_node],
-				O_RDWR | O_CLOEXEC);
-
-		/* This node is not available. */
-		if (fd < 0) continue;
-
-		version = drmGetVersion(fd);
-		if (!version) {
-			fprintf(stderr,
-				"Warning: Cannot get version for %s."
-				"Error is %s\n",
-				devices[i]->nodes[drm_node],
-				strerror(errno));
-			close(fd);
-			continue;
-		}
-
-		if (strcmp(version->name, "amdgpu")) {
-			/* This is not AMDGPU driver, skip.*/
-			drmFreeVersion(version);
-			close(fd);
-			continue;
-		}
-
-		drmFreeVersion(version);
-
-		drm_amdgpu[amd_index] = fd;
-		amd_index++;
-	}
-
-	drmFreeDevices(devices, drm_count);
-	return amd_index;
-}
-
-/* Close AMD devices.
- */
-void amdgpu_close_devices()
-{
-	int i;
-	for (i = 0; i < MAX_CARDS_SUPPORTED; i++)
-		if (drm_amdgpu[i] >=0) {
-			close(drm_amdgpu[i]);
-		}
-}
-
-/* Print AMD devices information */
-static void amdgpu_print_devices()
-{
-	int i;
-	drmDevicePtr device;
-
-	/* Open the first AMD device to print driver information. */
-	if (drm_amdgpu[0] >=0) {
-		/* Display AMD driver version information.*/
-		drmVersionPtr retval = drmGetVersion(drm_amdgpu[0]);
-
-		if (retval == NULL) {
-			perror("Cannot get version for AMDGPU device");
-			return;
-		}
-
-		printf("Driver name: %s, Date: %s, Description: %s.\n",
-			retval->name, retval->date, retval->desc);
-		drmFreeVersion(retval);
-	}
-
-	/* Display information of AMD devices */
-	printf("Devices:\n");
-	for (i = 0; i < MAX_CARDS_SUPPORTED && drm_amdgpu[i] >=0; i++)
-		if (drmGetDevice2(drm_amdgpu[i],
-			DRM_DEVICE_GET_PCI_REVISION,
-			&device) == 0) {
-			if (device->bustype == DRM_BUS_PCI) {
-				printf("PCI ");
-				printf(" domain:%04x",
-					device->businfo.pci->domain);
-				printf(" bus:%02x",
-					device->businfo.pci->bus);
-				printf(" device:%02x",
-					device->businfo.pci->dev);
-				printf(" function:%01x",
-					device->businfo.pci->func);
-				printf(" vendor_id:%04x",
-					device->deviceinfo.pci->vendor_id);
-				printf(" device_id:%04x",
-					device->deviceinfo.pci->device_id);
-				printf(" subvendor_id:%04x",
-					device->deviceinfo.pci->subvendor_id);
-				printf(" subdevice_id:%04x",
-					device->deviceinfo.pci->subdevice_id);
-				printf(" revision_id:%02x",
-					device->deviceinfo.pci->revision_id);
-				printf("\n");
-			}
-			drmFreeDevice(&device);
-		}
-}
-
-/* Find a match AMD device in PCI bus
- * Return the index of the device or -1 if not found
- */
-static int amdgpu_find_device(uint8_t bus, uint16_t dev)
-{
-	int i;
-	drmDevicePtr device;
-
-	for (i = 0; i < MAX_CARDS_SUPPORTED && drm_amdgpu[i] >= 0; i++) {
-		if (drmGetDevice2(drm_amdgpu[i],
-			DRM_DEVICE_GET_PCI_REVISION,
-			&device) == 0) {
-			if (device->bustype == DRM_BUS_PCI)
-				if ((bus == 0xFF || device->businfo.pci->bus == bus) &&
-					device->deviceinfo.pci->device_id == dev) {
-					drmFreeDevice(&device);
-					return i;
-				}
-
-			drmFreeDevice(&device);
-		}
-	}
-
-	return -1;
-}
-
-static void amdgpu_disable_suites()
-{
-	amdgpu_device_handle device_handle;
-	uint32_t major_version, minor_version, family_id;
-	drmDevicePtr devices[MAX_CARDS_SUPPORTED];
-	int i, drm_count;
-	int size = sizeof(suites_active_stat) / sizeof(suites_active_stat[0]);
-
-	if (amdgpu_device_initialize(drm_amdgpu[0], &major_version,
-				   &minor_version, &device_handle))
-		return;
-
-	family_id = device_handle->info.family_id;
-
-	if (amdgpu_device_deinitialize(device_handle))
-		return;
-
-	drm_count = drmGetDevices2(0, devices, MAX_CARDS_SUPPORTED);
-
-	/* Set active status for suites based on their policies */
-	for (i = 0; i < size; ++i)
-		if (amdgpu_set_suite_active(suites_active_stat[i].pName,
-				suites_active_stat[i].pActive()))
-			fprintf(stderr, "suite deactivation failed - %s\n", CU_get_error_msg());
-
-	/* Explicitly disable specific tests due to known bugs or preferences */
-	/*
-	* BUG: Compute ring stalls and never recovers when the address is
-	* written after the command already submitted
-	*/
-	if (amdgpu_set_test_active(DEADLOCK_TESTS_STR,
-			"compute ring block test (set amdgpu.lockup_timeout=50)", CU_FALSE))
-		fprintf(stderr, "test deactivation failed - %s\n", CU_get_error_msg());
-
-	if (amdgpu_set_test_active(DEADLOCK_TESTS_STR,
-				"sdma ring block test (set amdgpu.lockup_timeout=50)", CU_FALSE))
-		fprintf(stderr, "test deactivation failed - %s\n", CU_get_error_msg());
-
-	/* This test was ran on GFX9 only */
-	//if (family_id < AMDGPU_FAMILY_AI || family_id > AMDGPU_FAMILY_RV)
-		if (amdgpu_set_test_active(DEADLOCK_TESTS_STR,
-				"gfx ring bad dispatch test (set amdgpu.lockup_timeout=50)", CU_FALSE))
-			fprintf(stderr, "test deactivation failed - %s\n", CU_get_error_msg());
-
-	/* This test was ran on GFX9 only */
-	//if (family_id < AMDGPU_FAMILY_AI || family_id > AMDGPU_FAMILY_RV)
-		if (amdgpu_set_test_active(DEADLOCK_TESTS_STR,
-				"compute ring bad dispatch test (set amdgpu.lockup_timeout=50,50)", CU_FALSE))
-			fprintf(stderr, "test deactivation failed - %s\n", CU_get_error_msg());
-
-	/* This test was ran on GFX9 only */
-	//if (family_id < AMDGPU_FAMILY_AI || family_id > AMDGPU_FAMILY_RV)
-		if (amdgpu_set_test_active(DEADLOCK_TESTS_STR,
-				"gfx ring bad slow dispatch test (set amdgpu.lockup_timeout=50)", CU_FALSE))
-			fprintf(stderr, "test deactivation failed - %s\n", CU_get_error_msg());
-
-	/* This test was ran on GFX9 only */
-	//if (family_id < AMDGPU_FAMILY_AI || family_id > AMDGPU_FAMILY_RV)
-		if (amdgpu_set_test_active(DEADLOCK_TESTS_STR,
-				"compute ring bad slow dispatch test (set amdgpu.lockup_timeout=50,50)", CU_FALSE))
-			fprintf(stderr, "test deactivation failed - %s\n", CU_get_error_msg());
-
-	//if (family_id < AMDGPU_FAMILY_AI || family_id > AMDGPU_FAMILY_RV)
-		if (amdgpu_set_test_active(DEADLOCK_TESTS_STR,
-				"gfx ring bad draw test (set amdgpu.lockup_timeout=50)", CU_FALSE))
-			fprintf(stderr, "test deactivation failed - %s\n", CU_get_error_msg());
-
-	/* This test was ran on GFX9 only */
-	//if (family_id < AMDGPU_FAMILY_AI || family_id > AMDGPU_FAMILY_RV)
-		if (amdgpu_set_test_active(DEADLOCK_TESTS_STR,
-				"gfx ring slow bad draw test (set amdgpu.lockup_timeout=50)", CU_FALSE))
-			fprintf(stderr, "test deactivation failed - %s\n", CU_get_error_msg());
-
-	if (amdgpu_set_test_active(DEADLOCK_TESTS_STR,
-			"sdma ring corrupted header test (set amdgpu.lockup_timeout=50)", CU_FALSE))
-		fprintf(stderr, "test deactivation failed - %s\n", CU_get_error_msg());
-
-	if (amdgpu_set_test_active(DEADLOCK_TESTS_STR,
-			"sdma ring slow linear copy test (set amdgpu.lockup_timeout=50)", CU_FALSE))
-		fprintf(stderr, "test deactivation failed - %s\n", CU_get_error_msg());
-
-	if (amdgpu_set_test_active(BASIC_TESTS_STR, "bo eviction Test", CU_FALSE))
-		fprintf(stderr, "test deactivation failed - %s\n", CU_get_error_msg());
-
-	/* This test was ran on GFX8 and GFX9 only */
-	if (family_id < AMDGPU_FAMILY_VI || family_id > AMDGPU_FAMILY_RV)
-		if (amdgpu_set_test_active(BASIC_TESTS_STR, "Sync dependency Test", CU_FALSE))
-			fprintf(stderr, "test deactivation failed - %s\n", CU_get_error_msg());
-
-	/* This test was ran on GFX9 only */
-	if (family_id < AMDGPU_FAMILY_AI || family_id > AMDGPU_FAMILY_RV) {
-		if (amdgpu_set_test_active(BASIC_TESTS_STR, "Dispatch Test (GFX)", CU_FALSE))
-			fprintf(stderr, "test deactivation failed - %s\n", CU_get_error_msg());
-		if (amdgpu_set_test_active(BASIC_TESTS_STR, "Dispatch Test (Compute)", CU_FALSE))
-			fprintf(stderr, "test deactivation failed - %s\n", CU_get_error_msg());
-	}
-
-	/* This test was ran on GFX9 only */
-	if (family_id < AMDGPU_FAMILY_AI || family_id > AMDGPU_FAMILY_RV)
-		if (amdgpu_set_test_active(BASIC_TESTS_STR, "Draw Test", CU_FALSE))
-			fprintf(stderr, "test deactivation failed - %s\n", CU_get_error_msg());
-
-	/* This test was ran on GFX9 only */
-	//if (family_id < AMDGPU_FAMILY_AI || family_id > AMDGPU_FAMILY_RV)
-		if (amdgpu_set_test_active(BASIC_TESTS_STR, "GPU reset Test", CU_FALSE))
-			fprintf(stderr, "test deactivation failed - %s\n", CU_get_error_msg());
-
-	/* You need at least 2 devices for this	*/
-	if (drm_count < 2)
-		if (amdgpu_set_test_active(HOTUNPLUG_TESTS_STR, "Unplug with exported fence", CU_FALSE))
-			fprintf(stderr, "test deactivation failed - %s\n", CU_get_error_msg());
-}
-
-int test_device_index;
-
-int amdgpu_open_device_on_test_index(int render_node)
-{
-	int i;
-
-	if (amdgpu_open_devices(open_render_node) <= 0) {
-		perror("Cannot open AMDGPU device");
-		return -1;
-	}
-
-	if (test_device_index >= 0) {
-		/* Most tests run on device of drm_amdgpu[0].
-		 * Swap the chosen device to drm_amdgpu[0].
-		 */
-		i = drm_amdgpu[0];
-		drm_amdgpu[0] = drm_amdgpu[test_device_index];
-		drm_amdgpu[test_device_index] = i;
-	}
-
-	return 0;
-
-
-}
-
-
-static bool amdgpu_node_is_drm(int maj, int min)
-{
-#ifdef __linux__
-    char path[64];
-    struct stat sbuf;
-
-    snprintf(path, sizeof(path), "/sys/dev/char/%d:%d/device/drm",
-             maj, min);
-    return stat(path, &sbuf) == 0;
-#elif defined(__FreeBSD__)
-    char name[SPECNAMELEN];
-
-    if (!devname_r(makedev(maj, min), S_IFCHR, name, sizeof(name)))
-      return 0;
-    /* Handle drm/ and dri/ as both are present in different FreeBSD version
-     * FreeBSD on amd64/i386/powerpc external kernel modules create node in
-     * in /dev/drm/ and links in /dev/dri while a WIP in kernel driver creates
-     * only device nodes in /dev/dri/ */
-    return (!strncmp(name, "drm/", 4) || !strncmp(name, "dri/", 4));
-#else
-    return maj == DRM_MAJOR;
-#endif
-}
-
-char *amdgpu_get_device_from_fd(int fd)
-{
-#ifdef __linux__
-    struct stat sbuf;
-    char path[PATH_MAX + 1];
-    unsigned int maj, min;
-
-    if (fstat(fd, &sbuf))
-        return NULL;
-
-    maj = major(sbuf.st_rdev);
-    min = minor(sbuf.st_rdev);
-
-    if (!amdgpu_node_is_drm(maj, min) || !S_ISCHR(sbuf.st_mode))
-        return NULL;
-
-    snprintf(path, sizeof(path), "/sys/dev/char/%d:%d/device", maj, min);
-    return strdup(path);
-#else
-    return NULL;
-#endif
-}
-
-#ifndef ARRAY_SIZE
-#define ARRAY_SIZE(_A) (sizeof(_A)/sizeof(_A[0]))
-#endif
-
-static void amdgpu_test_disable(long suite, long test)
-{
-	const char *suite_name;
-
-	if (suite < 1)
-		return;
-
-	/* The array is 0-based, so subract 1. */
-	suite--;
-	if (suite >= ARRAY_SIZE(suites) - 1)
-		return;
-
-	suite_name = suites[suite].pName;
-	if (test < 1) {
-		fprintf(stderr, "Deactivating suite %s\n", suite_name);
-		amdgpu_set_suite_active(suite_name, CU_FALSE);
-	} else {
-		int ii;
-
-		/* The array is 0-based so subtract 1. */
-		test--;
-		for (ii = 0; suites[suite].pTests[ii].pName; ii++) {
-			if (ii == test) {
-				fprintf(stderr, "Deactivating %s:%s\n",
-					suite_name,
-					suites[suite].pTests[ii].pName);
-				amdgpu_set_test_active(suite_name,
-						       suites[suite].pTests[ii].pName,
-						       CU_FALSE);
-				break;
-			}
-		}
-
-		if (suites[suite].pTests[ii].pName == NULL)
-			fprintf(stderr, "No such suite.test %ld.%ld\n", suite, test);
-	}
-}
-
-/* The main() function for setting up and running the tests.
- * Returns a CUE_SUCCESS on successful running, another
- * CUnit error code on failure.
- */
-int main(int argc, char **argv)
-{
-	int c;			/* Character received from getopt */
-	int i = 0;
-	int suite_id = -1;	/* By default run everything */
-	int test_id  = -1;	/* By default run all tests in the suite */
-	int pci_bus_id = -1;    /* By default PC bus ID is not specified */
-	int pci_device_id = 0;  /* By default PC device ID is zero */
-	int display_devices = 0;/* By default not to display devices' info */
-	CU_pSuite pSuite = NULL;
-	CU_pTest  pTest  = NULL;
-	int display_list = 0;
-	int force_run = 0;
-
-	/* Parse command line string.
-	 * Process various command line options as early as possible.
-	 */
-	opterr = 0;		/* Do not print error messages from getopt */
-	while ((c = getopt(argc, argv, options)) != -1) {
-		switch (c) {
-		case 'h':
-			fprintf(stderr, usage, argv[0]);
-			exit(EXIT_SUCCESS);
-		}
-	}
-
-	for (i = 0; i < MAX_CARDS_SUPPORTED; i++)
-		drm_amdgpu[i] = -1;
-
-	if (amdgpu_open_devices(open_render_node) <= 0) {
-		perror("Cannot open AMDGPU device");
-		exit(EXIT_FAILURE);
-	}
-
-	if (drm_amdgpu[0] < 0) {
-		perror("Cannot open AMDGPU device");
-		exit(EXIT_FAILURE);
-	}
-
-	/* Parse command line string */
-	opterr = 0;		/* Do not print error messages from getopt */
-	optind = 1;
-	while ((c = getopt(argc, argv, options)) != -1) {
-		switch (c) {
-		case 'p':
-			display_devices = 1;
-			break;
-		}
-	}
-
-	if (display_devices) {
-		amdgpu_print_devices();
-		amdgpu_close_devices();
-		exit(EXIT_SUCCESS);
-	}
-
-	/* Parse command line string */
-	opterr = 0;		/* Do not print error messages from getopt */
-	optind = 1;
-	while ((c = getopt(argc, argv, options)) != -1) {
-		switch (c) {
-		case 'b':
-			pci_bus_id = atoi(optarg);
-			break;
-		case 'd':
-			sscanf(optarg, "%x", &pci_device_id);
-			break;
-		}
-	}
-
-	if (pci_bus_id > 0 || pci_device_id) {
-		/* A device was specified to run the test */
-		test_device_index = amdgpu_find_device(pci_bus_id,
-						       pci_device_id);
-
-		if (test_device_index >= 0) {
-			/* Most tests run on device of drm_amdgpu[0].
-			 * Swap the chosen device to drm_amdgpu[0].
-			 */
-			i = drm_amdgpu[0];
-			drm_amdgpu[0] = drm_amdgpu[test_device_index];
-			drm_amdgpu[test_device_index] = i;
-		} else {
-			fprintf(stderr,
-				"The specified GPU device does not exist.\n");
-			exit(EXIT_FAILURE);
-		}
-	}
-
-	/* Initialize test suites to run */
-
-	/* initialize the CUnit test registry */
-	if (CUE_SUCCESS != CU_initialize_registry()) {
-		amdgpu_close_devices();
-		return CU_get_error();
-	}
-
-	/* Register suites. */
-	if (CU_register_suites(suites) != CUE_SUCCESS) {
-		fprintf(stderr, "suite registration failed - %s\n",
-				CU_get_error_msg());
-		CU_cleanup_registry();
-		amdgpu_close_devices();
-		exit(EXIT_FAILURE);
-	}
-
-	/* Run tests using the CUnit Basic interface */
-	CU_basic_set_mode(CU_BRM_VERBOSE);
-
-	/* Disable suites and individual tests based on misc. conditions */
-	amdgpu_disable_suites();
-
-	/* Parse command line string */
-	opterr = 0;		/* Do not print error messages from getopt */
-	optind = 1;
-	while ((c = getopt(argc, argv, options)) != -1) {
-		switch (c) {
-		case 'l':
-			display_list = 1;
-			break;
-		}
-	}
-
-	if (display_list) {
-		display_test_suites();
-		goto end;
-	}
-
-	/* Parse command line string */
-	opterr = 0;		/* Do not print error messages from getopt */
-	optind = 1;
-	while ((c = getopt(argc, argv, options)) != -1) {
-		long esuite = -1;
-		long etest = -1;
-		char *endp;
-		switch (c) {
-		case 's':
-			suite_id = atoi(optarg);
-			break;
-		case 't':
-			test_id = atoi(optarg);
-			break;
-		case 'r':
-                       open_render_node = 1;
-                       break;
-		case 'f':
-			force_run = 1;
-			break;
-		case 'e':
-			esuite = strtol(optarg, &endp, 0);
-			if (endp == optarg) {
-				fprintf(stderr, "No digits given for -e argument\n");
-				goto end;
-			} else if (endp && *endp == '.' && esuite > 0) {
-				char *tt = endp + 1;
-				etest = strtol(tt, &endp, 0);
-				if (endp == tt) {
-					fprintf(stderr, "No digits given for test in -e s.t argument\n");
-					goto end;
-				} else if (endp && *endp != '\0') {
-					fprintf(stderr, "Bad input given for test in -e s.t argument\n");
-					goto end;
-				} else if (etest < 1) {
-					fprintf(stderr, "Test in -e s.t argument cannot be smaller than 1\n");
-					goto end;
-				}
-			} else if (endp && *endp != '\0') {
-				fprintf(stderr, "Bad input given for suite for -e s argument\n");
-				goto end;
-			} else if (esuite < 1) {
-				fprintf(stderr, "Suite in -e s argument cannot be smaller than 1\n");
-				goto end;
-			}
-			amdgpu_test_disable(esuite, etest);
-			break;
-		case 'h':
-		case 'p':
-		case 'b':
-		case 'd':
-		case 'l':
-			/* Those have been processed earlier.
-			 */
-			break;
-		case '?':
-		default:
-			fprintf(stderr, "Unknown command line option '%c'. Try -h.\n",
-				c == '?' ? optopt : c);
-			goto end;
-		}
-	}
-
-	if (suite_id != -1) {	/* If user specify particular suite? */
-		pSuite = CU_get_suite_by_index((unsigned int) suite_id,
-						CU_get_registry());
-
-		if (pSuite) {
-
-			if (force_run)
-				CU_set_suite_active(pSuite, CU_TRUE);
-
-			if (test_id != -1) {   /* If user specify test id */
-				pTest = CU_get_test_by_index(
-						(unsigned int) test_id,
-						pSuite);
-				if (pTest) {
-					if (force_run)
-						CU_set_test_active(pTest, CU_TRUE);
-
-					CU_basic_run_test(pSuite, pTest);
-				}
-				else {
-					fprintf(stderr, "Invalid test id: %d\n",
-								test_id);
-					CU_cleanup_registry();
-					amdgpu_close_devices();
-					exit(EXIT_FAILURE);
-				}
-			} else
-				CU_basic_run_suite(pSuite);
-		} else {
-			fprintf(stderr, "Invalid suite id : %d\n",
-					suite_id);
-			CU_cleanup_registry();
-			amdgpu_close_devices();
-			exit(EXIT_FAILURE);
-		}
-	} else
-		CU_basic_run_tests();
-
-end:
-	CU_cleanup_registry();
-	amdgpu_close_devices();
-	return CU_get_error();
-}

tests/amdgpu/amdgpu_test.h

@@ -1,546 +0,0 @@
-/*
- * Copyright 2014 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
-*/
-
-#ifndef _AMDGPU_TEST_H_
-#define _AMDGPU_TEST_H_
-
-#include "amdgpu.h"
-#include "amdgpu_drm.h"
-
-/**
- * Define max. number of card in system which we are able to handle
- */
-#define MAX_CARDS_SUPPORTED     128
-
-/* Forward reference for array to keep "drm" handles */
-extern int drm_amdgpu[MAX_CARDS_SUPPORTED];
-
-/* Global variables */
-extern int open_render_node;
-
-/*************************  Basic test suite ********************************/
-
-/*
- * Define basic test suite to serve as the starting point for future testing
-*/
-
-/**
- * Initialize basic test suite
- */
-int suite_basic_tests_init();
-
-/**
- * Deinitialize basic test suite
- */
-int suite_basic_tests_clean();
-
-/**
- * Decide if the suite is enabled by default or not.
- */
-CU_BOOL suite_basic_tests_enable(void);
-
-/**
- * Tests in basic test suite
- */
-extern CU_TestInfo basic_tests[];
-
-/**
- * Initialize bo test suite
- */
-int suite_bo_tests_init();
-
-/**
- * Deinitialize bo test suite
- */
-int suite_bo_tests_clean();
-
-/**
- * Tests in bo test suite
- */
-extern CU_TestInfo bo_tests[];
-
-/**
- * Initialize cs test suite
- */
-int suite_cs_tests_init();
-
-/**
- * Deinitialize cs test suite
- */
-int suite_cs_tests_clean();
-
-/**
- * Decide if the suite is enabled by default or not.
- */
-CU_BOOL suite_cs_tests_enable(void);
-
-/**
- * Tests in cs test suite
- */
-extern CU_TestInfo cs_tests[];
-
-/**
- * Initialize vce test suite
- */
-int suite_vce_tests_init();
-
-/**
- * Deinitialize vce test suite
- */
-int suite_vce_tests_clean();
-
-/**
- * Decide if the suite is enabled by default or not.
- */
-CU_BOOL suite_vce_tests_enable(void);
-
-/**
- * Tests in vce test suite
- */
-extern CU_TestInfo vce_tests[];
-
-/**
-+ * Initialize vcn test suite
-+ */
-int suite_vcn_tests_init();
-
-/**
-+ * Deinitialize vcn test suite
-+ */
-int suite_vcn_tests_clean();
-
-/**
- * Decide if the suite is enabled by default or not.
- */
-CU_BOOL suite_vcn_tests_enable(void);
-
-/**
-+ * Tests in vcn test suite
-+ */
-extern CU_TestInfo vcn_tests[];
-
-/**
-+ * Initialize jpeg test suite
-+ */
-int suite_jpeg_tests_init();
-
-/**
-+ * Deinitialize jpeg test suite
-+ */
-int suite_jpeg_tests_clean();
-
-/**
- * Decide if the suite is enabled by default or not.
- */
-CU_BOOL suite_jpeg_tests_enable(void);
-
-/**
-+ * Tests in vcn test suite
-+ */
-extern CU_TestInfo jpeg_tests[];
-
-/**
- * Initialize uvd enc test suite
- */
-int suite_uvd_enc_tests_init();
-
-/**
- * Deinitialize uvd enc test suite
- */
-int suite_uvd_enc_tests_clean();
-
-/**
- * Decide if the suite is enabled by default or not.
- */
-CU_BOOL suite_uvd_enc_tests_enable(void);
-
-/**
- * Tests in uvd enc test suite
- */
-extern CU_TestInfo uvd_enc_tests[];
-
-/**
- * Initialize deadlock test suite
- */
-int suite_deadlock_tests_init();
-
-/**
- * Deinitialize deadlock test suite
- */
-int suite_deadlock_tests_clean();
-
-/**
- * Decide if the suite is enabled by default or not.
- */
-CU_BOOL suite_deadlock_tests_enable(void);
-
-/**
- * Tests in uvd enc test suite
- */
-extern CU_TestInfo deadlock_tests[];
-
-/**
- * Initialize vm test suite
- */
-int suite_vm_tests_init();
-
-/**
- * Deinitialize deadlock test suite
- */
-int suite_vm_tests_clean();
-
-/**
- * Decide if the suite is enabled by default or not.
- */
-CU_BOOL suite_vm_tests_enable(void);
-
-/**
- * Tests in vm test suite
- */
-extern CU_TestInfo vm_tests[];
-
-
-/**
- * Initialize ras test suite
- */
-int suite_ras_tests_init();
-
-/**
- * Deinitialize deadlock test suite
- */
-int suite_ras_tests_clean();
-
-/**
- * Decide if the suite is enabled by default or not.
- */
-CU_BOOL suite_ras_tests_enable(void);
-
-/**
- * Tests in ras test suite
- */
-extern CU_TestInfo ras_tests[];
-
-
-/**
- * Initialize syncobj timeline test suite
- */
-int suite_syncobj_timeline_tests_init();
-
-/**
- * Deinitialize syncobj timeline test suite
- */
-int suite_syncobj_timeline_tests_clean();
-
-/**
- * Decide if the suite is enabled by default or not.
- */
-CU_BOOL suite_syncobj_timeline_tests_enable(void);
-
-/**
- * Tests in syncobj timeline test suite
- */
-extern CU_TestInfo syncobj_timeline_tests[];
-
-
-/**
- * Initialize cp dma test suite
- */
-int suite_cp_dma_tests_init();
-
-/**
- * Deinitialize cp dma test suite
- */
-int suite_cp_dma_tests_clean();
-
-/**
- * Decide if the suite is enabled by default or not.
- */
-CU_BOOL suite_cp_dma_tests_enable(void);
-
-/**
- * Tests in cp dma test suite
- */
-extern CU_TestInfo cp_dma_tests[];
-
-/**
- * Initialize security test suite
- */
-int suite_security_tests_init();
-
-/**
- * Deinitialize security test suite
- */
-int suite_security_tests_clean();
-
-/**
- * Decide if the suite is enabled by default or not.
- */
-CU_BOOL suite_security_tests_enable(void);
-
-/**
- * Tests in security test suite
- */
-extern CU_TestInfo security_tests[];
-
-extern void
-amdgpu_command_submission_write_linear_helper_with_secure(amdgpu_device_handle
-							  device,
-							  unsigned ip_type,
-							  bool secure);
-
-extern void amdgpu_test_dispatch_helper(amdgpu_device_handle device_handle, unsigned ip);
-extern void amdgpu_test_dispatch_hang_helper(amdgpu_device_handle device_handle, uint32_t ip);
-extern void amdgpu_test_dispatch_hang_slow_helper(amdgpu_device_handle device_handle, uint32_t ip);
-extern void amdgpu_test_draw_helper(amdgpu_device_handle device_handle);
-extern void amdgpu_test_draw_hang_helper(amdgpu_device_handle device_handle);
-extern void amdgpu_test_draw_hang_slow_helper(amdgpu_device_handle device_handle);
-
-/**
- * Initialize hotunplug test suite
- */
-int suite_hotunplug_tests_init();
-
-/**
- * Deinitialize hotunplug test suite
- */
-int suite_hotunplug_tests_clean();
-
-/**
- * Decide if the suite is enabled by default or not.
- */
-CU_BOOL suite_hotunplug_tests_enable(void);
-
-/**
- * Tests in uvd enc test suite
- */
-extern CU_TestInfo hotunplug_tests[];
-
-
-/**
- * Helper functions
- */
-static inline amdgpu_bo_handle gpu_mem_alloc(
-					amdgpu_device_handle device_handle,
-					uint64_t size,
-					uint64_t alignment,
-					uint32_t type,
-					uint64_t flags,
-					uint64_t *vmc_addr,
-					amdgpu_va_handle *va_handle)
-{
-	struct amdgpu_bo_alloc_request req = {0};
-	amdgpu_bo_handle buf_handle = NULL;
-	int r;
-
-	req.alloc_size = size;
-	req.phys_alignment = alignment;
-	req.preferred_heap = type;
-	req.flags = flags;
-
-	r = amdgpu_bo_alloc(device_handle, &req, &buf_handle);
-	CU_ASSERT_EQUAL(r, 0);
-	if (r)
-		return NULL;
-
-	if (vmc_addr && va_handle) {
-		r = amdgpu_va_range_alloc(device_handle,
-					  amdgpu_gpu_va_range_general,
-					  size, alignment, 0, vmc_addr,
-					  va_handle, 0);
-		CU_ASSERT_EQUAL(r, 0);
-		if (r)
-			goto error_free_bo;
-
-		r = amdgpu_bo_va_op(buf_handle, 0, size, *vmc_addr, 0,
-				    AMDGPU_VA_OP_MAP);
-		CU_ASSERT_EQUAL(r, 0);
-		if (r)
-			goto error_free_va;
-	}
-
-	return buf_handle;
-
-error_free_va:
-	r = amdgpu_va_range_free(*va_handle);
-	CU_ASSERT_EQUAL(r, 0);
-
-error_free_bo:
-	r = amdgpu_bo_free(buf_handle);
-	CU_ASSERT_EQUAL(r, 0);
-
-	return NULL;
-}
-
-static inline int gpu_mem_free(amdgpu_bo_handle bo,
-			       amdgpu_va_handle va_handle,
-			       uint64_t vmc_addr,
-			       uint64_t size)
-{
-	int r;
-
-	if (!bo)
-		return 0;
-
-	if (va_handle) {
-		r = amdgpu_bo_va_op(bo, 0, size, vmc_addr, 0,
-				    AMDGPU_VA_OP_UNMAP);
-		CU_ASSERT_EQUAL(r, 0);
-		if (r)
-			return r;
-
-		r = amdgpu_va_range_free(va_handle);
-		CU_ASSERT_EQUAL(r, 0);
-		if (r)
-			return r;
-	}
-
-	r = amdgpu_bo_free(bo);
-	CU_ASSERT_EQUAL(r, 0);
-
-	return r;
-}
-
-static inline int
-amdgpu_bo_alloc_wrap(amdgpu_device_handle dev, unsigned size,
-		     unsigned alignment, unsigned heap, uint64_t flags,
-		     amdgpu_bo_handle *bo)
-{
-	struct amdgpu_bo_alloc_request request = {};
-	amdgpu_bo_handle buf_handle;
-	int r;
-
-	request.alloc_size = size;
-	request.phys_alignment = alignment;
-	request.preferred_heap = heap;
-	request.flags = flags;
-
-	r = amdgpu_bo_alloc(dev, &request, &buf_handle);
-	if (r)
-		return r;
-
-	*bo = buf_handle;
-
-	return 0;
-}
-
-int amdgpu_bo_alloc_and_map_raw(amdgpu_device_handle dev, unsigned size,
-			unsigned alignment, unsigned heap, uint64_t alloc_flags,
-			uint64_t mapping_flags, amdgpu_bo_handle *bo, void **cpu,
-			uint64_t *mc_address,
-			amdgpu_va_handle *va_handle);
-
-static inline int
-amdgpu_bo_alloc_and_map(amdgpu_device_handle dev, unsigned size,
-			unsigned alignment, unsigned heap, uint64_t alloc_flags,
-			amdgpu_bo_handle *bo, void **cpu, uint64_t *mc_address,
-			amdgpu_va_handle *va_handle)
-{
-	return amdgpu_bo_alloc_and_map_raw(dev, size, alignment, heap,
-					alloc_flags, 0, bo, cpu, mc_address, va_handle);
-}
-
-static inline int
-amdgpu_bo_unmap_and_free(amdgpu_bo_handle bo, amdgpu_va_handle va_handle,
-			 uint64_t mc_addr, uint64_t size)
-{
-	amdgpu_bo_cpu_unmap(bo);
-	amdgpu_bo_va_op(bo, 0, size, mc_addr, 0, AMDGPU_VA_OP_UNMAP);
-	amdgpu_va_range_free(va_handle);
-	amdgpu_bo_free(bo);
-
-	return 0;
-
-}
-
-static inline int
-amdgpu_get_bo_list(amdgpu_device_handle dev, amdgpu_bo_handle bo1,
-		   amdgpu_bo_handle bo2, amdgpu_bo_list_handle *list)
-{
-	amdgpu_bo_handle resources[] = {bo1, bo2};
-
-	return amdgpu_bo_list_create(dev, bo2 ? 2 : 1, resources, NULL, list);
-}
-
-
-static inline CU_ErrorCode amdgpu_set_suite_active(const char *suite_name,
-							  CU_BOOL active)
-{
-	CU_ErrorCode r = CU_set_suite_active(CU_get_suite(suite_name), active);
-
-	if (r != CUE_SUCCESS)
-		fprintf(stderr, "Failed to obtain suite %s\n", suite_name);
-
-	return r;
-}
-
-static inline CU_ErrorCode amdgpu_set_test_active(const char *suite_name,
-				  const char *test_name, CU_BOOL active)
-{
-	CU_ErrorCode r;
-	CU_pSuite pSuite = CU_get_suite(suite_name);
-
-	if (!pSuite) {
-		fprintf(stderr, "Failed to obtain suite %s\n",
-				suite_name);
-		return CUE_NOSUITE;
-	}
-
-	r = CU_set_test_active(CU_get_test(pSuite, test_name), active);
-	if (r != CUE_SUCCESS)
-		fprintf(stderr, "Failed to obtain test %s\n", test_name);
-
-	return r;
-}
-
-
-static inline bool asic_is_gfx_pipe_removed(uint32_t family_id, uint32_t chip_id, uint32_t chip_rev)
-{
-
-	if (family_id != AMDGPU_FAMILY_AI)
-	return false;
-
-	switch (chip_id - chip_rev) {
-	/* Arcturus */
-	case 0x32:
-	/* Aldebaran */
-	case 0x3c:
-		return true;
-	default:
-		return false;
-	}
-}
-
-void amdgpu_test_exec_cs_helper_raw(amdgpu_device_handle device_handle,
-				    amdgpu_context_handle context_handle,
-				    unsigned ip_type, int instance, int pm4_dw,
-				    uint32_t *pm4_src, int res_cnt,
-				    amdgpu_bo_handle *resources,
-				    struct amdgpu_cs_ib_info *ib_info,
-				    struct amdgpu_cs_request *ibs_request,
-				    bool secure);
-
-void amdgpu_close_devices();
-int amdgpu_open_device_on_test_index(int render_node);
-char *amdgpu_get_device_from_fd(int fd);
-
-#endif  /* #ifdef _AMDGPU_TEST_H_ */

tests/amdgpu/bo_tests.c

@@ -1,317 +0,0 @@
-/*
- * Copyright 2014 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
-*/
-
-#include <stdio.h>
-
-#include "CUnit/Basic.h"
-
-#include "amdgpu_test.h"
-#include "amdgpu_drm.h"
-#include "amdgpu_internal.h"
-
-#define BUFFER_SIZE (4*1024)
-#define BUFFER_ALIGN (4*1024)
-
-static amdgpu_device_handle device_handle;
-static uint32_t major_version;
-static uint32_t minor_version;
-
-static amdgpu_bo_handle buffer_handle;
-static uint64_t virtual_mc_base_address;
-static amdgpu_va_handle va_handle;
-
-static void amdgpu_bo_export_import(void);
-static void amdgpu_bo_metadata(void);
-static void amdgpu_bo_map_unmap(void);
-static void amdgpu_memory_alloc(void);
-static void amdgpu_mem_fail_alloc(void);
-static void amdgpu_bo_find_by_cpu_mapping(void);
-
-CU_TestInfo bo_tests[] = {
-	{ "Export/Import",  amdgpu_bo_export_import },
-	{ "Metadata",  amdgpu_bo_metadata },
-	{ "CPU map/unmap",  amdgpu_bo_map_unmap },
-	{ "Memory alloc Test",  amdgpu_memory_alloc },
-	{ "Memory fail alloc Test",  amdgpu_mem_fail_alloc },
-	{ "Find bo by CPU mapping",  amdgpu_bo_find_by_cpu_mapping },
-	CU_TEST_INFO_NULL,
-};
-
-int suite_bo_tests_init(void)
-{
-	struct amdgpu_bo_alloc_request req = {0};
-	amdgpu_bo_handle buf_handle;
-	uint64_t va;
-	int r;
-
-	r = amdgpu_device_initialize(drm_amdgpu[0], &major_version,
-				  &minor_version, &device_handle);
-	if (r) {
-		if ((r == -EACCES) && (errno == EACCES))
-			printf("\n\nError:%s. "
-				"Hint:Try to run this test program as root.",
-				strerror(errno));
-
-		return CUE_SINIT_FAILED;
-	}
-
-	req.alloc_size = BUFFER_SIZE;
-	req.phys_alignment = BUFFER_ALIGN;
-	req.preferred_heap = AMDGPU_GEM_DOMAIN_GTT;
-
-	r = amdgpu_bo_alloc(device_handle, &req, &buf_handle);
-	if (r)
-		return CUE_SINIT_FAILED;
-
-	r = amdgpu_va_range_alloc(device_handle,
-				  amdgpu_gpu_va_range_general,
-				  BUFFER_SIZE, BUFFER_ALIGN, 0,
-				  &va, &va_handle, 0);
-	if (r)
-		goto error_va_alloc;
-
-	r = amdgpu_bo_va_op(buf_handle, 0, BUFFER_SIZE, va, 0, AMDGPU_VA_OP_MAP);
-	if (r)
-		goto error_va_map;
-
-	buffer_handle = buf_handle;
-	virtual_mc_base_address = va;
-
-	return CUE_SUCCESS;
-
-error_va_map:
-	amdgpu_va_range_free(va_handle);
-
-error_va_alloc:
-	amdgpu_bo_free(buf_handle);
-	return CUE_SINIT_FAILED;
-}
-
-int suite_bo_tests_clean(void)
-{
-	int r;
-
-	r = amdgpu_bo_va_op(buffer_handle, 0, BUFFER_SIZE,
-			    virtual_mc_base_address, 0,
-			    AMDGPU_VA_OP_UNMAP);
-	if (r)
-		return CUE_SCLEAN_FAILED;
-
-	r = amdgpu_va_range_free(va_handle);
-	if (r)
-		return CUE_SCLEAN_FAILED;
-
-	r = amdgpu_bo_free(buffer_handle);
-	if (r)
-		return CUE_SCLEAN_FAILED;
-
-	r = amdgpu_device_deinitialize(device_handle);
-	if (r)
-		return CUE_SCLEAN_FAILED;
-
-	return CUE_SUCCESS;
-}
-
-static void amdgpu_bo_export_import_do_type(enum amdgpu_bo_handle_type type)
-{
-	struct amdgpu_bo_import_result res = {0};
-	uint32_t shared_handle;
-	int r;
-
-	r = amdgpu_bo_export(buffer_handle, type, &shared_handle);
-	CU_ASSERT_EQUAL(r, 0);
-
-	r = amdgpu_bo_import(device_handle, type, shared_handle, &res);
-	CU_ASSERT_EQUAL(r, 0);
-
-	CU_ASSERT_EQUAL(res.buf_handle, buffer_handle);
-	CU_ASSERT_EQUAL(res.alloc_size, BUFFER_SIZE);
-
-	r = amdgpu_bo_free(res.buf_handle);
-	CU_ASSERT_EQUAL(r, 0);
-}
-
-static void amdgpu_bo_export_import(void)
-{
-	if (open_render_node) {
-		printf("(DRM render node is used. Skip export/Import test) ");
-		return;
-	}
-
-	amdgpu_bo_export_import_do_type(amdgpu_bo_handle_type_gem_flink_name);
-	amdgpu_bo_export_import_do_type(amdgpu_bo_handle_type_dma_buf_fd);
-}
-
-static void amdgpu_bo_metadata(void)
-{
-	struct amdgpu_bo_metadata meta = {0};
-	struct amdgpu_bo_info info = {0};
-	int r;
-
-	meta.size_metadata = 4;
-	meta.umd_metadata[0] = 0xdeadbeef;
-
-	r = amdgpu_bo_set_metadata(buffer_handle, &meta);
-	CU_ASSERT_EQUAL(r, 0);
-
-	r = amdgpu_bo_query_info(buffer_handle, &info);
-	CU_ASSERT_EQUAL(r, 0);
-
-	CU_ASSERT_EQUAL(info.metadata.size_metadata, 4);
-	CU_ASSERT_EQUAL(info.metadata.umd_metadata[0], 0xdeadbeef);
-}
-
-static void amdgpu_bo_map_unmap(void)
-{
-	uint32_t *ptr;
-	int i, r;
-
-	r = amdgpu_bo_cpu_map(buffer_handle, (void **)&ptr);
-	CU_ASSERT_EQUAL(r, 0);
-	CU_ASSERT_NOT_EQUAL(ptr, NULL);
-
-	for (i = 0; i < (BUFFER_SIZE / 4); ++i)
-		ptr[i] = 0xdeadbeef;
-
-	r = amdgpu_bo_cpu_unmap(buffer_handle);
-	CU_ASSERT_EQUAL(r, 0);
-}
-
-static void amdgpu_memory_alloc(void)
-{
-	amdgpu_bo_handle bo;
-	amdgpu_va_handle va_handle;
-	uint64_t bo_mc;
-	int r;
-
-	/* Test visible VRAM */
-	bo = gpu_mem_alloc(device_handle,
-			4096, 4096,
-			AMDGPU_GEM_DOMAIN_VRAM,
-			AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
-			&bo_mc, &va_handle);
-
-	r = gpu_mem_free(bo, va_handle, bo_mc, 4096);
-	CU_ASSERT_EQUAL(r, 0);
-
-	/* Test invisible VRAM */
-	bo = gpu_mem_alloc(device_handle,
-			4096, 4096,
-			AMDGPU_GEM_DOMAIN_VRAM,
-			AMDGPU_GEM_CREATE_NO_CPU_ACCESS,
-			&bo_mc, &va_handle);
-
-	r = gpu_mem_free(bo, va_handle, bo_mc, 4096);
-	CU_ASSERT_EQUAL(r, 0);
-
-	/* Test GART Cacheable */
-	bo = gpu_mem_alloc(device_handle,
-			4096, 4096,
-			AMDGPU_GEM_DOMAIN_GTT,
-			0, &bo_mc, &va_handle);
-
-	r = gpu_mem_free(bo, va_handle, bo_mc, 4096);
-	CU_ASSERT_EQUAL(r, 0);
-
-	/* Test GART USWC */
-	bo = gpu_mem_alloc(device_handle,
-			4096, 4096,
-			AMDGPU_GEM_DOMAIN_GTT,
-			AMDGPU_GEM_CREATE_CPU_GTT_USWC,
-			&bo_mc, &va_handle);
-
-	r = gpu_mem_free(bo, va_handle, bo_mc, 4096);
-	CU_ASSERT_EQUAL(r, 0);
-
-	/* Test GDS */
-	bo = gpu_mem_alloc(device_handle, 1024, 0,
-			AMDGPU_GEM_DOMAIN_GDS, 0,
-			NULL, NULL);
-	r = gpu_mem_free(bo, NULL, 0, 4096);
-	CU_ASSERT_EQUAL(r, 0);
-
-	/* Test GWS */
-	bo = gpu_mem_alloc(device_handle, 1, 0,
-			AMDGPU_GEM_DOMAIN_GWS, 0,
-			NULL, NULL);
-	r = gpu_mem_free(bo, NULL, 0, 4096);
-	CU_ASSERT_EQUAL(r, 0);
-
-	/* Test OA */
-	bo = gpu_mem_alloc(device_handle, 1, 0,
-			AMDGPU_GEM_DOMAIN_OA, 0,
-			NULL, NULL);
-	r = gpu_mem_free(bo, NULL, 0, 4096);
-	CU_ASSERT_EQUAL(r, 0);
-}
-
-static void amdgpu_mem_fail_alloc(void)
-{
-	int r;
-	struct amdgpu_bo_alloc_request req = {0};
-	amdgpu_bo_handle buf_handle;
-
-	/* Test impossible mem allocation, 1TB */
-	req.alloc_size = 0xE8D4A51000;
-	req.phys_alignment = 4096;
-	req.preferred_heap = AMDGPU_GEM_DOMAIN_VRAM;
-	req.flags = AMDGPU_GEM_CREATE_NO_CPU_ACCESS;
-
-	r = amdgpu_bo_alloc(device_handle, &req, &buf_handle);
-	CU_ASSERT_EQUAL(r, -ENOMEM);
-
-	if (!r) {
-		r = amdgpu_bo_free(buf_handle);
-		CU_ASSERT_EQUAL(r, 0);
-	}
-}
-
-static void amdgpu_bo_find_by_cpu_mapping(void)
-{
-	amdgpu_bo_handle bo_handle, find_bo_handle;
-	amdgpu_va_handle va_handle;
-	void *bo_cpu;
-	uint64_t bo_mc_address;
-	uint64_t offset;
-	int r;
-
-	r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096,
-				    AMDGPU_GEM_DOMAIN_GTT, 0,
-				    &bo_handle, &bo_cpu,
-				    &bo_mc_address, &va_handle);
-	CU_ASSERT_EQUAL(r, 0);
-
-	r = amdgpu_find_bo_by_cpu_mapping(device_handle,
-					  bo_cpu,
-					  4096,
-					  &find_bo_handle,
-					  &offset);
-	CU_ASSERT_EQUAL(r, 0);
-	CU_ASSERT_EQUAL(offset, 0);
-	CU_ASSERT_EQUAL(bo_handle->handle, find_bo_handle->handle);
-
-	atomic_dec(&find_bo_handle->refcount, 1);
-	r = amdgpu_bo_unmap_and_free(bo_handle, va_handle,
-				     bo_mc_address, 4096);
-	CU_ASSERT_EQUAL(r, 0);
-}

tests/amdgpu/cp_dma_tests.c

@@ -1,533 +0,0 @@
-/*
- * Copyright 2022 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
-*/
-
-#include <unistd.h>
-#include <stdio.h>
-#include <stdlib.h>
-#include <inttypes.h>
-
-#include "CUnit/Basic.h"
-
-#include "amdgpu_test.h"
-#include "amdgpu_drm.h"
-#include "amdgpu_internal.h"
-
-#define IB_SIZE 4096
-#define MAX_RESOURCES 8
-
-#define DMA_SIZE 4097 
-#define DMA_DATA_BYTE 0xea
-
-static bool do_p2p;
-
-static amdgpu_device_handle executing_device_handle;
-static uint32_t executing_device_major_version;
-static uint32_t executing_device_minor_version;
-
-static amdgpu_device_handle peer_exporting_device_handle;
-static uint32_t peer_exporting_device_major_version;
-static uint32_t peer_exporting_device_minor_version;
-
-static amdgpu_context_handle context_handle;
-static amdgpu_bo_handle ib_handle;
-static uint32_t *ib_cpu;
-static uint64_t ib_mc_address;
-static amdgpu_va_handle ib_va_handle;
-static uint32_t num_dword;
-
-static amdgpu_bo_handle resources[MAX_RESOURCES];
-static unsigned num_resources;
-
-static uint8_t* reference_data;
-
-static void amdgpu_cp_dma_host_to_vram(void);
-static void amdgpu_cp_dma_vram_to_host(void);
-static void amdgpu_cp_dma_p2p_vram_to_vram(void);
-static void amdgpu_cp_dma_p2p_host_to_vram(void);
-static void amdgpu_cp_dma_p2p_vram_to_host(void);
-
-/**
- * Tests in cp dma test suite
- */
-CU_TestInfo cp_dma_tests[] = {
-	{ "CP DMA write Host to VRAM",  amdgpu_cp_dma_host_to_vram },
-	{ "CP DMA write VRAM to Host",  amdgpu_cp_dma_vram_to_host },
-
-	{ "Peer to Peer CP DMA write VRAM to VRAM",  amdgpu_cp_dma_p2p_vram_to_vram },
-	{ "Peer to Peer CP DMA write Host to VRAM",  amdgpu_cp_dma_p2p_host_to_vram },
-	{ "Peer to Peer CP DMA write VRAM to Host",  amdgpu_cp_dma_p2p_vram_to_host },
-	CU_TEST_INFO_NULL,
-};
-
-struct amdgpu_cp_dma_bo{
-	amdgpu_bo_handle buf_handle;
-	amdgpu_va_handle va_handle;
-	uint64_t gpu_va;
-	uint64_t size;
-};
-
-static int allocate_bo_and_va(amdgpu_device_handle dev,
-		uint64_t size, uint64_t alignment,
-		uint32_t heap, uint64_t alloc_flags,
-		struct amdgpu_cp_dma_bo *bo) {
-	struct amdgpu_bo_alloc_request request = {};
-	amdgpu_bo_handle buf_handle;
-	amdgpu_va_handle va_handle;
-	uint64_t vmc_addr;
-	int r;
-
-	request.alloc_size = size;
-	request.phys_alignment = alignment;
-	request.preferred_heap = heap;
-	request.flags = alloc_flags;
-
-	r = amdgpu_bo_alloc(dev, &request, &buf_handle);
-	if (r)
-		goto error_bo_alloc;
-
-	r = amdgpu_va_range_alloc(dev, amdgpu_gpu_va_range_general,
-			size, alignment, 0,
-			&vmc_addr, &va_handle, 0);
-	if (r)
-		goto error_va_alloc;
-
-	r = amdgpu_bo_va_op(buf_handle, 0, size, vmc_addr,
-						AMDGPU_VM_PAGE_READABLE |
-							AMDGPU_VM_PAGE_WRITEABLE |
-							AMDGPU_VM_PAGE_EXECUTABLE,
-						AMDGPU_VA_OP_MAP);
-	if (r)
-		goto error_va_map;
-
-	bo->buf_handle = buf_handle;
-	bo->va_handle = va_handle;
-	bo->gpu_va = vmc_addr;
-	bo->size = size;
-
-	return 0;
-
-error_va_map:
-	amdgpu_bo_va_op(buf_handle, 0,
-			size, vmc_addr, 0, AMDGPU_VA_OP_UNMAP);
-
-error_va_alloc:
-	amdgpu_va_range_free(va_handle);
-
-error_bo_alloc:
-	amdgpu_bo_free(buf_handle);
-
-	return r;
-}
-
-static int import_dma_buf_to_bo(amdgpu_device_handle dev,
-		int dmabuf_fd, struct amdgpu_cp_dma_bo *bo) {
-	amdgpu_va_handle va_handle;
-	uint64_t vmc_addr;
-	int r;
-	struct amdgpu_bo_import_result bo_import_result = {};
-
-	r = amdgpu_bo_import(dev, amdgpu_bo_handle_type_dma_buf_fd,
-			dmabuf_fd, &bo_import_result);
-	if (r)
-		goto error_bo_import;
-
-	r = amdgpu_va_range_alloc(dev, amdgpu_gpu_va_range_general,
-				bo_import_result.alloc_size, 0, 0,
-				&vmc_addr, &va_handle, 0);
-	if (r)
-		goto error_va_alloc;
-
-	r = amdgpu_bo_va_op(bo_import_result.buf_handle, 0,
-			bo_import_result.alloc_size, vmc_addr,
-			AMDGPU_VM_PAGE_READABLE |
-				AMDGPU_VM_PAGE_WRITEABLE |
-				AMDGPU_VM_PAGE_EXECUTABLE,
-			AMDGPU_VA_OP_MAP);
-	if (r)
-		goto error_va_map;
-
-	bo->buf_handle = bo_import_result.buf_handle;
-	bo->va_handle = va_handle;
-	bo->gpu_va = vmc_addr;
-	bo->size = bo_import_result.alloc_size;
-
-	return 0;
-
-error_va_map:
-	amdgpu_bo_va_op(bo_import_result.buf_handle, 0,
-			bo_import_result.alloc_size, vmc_addr, 0, AMDGPU_VA_OP_UNMAP);
-
-error_va_alloc:
-	amdgpu_va_range_free(va_handle);
-
-error_bo_import:
-	amdgpu_bo_free(bo_import_result.buf_handle);
-
-	return r;
-}
-
-static int free_bo(struct amdgpu_cp_dma_bo bo) {
-	int r;
-	r = amdgpu_bo_va_op(bo.buf_handle, 0,
-			bo.size, bo.gpu_va, 0, AMDGPU_VA_OP_UNMAP);
-	if(r)
-		return r;
-
-	r = amdgpu_va_range_free(bo.va_handle);
-	if(r)
-		return r;
-
-	r = amdgpu_bo_free(bo.buf_handle);
-	if(r)
-		return r;
-
-	return 0;
-}
-
-static int submit_and_sync() {
-	struct amdgpu_cs_request ibs_request = {0};
-	struct amdgpu_cs_ib_info ib_info = {0};
-	struct amdgpu_cs_fence fence_status = {0};
-	uint32_t expired;
-	uint32_t family_id, chip_id, chip_rev;
-	unsigned gc_ip_type;
-	int r;
-
-	r = amdgpu_bo_list_create(executing_device_handle,
-			num_resources, resources,
-			NULL, &ibs_request.resources);
-	if (r)
-		return r;
-
-	family_id = executing_device_handle->info.family_id;
-	chip_id = executing_device_handle->info.chip_external_rev;
-	chip_rev = executing_device_handle->info.chip_rev;
-
-	gc_ip_type = (asic_is_gfx_pipe_removed(family_id, chip_id, chip_rev)) ?
-		AMDGPU_HW_IP_COMPUTE : AMDGPU_HW_IP_GFX;
-
-	ib_info.ib_mc_address = ib_mc_address;
-	ib_info.size = num_dword;
-
-	ibs_request.ip_type = gc_ip_type;
-	ibs_request.number_of_ibs = 1;
-	ibs_request.ibs = &ib_info;
-	ibs_request.fence_info.handle = NULL;
-
-	r = amdgpu_cs_submit(context_handle, 0, &ibs_request, 1);
-	if (r)
-		return r;
-
-	r = amdgpu_bo_list_destroy(ibs_request.resources);
-	if (r)
-		return r;
-
-	fence_status.context = context_handle;
-	fence_status.ip_type = gc_ip_type;
-	fence_status.fence = ibs_request.seq_no;
-
-	r = amdgpu_cs_query_fence_status(&fence_status,
-			AMDGPU_TIMEOUT_INFINITE,
-			0, &expired);
-	if (r)
-		return r;
-
-	return 0;
-} 
-
-static void cp_dma_cmd(struct amdgpu_cp_dma_bo src_bo,
-		struct amdgpu_cp_dma_bo dst_bo) {
-	_Static_assert(DMA_SIZE < (1 << 26), "DMA size exceeds CP DMA maximium!");
-
-	ib_cpu[0] = 0xc0055000;
-	ib_cpu[1] = 0x80000000;
-	ib_cpu[2] = src_bo.gpu_va & 0x00000000ffffffff;
-	ib_cpu[3] = (src_bo.gpu_va & 0xffffffff00000000) >> 32;
-	ib_cpu[4] = dst_bo.gpu_va & 0x00000000ffffffff;
-	ib_cpu[5] = (dst_bo.gpu_va & 0xffffffff00000000) >> 32;
-	// size is read from the lower 26bits. 
-	ib_cpu[6] = ((1 << 26) - 1) & DMA_SIZE;
-	ib_cpu[7] = 0xffff1000;
-
-	num_dword = 8;
-
-	resources[0] = src_bo.buf_handle;
-	resources[1] = dst_bo.buf_handle;
-	resources[2] = ib_handle;
-	num_resources = 3;
-}
-
-static void amdgpu_cp_dma(uint32_t src_heap, uint32_t dst_heap) {
-	int r;
-	struct amdgpu_cp_dma_bo src_bo = {0};
-	struct amdgpu_cp_dma_bo dst_bo = {0};
-	void *src_bo_cpu;
-	void *dst_bo_cpu;
-
-	/* allocate the src bo, set its data to DMA_DATA_BYTE */
-	r = allocate_bo_and_va(executing_device_handle, DMA_SIZE, 4096,
-			src_heap, AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, &src_bo);
-	CU_ASSERT_EQUAL(r, 0);
-
-	r = amdgpu_bo_cpu_map(src_bo.buf_handle, (void **)&src_bo_cpu);
-	CU_ASSERT_EQUAL(r, 0);
-	memset(src_bo_cpu, DMA_DATA_BYTE, DMA_SIZE);
-
-	r = amdgpu_bo_cpu_unmap(src_bo.buf_handle);
-	CU_ASSERT_EQUAL(r, 0);
-
-	/* allocate the dst bo and clear its content to all 0 */
-	r = allocate_bo_and_va(executing_device_handle, DMA_SIZE, 4096,
-			dst_heap, AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, &dst_bo);
-	CU_ASSERT_EQUAL(r, 0);
-
-	r = amdgpu_bo_cpu_map(dst_bo.buf_handle, (void **)&dst_bo_cpu);
-	CU_ASSERT_EQUAL(r, 0);
-
-	_Static_assert(DMA_DATA_BYTE != 0, "Initialization data should be different from DMA data!");
-	memset(dst_bo_cpu, 0, DMA_SIZE);
-
-	/* record CP DMA command and dispatch the command */
-	cp_dma_cmd(src_bo, dst_bo);
-
-	r = submit_and_sync();
-	CU_ASSERT_EQUAL(r, 0);
-
-	/* verify the dst bo is filled with DMA_DATA_BYTE */
-	CU_ASSERT_EQUAL(memcmp(dst_bo_cpu, reference_data, DMA_SIZE) == 0, true);
-
-	r = amdgpu_bo_cpu_unmap(dst_bo.buf_handle);
-	CU_ASSERT_EQUAL(r, 0);
-
-	r = free_bo(src_bo);
-	CU_ASSERT_EQUAL(r, 0);
-
-	r = free_bo(dst_bo);
-	CU_ASSERT_EQUAL(r, 0);
-}
-
-static void amdgpu_cp_dma_p2p(uint32_t src_heap, uint32_t dst_heap) {
-	int r;
-	struct amdgpu_cp_dma_bo exported_bo = {0};
-	int dma_buf_fd;
-	int dma_buf_fd_dup;
-	struct amdgpu_cp_dma_bo src_bo = {0};
-	struct amdgpu_cp_dma_bo imported_dst_bo = {0};
-	void *exported_bo_cpu;
-	void *src_bo_cpu;
-
-	/* allocate a bo on the peer device and export it to dma-buf */
-	r = allocate_bo_and_va(peer_exporting_device_handle, DMA_SIZE, 4096,
-			src_heap, AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, &exported_bo);
-	CU_ASSERT_EQUAL(r, 0);
-
-	/* map the exported bo and clear its content to 0 */
-	_Static_assert(DMA_DATA_BYTE != 0, "Initialization data should be different from DMA data!");
-	r = amdgpu_bo_cpu_map(exported_bo.buf_handle, (void **)&exported_bo_cpu);
-	CU_ASSERT_EQUAL(r, 0);
-	memset(exported_bo_cpu, 0, DMA_SIZE);
-
-	r = amdgpu_bo_export(exported_bo.buf_handle,
-			amdgpu_bo_handle_type_dma_buf_fd, (uint32_t*)&dma_buf_fd);
-	CU_ASSERT_EQUAL(r, 0);
-
-    // According to amdgpu_drm:
-	// "Buffer must be "imported" only using new "fd"
-	// (different from one used by "exporter")"
-	dma_buf_fd_dup = dup(dma_buf_fd);
-	r = close(dma_buf_fd);
-	CU_ASSERT_EQUAL(r, 0);
-
-	/* import the dma-buf to the executing device, imported bo is the DMA destination */
-	r = import_dma_buf_to_bo(
-			executing_device_handle, dma_buf_fd_dup, &imported_dst_bo);
-	CU_ASSERT_EQUAL(r, 0);
-
-	r = close(dma_buf_fd_dup);
-	CU_ASSERT_EQUAL(r, 0);
-
-	/* allocate the src bo and set its content to DMA_DATA_BYTE */
-	r = allocate_bo_and_va(executing_device_handle, DMA_SIZE, 4096,
-			dst_heap, AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, &src_bo);
-	CU_ASSERT_EQUAL(r, 0);
-
-	r = amdgpu_bo_cpu_map(src_bo.buf_handle, (void **)&src_bo_cpu);
-	CU_ASSERT_EQUAL(r, 0);
-
-	memset(src_bo_cpu, DMA_DATA_BYTE, DMA_SIZE);
-
-	r = amdgpu_bo_cpu_unmap(src_bo.buf_handle);
-	CU_ASSERT_EQUAL(r, 0);
-
-	/* record CP DMA command and dispatch the command */
-	cp_dma_cmd(src_bo, imported_dst_bo);
-
-	r = submit_and_sync();
-	CU_ASSERT_EQUAL(r, 0);
-
-	/* verify the bo from the peer device is filled with DMA_DATA_BYTE */
-	CU_ASSERT_EQUAL(memcmp(exported_bo_cpu, reference_data, DMA_SIZE) == 0, true);
-
-	r = amdgpu_bo_cpu_unmap(exported_bo.buf_handle);
-	CU_ASSERT_EQUAL(r, 0);
-
-	r = free_bo(exported_bo);
-	CU_ASSERT_EQUAL(r, 0);
-
-	r = free_bo(imported_dst_bo);
-	CU_ASSERT_EQUAL(r, 0);
-
-	r = free_bo(src_bo);
-	CU_ASSERT_EQUAL(r, 0);
-}
-
-static void amdgpu_cp_dma_host_to_vram(void) {
-	amdgpu_cp_dma(AMDGPU_GEM_DOMAIN_GTT, AMDGPU_GEM_DOMAIN_VRAM);
-}
-
-static void amdgpu_cp_dma_vram_to_host(void) {
-	amdgpu_cp_dma(AMDGPU_GEM_DOMAIN_VRAM, AMDGPU_GEM_DOMAIN_GTT);
-}
-
-static void amdgpu_cp_dma_p2p_vram_to_vram(void) {
-	amdgpu_cp_dma_p2p(AMDGPU_GEM_DOMAIN_VRAM, AMDGPU_GEM_DOMAIN_VRAM);
-}
-
-static void amdgpu_cp_dma_p2p_host_to_vram(void) {
-	amdgpu_cp_dma_p2p(AMDGPU_GEM_DOMAIN_GTT, AMDGPU_GEM_DOMAIN_VRAM);
-}
-
-static void amdgpu_cp_dma_p2p_vram_to_host(void) {
-	amdgpu_cp_dma_p2p(AMDGPU_GEM_DOMAIN_VRAM, AMDGPU_GEM_DOMAIN_GTT);
-}
-
-int suite_cp_dma_tests_init() {
-	int r;
-	
-	r = amdgpu_device_initialize(drm_amdgpu[0],
-			&executing_device_major_version,
-			&executing_device_minor_version,
-			&executing_device_handle);
-	if (r)
-		return CUE_SINIT_FAILED;
-	
-	r = amdgpu_cs_ctx_create(executing_device_handle, &context_handle);
-	if (r)
-		return CUE_SINIT_FAILED;
-
-	r = amdgpu_bo_alloc_and_map(executing_device_handle, IB_SIZE, 4096,
-					AMDGPU_GEM_DOMAIN_GTT, 0,
-					&ib_handle, (void**)&ib_cpu,
-					&ib_mc_address, &ib_va_handle);
-	if (r)
-		return CUE_SINIT_FAILED;
-	
-	if (do_p2p) {
-		r = amdgpu_device_initialize(drm_amdgpu[1],
-				&peer_exporting_device_major_version,
-				&peer_exporting_device_minor_version,
-				&peer_exporting_device_handle);
-		
-		if (r)
-			return CUE_SINIT_FAILED;
-	}
-
-	reference_data = (uint8_t*)malloc(DMA_SIZE);
-	if (!reference_data)
-		return CUE_SINIT_FAILED;
-	memset(reference_data, DMA_DATA_BYTE, DMA_SIZE);
-
-	return CUE_SUCCESS;
-}
-
-int suite_cp_dma_tests_clean() {
-	int r;
-
-	free(reference_data);
-
-	r = amdgpu_bo_unmap_and_free(ib_handle, ib_va_handle,
-				 ib_mc_address, IB_SIZE);
-	if (r)
-		return CUE_SCLEAN_FAILED;
-
-	r = amdgpu_cs_ctx_free(context_handle);
-	if (r)
-		return CUE_SCLEAN_FAILED;
-
-	r = amdgpu_device_deinitialize(executing_device_handle);
-	if (r)
-		return CUE_SCLEAN_FAILED;
-
-	if (do_p2p) {
-		r = amdgpu_device_deinitialize(peer_exporting_device_handle);
-		if (r)
-			return CUE_SCLEAN_FAILED;
-	}
-
-	return CUE_SUCCESS;
-}
-
-CU_BOOL suite_cp_dma_tests_enable(void) {
-	int r = 0;
-
-	if (amdgpu_device_initialize(drm_amdgpu[0],
-			&executing_device_major_version,
-			&executing_device_minor_version,
-			&executing_device_handle))
-		return CU_FALSE;
-
-	if (!(executing_device_handle->info.family_id >= AMDGPU_FAMILY_AI &&
-			executing_device_handle->info.family_id <= AMDGPU_FAMILY_NV)) {
-		printf("Testing device has ASIC that is not supported by CP-DMA test suite!\n");
-		return CU_FALSE;
-	}
-
-	if (amdgpu_device_deinitialize(executing_device_handle))
-		return CU_FALSE;	
-
-	if (drm_amdgpu[1] >= 0) {
-		r = amdgpu_device_initialize(drm_amdgpu[1],
-				&peer_exporting_device_major_version,
-				&peer_exporting_device_minor_version,
-				&peer_exporting_device_handle);
-		
-		if (r == 0 && (peer_exporting_device_handle->info.family_id >= AMDGPU_FAMILY_AI &&
-						peer_exporting_device_handle->info.family_id <= AMDGPU_FAMILY_NV)) {
-			do_p2p = true;
-		}
-
-		if (r == 0 && amdgpu_device_deinitialize(peer_exporting_device_handle) != 0) {
-			printf("Deinitialize peer_exporting_device_handle failed!\n");
-			return CU_FALSE;
-		}
-	}
-
-	if (!do_p2p) {
-		amdgpu_set_test_active("CP DMA Tests", "Peer to Peer CP DMA write VRAM to VRAM", CU_FALSE);
-		amdgpu_set_test_active("CP DMA Tests", "Peer to Peer CP DMA write Host to VRAM", CU_FALSE);
-		amdgpu_set_test_active("CP DMA Tests", "Peer to Peer CP DMA write VRAM to Host", CU_FALSE);
-		printf("Peer device is not opened or has ASIC not supported by the suite, skip all Peer to Peer tests.\n");
-	}
-	
-	return CU_TRUE;
-}

tests/amdgpu/cs_tests.c

@@ -1,471 +0,0 @@
-/*
- * Copyright 2014 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
-*/
-
-#include <stdio.h>
-
-#include "CUnit/Basic.h"
-
-#include "util_math.h"
-
-#include "amdgpu_test.h"
-#include "decode_messages.h"
-#include "amdgpu_drm.h"
-#include "amdgpu_internal.h"
-
-#define IB_SIZE		4096
-#define MAX_RESOURCES	16
-
-static amdgpu_device_handle device_handle;
-static uint32_t major_version;
-static uint32_t minor_version;
-static uint32_t family_id;
-static uint32_t chip_rev;
-static uint32_t chip_id;
-
-static amdgpu_context_handle context_handle;
-static amdgpu_bo_handle ib_handle;
-static uint64_t ib_mc_address;
-static uint32_t *ib_cpu;
-static amdgpu_va_handle ib_va_handle;
-
-static amdgpu_bo_handle resources[MAX_RESOURCES];
-static unsigned num_resources;
-
-static void amdgpu_cs_uvd_create(void);
-static void amdgpu_cs_uvd_decode(void);
-static void amdgpu_cs_uvd_destroy(void);
-
-CU_TestInfo cs_tests[] = {
-	{ "UVD create",  amdgpu_cs_uvd_create },
-	{ "UVD decode",  amdgpu_cs_uvd_decode },
-	{ "UVD destroy",  amdgpu_cs_uvd_destroy },
-	CU_TEST_INFO_NULL,
-};
-
-CU_BOOL suite_cs_tests_enable(void)
-{
-	if (amdgpu_device_initialize(drm_amdgpu[0], &major_version,
-					     &minor_version, &device_handle))
-		return CU_FALSE;
-
-	family_id = device_handle->info.family_id;
-    chip_id = device_handle->info.chip_external_rev;
-    chip_rev = device_handle->info.chip_rev;
-
-	if (amdgpu_device_deinitialize(device_handle))
-		return CU_FALSE;
-
-
-	if (family_id >= AMDGPU_FAMILY_RV || family_id == AMDGPU_FAMILY_SI ||
-		asic_is_gfx_pipe_removed(family_id, chip_id, chip_rev)) {
-		printf("\n\nThe ASIC NOT support UVD, suite disabled\n");
-		return CU_FALSE;
-	}
-
-	return CU_TRUE;
-}
-
-int suite_cs_tests_init(void)
-{
-	amdgpu_bo_handle ib_result_handle;
-	void *ib_result_cpu;
-	uint64_t ib_result_mc_address;
-	amdgpu_va_handle ib_result_va_handle;
-	int r;
-
-	r = amdgpu_device_initialize(drm_amdgpu[0], &major_version,
-				     &minor_version, &device_handle);
-	if (r) {
-		if ((r == -EACCES) && (errno == EACCES))
-			printf("\n\nError:%s. "
-				"Hint:Try to run this test program as root.",
-				strerror(errno));
-
-		return CUE_SINIT_FAILED;
-	}
-
-	family_id = device_handle->info.family_id;
-	/* VI asic POLARIS10/11 have specific external_rev_id */
-	chip_rev = device_handle->info.chip_rev;
-	chip_id = device_handle->info.chip_external_rev;
-
-	r = amdgpu_cs_ctx_create(device_handle, &context_handle);
-	if (r)
-		return CUE_SINIT_FAILED;
-
-	r = amdgpu_bo_alloc_and_map(device_handle, IB_SIZE, 4096,
-				    AMDGPU_GEM_DOMAIN_GTT, 0,
-				    &ib_result_handle, &ib_result_cpu,
-				    &ib_result_mc_address,
-				    &ib_result_va_handle);
-	if (r)
-		return CUE_SINIT_FAILED;
-
-	ib_handle = ib_result_handle;
-	ib_mc_address = ib_result_mc_address;
-	ib_cpu = ib_result_cpu;
-	ib_va_handle = ib_result_va_handle;
-
-	return CUE_SUCCESS;
-}
-
-int suite_cs_tests_clean(void)
-{
-	int r;
-
-	r = amdgpu_bo_unmap_and_free(ib_handle, ib_va_handle,
-				     ib_mc_address, IB_SIZE);
-	if (r)
-		return CUE_SCLEAN_FAILED;
-
-	r = amdgpu_cs_ctx_free(context_handle);
-	if (r)
-		return CUE_SCLEAN_FAILED;
-
-	r = amdgpu_device_deinitialize(device_handle);
-	if (r)
-		return CUE_SCLEAN_FAILED;
-
-	return CUE_SUCCESS;
-}
-
-static int submit(unsigned ndw, unsigned ip)
-{
-	struct amdgpu_cs_request ibs_request = {0};
-	struct amdgpu_cs_ib_info ib_info = {0};
-	struct amdgpu_cs_fence fence_status = {0};
-	uint32_t expired;
-	int r;
-
-	ib_info.ib_mc_address = ib_mc_address;
-	ib_info.size = ndw;
-
-	ibs_request.ip_type = ip;
-
-	r = amdgpu_bo_list_create(device_handle, num_resources, resources,
-				  NULL, &ibs_request.resources);
-	if (r)
-		return r;
-
-	ibs_request.number_of_ibs = 1;
-	ibs_request.ibs = &ib_info;
-	ibs_request.fence_info.handle = NULL;
-
-	r = amdgpu_cs_submit(context_handle, 0, &ibs_request, 1);
-	if (r)
-		return r;
-
-	r = amdgpu_bo_list_destroy(ibs_request.resources);
-	if (r)
-		return r;
-
-	fence_status.context = context_handle;
-	fence_status.ip_type = ip;
-	fence_status.fence = ibs_request.seq_no;
-
-	r = amdgpu_cs_query_fence_status(&fence_status,
-					 AMDGPU_TIMEOUT_INFINITE,
-					 0, &expired);
-	if (r)
-		return r;
-
-	return 0;
-}
-
-static void uvd_cmd(uint64_t addr, unsigned cmd, int *idx)
-{
-	ib_cpu[(*idx)++] = (family_id < AMDGPU_FAMILY_AI) ? 0x3BC4 : 0x81C4;
-	ib_cpu[(*idx)++] = addr;
-	ib_cpu[(*idx)++] = (family_id < AMDGPU_FAMILY_AI) ? 0x3BC5 : 0x81C5;
-	ib_cpu[(*idx)++] = addr >> 32;
-	ib_cpu[(*idx)++] = (family_id < AMDGPU_FAMILY_AI) ? 0x3BC3 : 0x81C3;
-	ib_cpu[(*idx)++] = cmd << 1;
-}
-
-static void amdgpu_cs_uvd_create(void)
-{
-	struct amdgpu_bo_alloc_request req = {0};
-	amdgpu_bo_handle buf_handle;
-	uint64_t va = 0;
-	amdgpu_va_handle va_handle;
-	void *msg;
-	int i, r;
-
-	req.alloc_size = 4*1024;
-	req.preferred_heap = AMDGPU_GEM_DOMAIN_GTT;
-
-	r = amdgpu_bo_alloc(device_handle, &req, &buf_handle);
-	CU_ASSERT_EQUAL(r, 0);
-
-	r = amdgpu_va_range_alloc(device_handle,
-				  amdgpu_gpu_va_range_general,
-				  4096, 1, 0, &va,
-				  &va_handle, 0);
-	CU_ASSERT_EQUAL(r, 0);
-
-	r = amdgpu_bo_va_op(buf_handle, 0, 4096, va, 0, AMDGPU_VA_OP_MAP);
-	CU_ASSERT_EQUAL(r, 0);
-
-	r = amdgpu_bo_cpu_map(buf_handle, &msg);
-	CU_ASSERT_EQUAL(r, 0);
-
-	memcpy(msg, uvd_create_msg, sizeof(uvd_create_msg));
-
-	if (family_id >= AMDGPU_FAMILY_VI) {
-		((uint8_t*)msg)[0x10] = 7;
-		/* chip beyond polaris 10/11 */
-		if ((family_id == AMDGPU_FAMILY_AI) ||
-		    (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A ||
-		     chip_id == chip_rev+0x64)) {
-			/* dpb size */
-			((uint8_t*)msg)[0x28] = 0x00;
-			((uint8_t*)msg)[0x29] = 0x94;
-			((uint8_t*)msg)[0x2A] = 0x6B;
-			((uint8_t*)msg)[0x2B] = 0x00;
-		}
-	}
-
-	r = amdgpu_bo_cpu_unmap(buf_handle);
-	CU_ASSERT_EQUAL(r, 0);
-
-	num_resources = 0;
-	resources[num_resources++] = buf_handle;
-	resources[num_resources++] = ib_handle;
-
-	i = 0;
-	uvd_cmd(va, 0x0, &i);
-	for (; i % 16; ++i)
-		ib_cpu[i] = 0x80000000;
-
-	r = submit(i, AMDGPU_HW_IP_UVD);
-	CU_ASSERT_EQUAL(r, 0);
-
-	r = amdgpu_bo_va_op(buf_handle, 0, 4096, va, 0, AMDGPU_VA_OP_UNMAP);
-	CU_ASSERT_EQUAL(r, 0);
-
-	r = amdgpu_va_range_free(va_handle);
-	CU_ASSERT_EQUAL(r, 0);
-
-	r = amdgpu_bo_free(buf_handle);
-	CU_ASSERT_EQUAL(r, 0);
-}
-
-static void amdgpu_cs_uvd_decode(void)
-{
-	const unsigned dpb_size = 15923584, dt_size = 737280;
-	uint64_t msg_addr, fb_addr, bs_addr, dpb_addr, ctx_addr, dt_addr, it_addr;
-	struct amdgpu_bo_alloc_request req = {0};
-	amdgpu_bo_handle buf_handle;
-	amdgpu_va_handle va_handle;
-	uint64_t va = 0;
-	uint64_t sum;
-	uint8_t *ptr;
-	int i, r;
-
-	req.alloc_size = 4*1024; /* msg */
-	req.alloc_size += 4*1024; /* fb */
-	if (family_id >= AMDGPU_FAMILY_VI)
-		req.alloc_size += 4096; /*it_scaling_table*/
-	req.alloc_size += ALIGN(sizeof(uvd_bitstream), 4*1024);
-	req.alloc_size += ALIGN(dpb_size, 4*1024);
-	req.alloc_size += ALIGN(dt_size, 4*1024);
-
-	req.preferred_heap = AMDGPU_GEM_DOMAIN_GTT;
-
-	r = amdgpu_bo_alloc(device_handle, &req, &buf_handle);
-	CU_ASSERT_EQUAL(r, 0);
-
-	r = amdgpu_va_range_alloc(device_handle,
-				  amdgpu_gpu_va_range_general,
-				  req.alloc_size, 1, 0, &va,
-				  &va_handle, 0);
-	CU_ASSERT_EQUAL(r, 0);
-
-	r = amdgpu_bo_va_op(buf_handle, 0, req.alloc_size, va, 0,
-			    AMDGPU_VA_OP_MAP);
-	CU_ASSERT_EQUAL(r, 0);
-
-	r = amdgpu_bo_cpu_map(buf_handle, (void **)&ptr);
-	CU_ASSERT_EQUAL(r, 0);
-
-	memcpy(ptr, uvd_decode_msg, sizeof(uvd_decode_msg));
-	memcpy(ptr + sizeof(uvd_decode_msg), avc_decode_msg, sizeof(avc_decode_msg));
-
-	if (family_id >= AMDGPU_FAMILY_VI) {
-		ptr[0x10] = 7;
-		ptr[0x98] = 0x00;
-		ptr[0x99] = 0x02;
-		/* chip beyond polaris10/11 */
-		if ((family_id == AMDGPU_FAMILY_AI) ||
-		    (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A ||
-		     chip_id == chip_rev+0x64)) {
-			/* dpb size */
-			ptr[0x24] = 0x00;
-			ptr[0x25] = 0x94;
-			ptr[0x26] = 0x6B;
-			ptr[0x27] = 0x00;
-			/*ctx size */
-			ptr[0x2C] = 0x00;
-			ptr[0x2D] = 0xAF;
-			ptr[0x2E] = 0x50;
-			ptr[0x2F] = 0x00;
-		}
-	}
-
-	ptr += 4*1024;
-	memset(ptr, 0, 4*1024);
-	if (family_id >= AMDGPU_FAMILY_VI) {
-		ptr += 4*1024;
-		memcpy(ptr, uvd_it_scaling_table, sizeof(uvd_it_scaling_table));
-	}
-
-	ptr += 4*1024;
-	memcpy(ptr, uvd_bitstream, sizeof(uvd_bitstream));
-
-	ptr += ALIGN(sizeof(uvd_bitstream), 4*1024);
-	memset(ptr, 0, dpb_size);
-
-	ptr += ALIGN(dpb_size, 4*1024);
-	memset(ptr, 0, dt_size);
-
-	num_resources = 0;
-	resources[num_resources++] = buf_handle;
-	resources[num_resources++] = ib_handle;
-
-	msg_addr = va;
-	fb_addr = msg_addr + 4*1024;
-	if (family_id >= AMDGPU_FAMILY_VI) {
-		it_addr = fb_addr + 4*1024;
-		bs_addr = it_addr + 4*1024;
-	} else
-		bs_addr = fb_addr + 4*1024;
-	dpb_addr = ALIGN(bs_addr + sizeof(uvd_bitstream), 4*1024);
-
-	ctx_addr = 0;
-	if (family_id >= AMDGPU_FAMILY_VI) {
-		if ((family_id == AMDGPU_FAMILY_AI) ||
-		    (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A ||
-		     chip_id == chip_rev+0x64)) {
-			ctx_addr = ALIGN(dpb_addr + 0x006B9400, 4*1024);
-		}
-	}
-
-	dt_addr = ALIGN(dpb_addr + dpb_size, 4*1024);
-
-	i = 0;
-	uvd_cmd(msg_addr, 0x0, &i);
-	uvd_cmd(dpb_addr, 0x1, &i);
-	uvd_cmd(dt_addr, 0x2, &i);
-	uvd_cmd(fb_addr, 0x3, &i);
-	uvd_cmd(bs_addr, 0x100, &i);
-
-	if (family_id >= AMDGPU_FAMILY_VI) {
-		uvd_cmd(it_addr, 0x204, &i);
-		if ((family_id == AMDGPU_FAMILY_AI) ||
-		    (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A ||
-		     chip_id == chip_rev+0x64))
-			uvd_cmd(ctx_addr, 0x206, &i);
-	}
-
-	ib_cpu[i++] = (family_id < AMDGPU_FAMILY_AI) ? 0x3BC6 : 0x81C6;
-	ib_cpu[i++] = 0x1;
-	for (; i % 16; ++i)
-		ib_cpu[i] = 0x80000000;
-
-	r = submit(i, AMDGPU_HW_IP_UVD);
-	CU_ASSERT_EQUAL(r, 0);
-
-	/* TODO: use a real CRC32 */
-	for (i = 0, sum = 0; i < dt_size; ++i)
-		sum += ptr[i];
-	CU_ASSERT_EQUAL(sum, SUM_DECODE);
-
-	r = amdgpu_bo_cpu_unmap(buf_handle);
-	CU_ASSERT_EQUAL(r, 0);
-
-	r = amdgpu_bo_va_op(buf_handle, 0, req.alloc_size, va, 0, AMDGPU_VA_OP_UNMAP);
-	CU_ASSERT_EQUAL(r, 0);
-
-	r = amdgpu_va_range_free(va_handle);
-	CU_ASSERT_EQUAL(r, 0);
-
-	r = amdgpu_bo_free(buf_handle);
-	CU_ASSERT_EQUAL(r, 0);
-}
-
-static void amdgpu_cs_uvd_destroy(void)
-{
-	struct amdgpu_bo_alloc_request req = {0};
-	amdgpu_bo_handle buf_handle;
-	amdgpu_va_handle va_handle;
-	uint64_t va = 0;
-	void *msg;
-	int i, r;
-
-	req.alloc_size = 4*1024;
-	req.preferred_heap = AMDGPU_GEM_DOMAIN_GTT;
-
-	r = amdgpu_bo_alloc(device_handle, &req, &buf_handle);
-	CU_ASSERT_EQUAL(r, 0);
-
-	r = amdgpu_va_range_alloc(device_handle,
-				  amdgpu_gpu_va_range_general,
-				  req.alloc_size, 1, 0, &va,
-				  &va_handle, 0);
-	CU_ASSERT_EQUAL(r, 0);
-
-	r = amdgpu_bo_va_op(buf_handle, 0, req.alloc_size, va, 0,
-			    AMDGPU_VA_OP_MAP);
-	CU_ASSERT_EQUAL(r, 0);
-
-	r = amdgpu_bo_cpu_map(buf_handle, &msg);
-	CU_ASSERT_EQUAL(r, 0);
-
-	memcpy(msg, uvd_destroy_msg, sizeof(uvd_destroy_msg));
-	if (family_id >= AMDGPU_FAMILY_VI)
-		((uint8_t*)msg)[0x10] = 7;
-
-	r = amdgpu_bo_cpu_unmap(buf_handle);
-	CU_ASSERT_EQUAL(r, 0);
-
-	num_resources = 0;
-	resources[num_resources++] = buf_handle;
-	resources[num_resources++] = ib_handle;
-
-	i = 0;
-	uvd_cmd(va, 0x0, &i);
-	for (; i % 16; ++i)
-		ib_cpu[i] = 0x80000000;
-
-	r = submit(i, AMDGPU_HW_IP_UVD);
-	CU_ASSERT_EQUAL(r, 0);
-
-	r = amdgpu_bo_va_op(buf_handle, 0, req.alloc_size, va, 0, AMDGPU_VA_OP_UNMAP);
-	CU_ASSERT_EQUAL(r, 0);
-
-	r = amdgpu_va_range_free(va_handle);
-	CU_ASSERT_EQUAL(r, 0);
-
-	r = amdgpu_bo_free(buf_handle);
-	CU_ASSERT_EQUAL(r, 0);
-}

tests/amdgpu/deadlock_tests.c

@@ -1,696 +0,0 @@
-/*
- * Copyright 2017 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
-*/
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <unistd.h>
-#if HAVE_ALLOCA_H
-# include <alloca.h>
-#endif
-
-#include "CUnit/Basic.h"
-
-#include "amdgpu_test.h"
-#include "amdgpu_drm.h"
-#include "amdgpu_internal.h"
-
-#include <pthread.h>
-
-
-/*
- * This defines the delay in MS after which memory location designated for
- * compression against reference value is written to, unblocking command
- * processor
- */
-#define WRITE_MEM_ADDRESS_DELAY_MS 100
-
-#define	PACKET_TYPE3	3
-
-#define PACKET3(op, n)	((PACKET_TYPE3 << 30) |				\
-			 (((op) & 0xFF) << 8) |				\
-			 ((n) & 0x3FFF) << 16)
-
-#define	PACKET3_WAIT_REG_MEM				0x3C
-#define		WAIT_REG_MEM_FUNCTION(x)                ((x) << 0)
-		/* 0 - always
-		 * 1 - <
-		 * 2 - <=
-		 * 3 - ==
-		 * 4 - !=
-		 * 5 - >=
-		 * 6 - >
-		 */
-#define		WAIT_REG_MEM_MEM_SPACE(x)               ((x) << 4)
-		/* 0 - reg
-		 * 1 - mem
-		 */
-#define		WAIT_REG_MEM_OPERATION(x)               ((x) << 6)
-		/* 0 - wait_reg_mem
-		 * 1 - wr_wait_wr_reg
-		 */
-#define		WAIT_REG_MEM_ENGINE(x)                  ((x) << 8)
-		/* 0 - me
-		 * 1 - pfp
-		 */
-
-#define	PACKET3_WRITE_DATA				0x37
-#define		WRITE_DATA_DST_SEL(x)                   ((x) << 8)
-		/* 0 - register
-		 * 1 - memory (sync - via GRBM)
-		 * 2 - gl2
-		 * 3 - gds
-		 * 4 - reserved
-		 * 5 - memory (async - direct)
-		 */
-#define		WR_ONE_ADDR                             (1 << 16)
-#define		WR_CONFIRM                              (1 << 20)
-#define		WRITE_DATA_CACHE_POLICY(x)              ((x) << 25)
-		/* 0 - LRU
-		 * 1 - Stream
-		 */
-#define		WRITE_DATA_ENGINE_SEL(x)                ((x) << 30)
-		/* 0 - me
-		 * 1 - pfp
-		 * 2 - ce
-		 */
-
-#define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR                                      0x54f
-
-#define SDMA_PKT_HEADER_OP(x)	(x & 0xff)
-#define SDMA_OP_POLL_REGMEM  8
-
-static  amdgpu_device_handle device_handle;
-static  uint32_t  major_version;
-static  uint32_t  minor_version;
-
-static pthread_t stress_thread;
-static uint32_t *ptr;
-
-static uint32_t family_id;
-static uint32_t chip_rev;
-static uint32_t chip_id;
-
-int use_uc_mtype = 0;
-
-static void amdgpu_deadlock_helper(unsigned ip_type);
-static void amdgpu_deadlock_gfx(void);
-static void amdgpu_deadlock_compute(void);
-static void amdgpu_illegal_reg_access();
-static void amdgpu_illegal_mem_access();
-static void amdgpu_deadlock_sdma(void);
-static void amdgpu_dispatch_hang_gfx(void);
-static void amdgpu_dispatch_hang_compute(void);
-static void amdgpu_dispatch_hang_slow_gfx(void);
-static void amdgpu_dispatch_hang_slow_compute(void);
-static void amdgpu_draw_hang_gfx(void);
-static void amdgpu_draw_hang_slow_gfx(void);
-static void amdgpu_hang_sdma(void);
-static void amdgpu_hang_slow_sdma(void);
-
-CU_BOOL suite_deadlock_tests_enable(void)
-{
-	CU_BOOL enable = CU_TRUE;
-
-	if (amdgpu_device_initialize(drm_amdgpu[0], &major_version,
-					     &minor_version, &device_handle))
-		return CU_FALSE;
-
-	family_id = device_handle->info.family_id;
-	chip_id = device_handle->info.chip_external_rev;
-	chip_rev = device_handle->info.chip_rev;
-
-	/*
-	 * Only enable for ASICs supporting GPU reset and for which it's enabled
-	 * by default (currently GFX8+ dGPUS and gfx9+ APUs).  Note that Raven1
-	 * did not support GPU reset, but newer variants do.
-	 */
-	if (family_id == AMDGPU_FAMILY_SI ||
-	    family_id == AMDGPU_FAMILY_KV ||
-	    family_id == AMDGPU_FAMILY_CZ ||
-	    family_id == AMDGPU_FAMILY_RV) {
-		printf("\n\nGPU reset is not enabled for the ASIC, deadlock suite disabled\n");
-		enable = CU_FALSE;
-	}
-
-	if (asic_is_gfx_pipe_removed(family_id, chip_id, chip_rev)) {
-		if (amdgpu_set_test_active("Deadlock Tests",
-					"gfx ring block test (set amdgpu.lockup_timeout=50)",
-					CU_FALSE))
-			fprintf(stderr, "test deactivation failed - %s\n",
-				CU_get_error_msg());
-	}
-
-	if (device_handle->info.family_id >= AMDGPU_FAMILY_AI)
-		use_uc_mtype = 1;
-
-	if (amdgpu_device_deinitialize(device_handle))
-		return CU_FALSE;
-
-	return enable;
-}
-
-int suite_deadlock_tests_init(void)
-{
-	int r;
-
-	r = amdgpu_device_initialize(drm_amdgpu[0], &major_version,
-				   &minor_version, &device_handle);
-
-	if (r) {
-		if ((r == -EACCES) && (errno == EACCES))
-			printf("\n\nError:%s. "
-				"Hint:Try to run this test program as root.",
-				strerror(errno));
-		return CUE_SINIT_FAILED;
-	}
-
-	return CUE_SUCCESS;
-}
-
-int suite_deadlock_tests_clean(void)
-{
-	int r = amdgpu_device_deinitialize(device_handle);
-
-	if (r == 0)
-		return CUE_SUCCESS;
-	else
-		return CUE_SCLEAN_FAILED;
-}
-
-
-CU_TestInfo deadlock_tests[] = {
-	{ "gfx ring block test (set amdgpu.lockup_timeout=50)", amdgpu_deadlock_gfx },
-	{ "compute ring block test (set amdgpu.lockup_timeout=50)", amdgpu_deadlock_compute },
-	{ "sdma ring block test (set amdgpu.lockup_timeout=50)", amdgpu_deadlock_sdma },
-	{ "illegal reg access test", amdgpu_illegal_reg_access },
-	{ "illegal mem access test (set amdgpu.vm_fault_stop=2)", amdgpu_illegal_mem_access },
-	{ "gfx ring bad dispatch test (set amdgpu.lockup_timeout=50)", amdgpu_dispatch_hang_gfx },
-	{ "compute ring bad dispatch test (set amdgpu.lockup_timeout=50,50)", amdgpu_dispatch_hang_compute },
-	{ "gfx ring bad slow dispatch test (set amdgpu.lockup_timeout=50)", amdgpu_dispatch_hang_slow_gfx },
-	{ "compute ring bad slow dispatch test (set amdgpu.lockup_timeout=50,50)", amdgpu_dispatch_hang_slow_compute },
-	{ "gfx ring bad draw test (set amdgpu.lockup_timeout=50)", amdgpu_draw_hang_gfx },
-	{ "gfx ring slow bad draw test (set amdgpu.lockup_timeout=50)", amdgpu_draw_hang_slow_gfx },
-	{ "sdma ring corrupted header test (set amdgpu.lockup_timeout=50)", amdgpu_hang_sdma },
-	{ "sdma ring slow linear copy test (set amdgpu.lockup_timeout=50)", amdgpu_hang_slow_sdma },
-	CU_TEST_INFO_NULL,
-};
-
-static void *write_mem_address(void *data)
-{
-	int i;
-
-	/* useconds_t range is [0, 1,000,000] so use loop for waits > 1s */
-	for (i = 0; i < WRITE_MEM_ADDRESS_DELAY_MS; i++)
-		usleep(1000);
-
-	ptr[256] = 0x1;
-
-	return 0;
-}
-
-static void amdgpu_deadlock_gfx(void)
-{
-	amdgpu_deadlock_helper(AMDGPU_HW_IP_GFX);
-}
-
-static void amdgpu_deadlock_compute(void)
-{
-	amdgpu_deadlock_helper(AMDGPU_HW_IP_COMPUTE);
-}
-
-static void amdgpu_deadlock_helper(unsigned ip_type)
-{
-	amdgpu_context_handle context_handle;
-	amdgpu_bo_handle ib_result_handle;
-	void *ib_result_cpu;
-	uint64_t ib_result_mc_address;
-	struct amdgpu_cs_request ibs_request;
-	struct amdgpu_cs_ib_info ib_info;
-	struct amdgpu_cs_fence fence_status;
-	uint32_t expired;
-	int i, r;
-	amdgpu_bo_list_handle bo_list;
-	amdgpu_va_handle va_handle;
-
-	r = pthread_create(&stress_thread, NULL, write_mem_address, NULL);
-	CU_ASSERT_EQUAL(r, 0);
-
-	r = amdgpu_cs_ctx_create(device_handle, &context_handle);
-	CU_ASSERT_EQUAL(r, 0);
-
-	r = amdgpu_bo_alloc_and_map_raw(device_handle, 4096, 4096,
-			AMDGPU_GEM_DOMAIN_GTT, 0, use_uc_mtype ? AMDGPU_VM_MTYPE_UC : 0,
-						    &ib_result_handle, &ib_result_cpu,
-						    &ib_result_mc_address, &va_handle);
-	CU_ASSERT_EQUAL(r, 0);
-
-	r = amdgpu_get_bo_list(device_handle, ib_result_handle, NULL,
-			       &bo_list);
-	CU_ASSERT_EQUAL(r, 0);
-
-	ptr = ib_result_cpu;
-
-	ptr[0] = PACKET3(PACKET3_WAIT_REG_MEM, 5);
-	ptr[1] = (WAIT_REG_MEM_MEM_SPACE(1) | /* memory */
-			 WAIT_REG_MEM_FUNCTION(4) | /* != */
-			 WAIT_REG_MEM_ENGINE(0));  /* me */
-	ptr[2] = (ib_result_mc_address + 256*4) & 0xfffffffc;
-	ptr[3] = ((ib_result_mc_address + 256*4) >> 32) & 0xffffffff;
-	ptr[4] = 0x00000000; /* reference value */
-	ptr[5] = 0xffffffff; /* and mask */
-	ptr[6] = 0x00000004; /* poll interval */
-
-	for (i = 7; i < 16; ++i)
-		ptr[i] = 0xffff1000;
-
-
-	ptr[256] = 0x0; /* the memory we wait on to change */
-
-
-
-	memset(&ib_info, 0, sizeof(struct amdgpu_cs_ib_info));
-	ib_info.ib_mc_address = ib_result_mc_address;
-	ib_info.size = 16;
-
-	memset(&ibs_request, 0, sizeof(struct amdgpu_cs_request));
-	ibs_request.ip_type = ip_type;
-	ibs_request.ring = 0;
-	ibs_request.number_of_ibs = 1;
-	ibs_request.ibs = &ib_info;
-	ibs_request.resources = bo_list;
-	ibs_request.fence_info.handle = NULL;
-	for (i = 0; i < 200; i++) {
-		r = amdgpu_cs_submit(context_handle, 0,&ibs_request, 1);
-		CU_ASSERT_EQUAL((r == 0 || r == -ECANCELED), 1);
-
-	}
-
-	memset(&fence_status, 0, sizeof(struct amdgpu_cs_fence));
-	fence_status.context = context_handle;
-	fence_status.ip_type = ip_type;
-	fence_status.ip_instance = 0;
-	fence_status.ring = 0;
-	fence_status.fence = ibs_request.seq_no;
-
-	r = amdgpu_cs_query_fence_status(&fence_status,
-			AMDGPU_TIMEOUT_INFINITE,0, &expired);
-	CU_ASSERT_EQUAL((r == 0 || r == -ECANCELED), 1);
-
-	pthread_join(stress_thread, NULL);
-
-	r = amdgpu_bo_list_destroy(bo_list);
-	CU_ASSERT_EQUAL(r, 0);
-
-	r = amdgpu_bo_unmap_and_free(ib_result_handle, va_handle,
-				     ib_result_mc_address, 4096);
-	CU_ASSERT_EQUAL(r, 0);
-
-	r = amdgpu_cs_ctx_free(context_handle);
-	CU_ASSERT_EQUAL(r, 0);
-}
-
-static void amdgpu_deadlock_sdma(void)
-{
-	amdgpu_context_handle context_handle;
-	amdgpu_bo_handle ib_result_handle;
-	void *ib_result_cpu;
-	uint64_t ib_result_mc_address;
-	struct amdgpu_cs_request ibs_request;
-	struct amdgpu_cs_ib_info ib_info;
-	struct amdgpu_cs_fence fence_status;
-	uint32_t expired;
-	int i, r;
-	amdgpu_bo_list_handle bo_list;
-	amdgpu_va_handle va_handle;
-	struct drm_amdgpu_info_hw_ip info;
-	uint32_t ring_id;
-
-	r = amdgpu_query_hw_ip_info(device_handle, AMDGPU_HW_IP_DMA, 0, &info);
-	CU_ASSERT_EQUAL(r, 0);
-
-	r = amdgpu_cs_ctx_create(device_handle, &context_handle);
-	CU_ASSERT_EQUAL(r, 0);
-
-	for (ring_id = 0; (1 << ring_id) & info.available_rings; ring_id++) {
-		r = pthread_create(&stress_thread, NULL, write_mem_address, NULL);
-		CU_ASSERT_EQUAL(r, 0);
-
-		r = amdgpu_bo_alloc_and_map_raw(device_handle, 4096, 4096,
-				AMDGPU_GEM_DOMAIN_GTT, 0, use_uc_mtype ? AMDGPU_VM_MTYPE_UC : 0,
-							    &ib_result_handle, &ib_result_cpu,
-							    &ib_result_mc_address, &va_handle);
-		CU_ASSERT_EQUAL(r, 0);
-
-		r = amdgpu_get_bo_list(device_handle, ib_result_handle, NULL,
-				       &bo_list);
-		CU_ASSERT_EQUAL(r, 0);
-
-		ptr = ib_result_cpu;
-		i = 0;
-
-		ptr[i++] = SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
-				(0 << 26) | /* WAIT_REG_MEM */
-				(4 << 28) | /* != */
-				(1 << 31); /* memory */
-		ptr[i++] = (ib_result_mc_address + 256*4) & 0xfffffffc;
-		ptr[i++] = ((ib_result_mc_address + 256*4) >> 32) & 0xffffffff;
-		ptr[i++] = 0x00000000; /* reference value */
-		ptr[i++] = 0xffffffff; /* and mask */
-		ptr[i++] =  4 | /* poll interval */
-				(0xfff << 16); /* retry count */
-
-		for (; i < 16; i++)
-			ptr[i] = 0;
-
-		ptr[256] = 0x0; /* the memory we wait on to change */
-
-		memset(&ib_info, 0, sizeof(struct amdgpu_cs_ib_info));
-		ib_info.ib_mc_address = ib_result_mc_address;
-		ib_info.size = 16;
-
-		memset(&ibs_request, 0, sizeof(struct amdgpu_cs_request));
-		ibs_request.ip_type = AMDGPU_HW_IP_DMA;
-		ibs_request.ring = ring_id;
-		ibs_request.number_of_ibs = 1;
-		ibs_request.ibs = &ib_info;
-		ibs_request.resources = bo_list;
-		ibs_request.fence_info.handle = NULL;
-
-		for (i = 0; i < 200; i++) {
-			r = amdgpu_cs_submit(context_handle, 0,&ibs_request, 1);
-			CU_ASSERT_EQUAL((r == 0 || r == -ECANCELED), 1);
-
-		}
-
-		memset(&fence_status, 0, sizeof(struct amdgpu_cs_fence));
-		fence_status.context = context_handle;
-		fence_status.ip_type = AMDGPU_HW_IP_DMA;
-		fence_status.ip_instance = 0;
-		fence_status.ring = ring_id;
-		fence_status.fence = ibs_request.seq_no;
-
-		r = amdgpu_cs_query_fence_status(&fence_status,
-				AMDGPU_TIMEOUT_INFINITE,0, &expired);
-		CU_ASSERT_EQUAL((r == 0 || r == -ECANCELED), 1);
-
-		pthread_join(stress_thread, NULL);
-
-		r = amdgpu_bo_list_destroy(bo_list);
-		CU_ASSERT_EQUAL(r, 0);
-
-		r = amdgpu_bo_unmap_and_free(ib_result_handle, va_handle,
-					     ib_result_mc_address, 4096);
-		CU_ASSERT_EQUAL(r, 0);
-	}
-	r = amdgpu_cs_ctx_free(context_handle);
-	CU_ASSERT_EQUAL(r, 0);
-}
-
-static void bad_access_helper(int reg_access)
-{
-	amdgpu_context_handle context_handle;
-	amdgpu_bo_handle ib_result_handle;
-	void *ib_result_cpu;
-	uint64_t ib_result_mc_address;
-	struct amdgpu_cs_request ibs_request;
-	struct amdgpu_cs_ib_info ib_info;
-	struct amdgpu_cs_fence fence_status;
-	uint32_t expired;
-	int i, r;
-	amdgpu_bo_list_handle bo_list;
-	amdgpu_va_handle va_handle;
-
-	r = amdgpu_cs_ctx_create(device_handle, &context_handle);
-	CU_ASSERT_EQUAL(r, 0);
-
-	r = amdgpu_bo_alloc_and_map_raw(device_handle, 4096, 4096,
-			AMDGPU_GEM_DOMAIN_GTT, 0, 0,
-							&ib_result_handle, &ib_result_cpu,
-							&ib_result_mc_address, &va_handle);
-	CU_ASSERT_EQUAL(r, 0);
-
-	r = amdgpu_get_bo_list(device_handle, ib_result_handle, NULL,
-				   &bo_list);
-	CU_ASSERT_EQUAL(r, 0);
-
-	ptr = ib_result_cpu;
-	i = 0;
-
-	ptr[i++] = PACKET3(PACKET3_WRITE_DATA, 3);
-	ptr[i++] = (reg_access ? WRITE_DATA_DST_SEL(0) : WRITE_DATA_DST_SEL(5))| WR_CONFIRM;
-	ptr[i++] = reg_access ? mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR : 0xdeadbee0;
-	ptr[i++] = 0;
-	ptr[i++] = 0xdeadbeef;
-
-	for (; i < 16; ++i)
-		ptr[i] = 0xffff1000;
-
-	memset(&ib_info, 0, sizeof(struct amdgpu_cs_ib_info));
-	ib_info.ib_mc_address = ib_result_mc_address;
-	ib_info.size = 16;
-
-	memset(&ibs_request, 0, sizeof(struct amdgpu_cs_request));
-	ibs_request.ip_type = AMDGPU_HW_IP_GFX;
-	ibs_request.ring = 0;
-	ibs_request.number_of_ibs = 1;
-	ibs_request.ibs = &ib_info;
-	ibs_request.resources = bo_list;
-	ibs_request.fence_info.handle = NULL;
-
-	r = amdgpu_cs_submit(context_handle, 0,&ibs_request, 1);
-	CU_ASSERT_EQUAL((r == 0 || r == -ECANCELED), 1);
-
-
-	memset(&fence_status, 0, sizeof(struct amdgpu_cs_fence));
-	fence_status.context = context_handle;
-	fence_status.ip_type = AMDGPU_HW_IP_GFX;
-	fence_status.ip_instance = 0;
-	fence_status.ring = 0;
-	fence_status.fence = ibs_request.seq_no;
-
-	r = amdgpu_cs_query_fence_status(&fence_status,
-			AMDGPU_TIMEOUT_INFINITE,0, &expired);
-	CU_ASSERT_EQUAL((r == 0 || r == -ECANCELED), 1);
-
-	r = amdgpu_bo_list_destroy(bo_list);
-	CU_ASSERT_EQUAL(r, 0);
-
-	r = amdgpu_bo_unmap_and_free(ib_result_handle, va_handle,
-					 ib_result_mc_address, 4096);
-	CU_ASSERT_EQUAL(r, 0);
-
-	r = amdgpu_cs_ctx_free(context_handle);
-	CU_ASSERT_EQUAL(r, 0);
-}
-
-static void amdgpu_illegal_reg_access()
-{
-	bad_access_helper(1);
-}
-
-static void amdgpu_illegal_mem_access()
-{
-	bad_access_helper(0);
-}
-
-static void amdgpu_dispatch_hang_gfx(void)
-{
-	amdgpu_test_dispatch_hang_helper(device_handle, AMDGPU_HW_IP_GFX);
-}
-static void amdgpu_dispatch_hang_compute(void)
-{
-	amdgpu_test_dispatch_hang_helper(device_handle, AMDGPU_HW_IP_COMPUTE);
-}
-static void amdgpu_dispatch_hang_slow_gfx(void)
-{
-	amdgpu_test_dispatch_hang_slow_helper(device_handle, AMDGPU_HW_IP_GFX);
-}
-static void amdgpu_dispatch_hang_slow_compute(void)
-{
-	amdgpu_test_dispatch_hang_slow_helper(device_handle, AMDGPU_HW_IP_COMPUTE);
-}
-static void amdgpu_draw_hang_gfx(void)
-{
-	amdgpu_test_draw_hang_helper(device_handle);
-}
-static void amdgpu_draw_hang_slow_gfx(void)
-{
-	amdgpu_test_draw_hang_slow_helper(device_handle);
-}
-
-#define DMA_CORRUPTED_HEADER_HANG	1
-#define DMA_SLOW_LINEARCOPY_HANG	2
-
-static void amdgpu_hang_sdma_helper(unsigned hang_type)
-{
-	const int sdma_write_length = 1024;
-	amdgpu_context_handle context_handle;
-	amdgpu_bo_handle ib_result_handle;
-	amdgpu_bo_handle bo1, bo2;
-	amdgpu_bo_handle resources[3];
-	amdgpu_bo_list_handle bo_list;
-	void *ib_result_cpu;
-	struct amdgpu_cs_ib_info ib_info;
-	struct amdgpu_cs_request ibs_request;
-	struct amdgpu_cs_fence fence_status;
-	uint64_t bo1_mc, bo2_mc;
-	uint64_t ib_result_mc_address;
-	volatile unsigned char *bo1_cpu, *bo2_cpu;
-	amdgpu_va_handle bo1_va_handle, bo2_va_handle;
-	amdgpu_va_handle va_handle;
-	struct drm_amdgpu_info_hw_ip hw_ip_info;
-	int i, j, r;
-	uint32_t expired, ib_size;
-
-	r = amdgpu_query_hw_ip_info(device_handle, AMDGPU_HW_IP_DMA, 0, &hw_ip_info);
-	CU_ASSERT_EQUAL(r, 0);
-
-	r = amdgpu_cs_ctx_create(device_handle, &context_handle);
-	CU_ASSERT_EQUAL(r, 0);
-
-	if (hang_type == DMA_CORRUPTED_HEADER_HANG)
-		ib_size = 4096;
-	else
-		ib_size = 4096 * 0x20000;
-
-	r = amdgpu_bo_alloc_and_map(device_handle, ib_size, 4096,
-				    AMDGPU_GEM_DOMAIN_GTT, 0,
-				    &ib_result_handle, &ib_result_cpu,
-				    &ib_result_mc_address, &va_handle);
-	CU_ASSERT_EQUAL(r, 0);
-
-	r = amdgpu_bo_alloc_and_map(device_handle,
-				    sdma_write_length, 4096,
-				    AMDGPU_GEM_DOMAIN_GTT,
-				    0, &bo1,
-				    (void**)&bo1_cpu, &bo1_mc,
-				    &bo1_va_handle);
-	CU_ASSERT_EQUAL(r, 0);
-
-	/* set bo1 */
-	memset((void*)bo1_cpu, 0xaa, sdma_write_length);
-
-	/* allocate UC bo2 for sDMA use */
-	r = amdgpu_bo_alloc_and_map(device_handle,
-				    sdma_write_length, 4096,
-				    AMDGPU_GEM_DOMAIN_GTT,
-				    0, &bo2,
-				    (void**)&bo2_cpu, &bo2_mc,
-				    &bo2_va_handle);
-	CU_ASSERT_EQUAL(r, 0);
-
-	/* clear bo2 */
-	memset((void*)bo2_cpu, 0, sdma_write_length);
-
-	resources[0] = bo1;
-	resources[1] = bo2;
-	resources[2] = ib_result_handle;
-	r = amdgpu_bo_list_create(device_handle, 3,
-				  resources, NULL, &bo_list);
-
-	/* fulfill PM4: with bad copy linear header */
-	ptr = ib_result_cpu;
-	i = 0;
-	if (hang_type == DMA_CORRUPTED_HEADER_HANG) {
-		ptr[i++] = 0x23decd3d;
-		ptr[i++] = sdma_write_length - 1;
-		ptr[i++] = 0;
-		ptr[i++] = 0xffffffff & bo1_mc;
-		ptr[i++] = (0xffffffff00000000 & bo1_mc) >> 32;
-		ptr[i++] = 0xffffffff & bo2_mc;
-		ptr[i++] = (0xffffffff00000000 & bo2_mc) >> 32;
-	} else {
-		for (j = 1; j < 0x20000; j++) {
-			ptr[i++] = 0x1;
-			ptr[i++] = sdma_write_length - 1;
-			ptr[i++] = 0;
-			ptr[i++] = 0xffffffff & bo1_mc;
-			ptr[i++] = (0xffffffff00000000 & bo1_mc) >> 32;
-			ptr[i++] = 0xffffffff & bo2_mc;
-			ptr[i++] = (0xffffffff00000000 & bo2_mc) >> 32;
-			ptr[i++] = 0x1;
-			ptr[i++] = sdma_write_length - 1;
-			ptr[i++] = 0;
-			ptr[i++] = 0xffffffff & bo2_mc;
-			ptr[i++] = (0xffffffff00000000 & bo2_mc) >> 32;
-			ptr[i++] = 0xffffffff & bo1_mc;
-			ptr[i++] = (0xffffffff00000000 & bo1_mc) >> 32;
-		}
-	}
-
-	/* exec command */
-	memset(&ib_info, 0, sizeof(struct amdgpu_cs_ib_info));
-	ib_info.ib_mc_address = ib_result_mc_address;
-	ib_info.size = i;
-
-	memset(&ibs_request, 0, sizeof(struct amdgpu_cs_request));
-	ibs_request.ip_type = AMDGPU_HW_IP_DMA;
-	ibs_request.ring = 0;
-	ibs_request.number_of_ibs = 1;
-	ibs_request.ibs = &ib_info;
-	ibs_request.resources = bo_list;
-	ibs_request.fence_info.handle = NULL;
-
-	r = amdgpu_cs_submit(context_handle, 0, &ibs_request, 1);
-	CU_ASSERT_EQUAL(r, 0);
-
-	memset(&fence_status, 0, sizeof(struct amdgpu_cs_fence));
-	fence_status.context = context_handle;
-	fence_status.ip_type = AMDGPU_HW_IP_DMA;
-	fence_status.ip_instance = 0;
-	fence_status.ring = 0;
-	fence_status.fence = ibs_request.seq_no;
-
-	r = amdgpu_cs_query_fence_status(&fence_status,
-					 AMDGPU_TIMEOUT_INFINITE,
-					 0, &expired);
-	CU_ASSERT_EQUAL((r == 0 || r == -ECANCELED), 1);
-
-	r = amdgpu_bo_list_destroy(bo_list);
-	CU_ASSERT_EQUAL(r, 0);
-
-	r = amdgpu_bo_unmap_and_free(ib_result_handle, va_handle,
-				     ib_result_mc_address, 4096);
-	CU_ASSERT_EQUAL(r, 0);
-
-	r = amdgpu_bo_unmap_and_free(bo1, bo1_va_handle, bo1_mc,
-				     sdma_write_length);
-	CU_ASSERT_EQUAL(r, 0);
-
-	r = amdgpu_bo_unmap_and_free(bo2, bo2_va_handle, bo2_mc,
-				     sdma_write_length);
-	CU_ASSERT_EQUAL(r, 0);
-
-	/* end of test */
-	r = amdgpu_cs_ctx_free(context_handle);
-	CU_ASSERT_EQUAL(r, 0);
-}
-
-static void amdgpu_hang_sdma(void)
-{
-	amdgpu_hang_sdma_helper(DMA_CORRUPTED_HEADER_HANG);
-}
-static void amdgpu_hang_slow_sdma(void)
-{
-	amdgpu_hang_sdma_helper(DMA_SLOW_LINEARCOPY_HANG);
-}

tests/amdgpu/decode_messages.h

@@ -1,881 +0,0 @@
-/*
- * Copyright 2017 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-
-#ifndef _DECODE_MESSAGES_H_
-#define _DECODE_MESSAGES_H_
-
-#define SUM_DECODE 0x20345d8
-
-static const uint8_t uvd_create_msg[] = {
-	0xe4,0x0d,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x00,0x44,0x40,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x60,0x03,0x00,0x00,
-	0xe0,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0xf9,0xf2,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
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-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-};
-
-static const uint8_t uvd_bitstream[] ={
-	0x00,0x00,0x01,0x25,0xb8,0x20,0x20,0x21,0x44,0xc5,0x00,0x01,0x57,0x9b,0xef,0xbe,
-	0xfb,0xef,0xbe,0xfb,0xef,0xbe,0xfb,0xef,0xbe,0xfb,0xef,0xbe,0xfb,0xef,0xbe,0xfb,
-	0xef,0xbe,0xfb,0xef,0xbe,0xfb,0xef,0xbe,0xfb,0xef,0xbe,0xfb,0xef,0xbe,0xfb,0xef,
-	0xbe,0xfb,0xef,0xbe,0xff,0x87,0xff,0xc2,0x58,0x0e,0x00,0x02,0x02,0xa0,0x00,0x20,
-	0x3a,0x00,0x0d,0x00,0x01,0x01,0xa4,0xcb,0x94,0x73,0xeb,0xae,0xba,0xeb,0xae,0xba,
-	0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,
-	0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,
-	0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,
-	0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,
-	0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,
-	0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,
-	0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,
-	0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,
-	0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,
-	0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,
-	0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,
-	0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,
-	0xeb,0xae,0xba,0xeb,0xaf,0x00,0x00,0x01,0x25,0x00,0xa2,0xb8,0x20,0x20,0x21,0x44,
-	0xc5,0x00,0x01,0x57,0x9b,0xef,0xbe,0xfb,0xef,0xbe,0xfb,0xef,0xbe,0xfb,0xef,0xbe,
-	0xfb,0xef,0xbe,0xfb,0xef,0xbe,0xfb,0xef,0xbe,0xfb,0xef,0xbe,0xfb,0xef,0xbe,0xfb,
-	0xef,0xbe,0xfb,0xef,0xbe,0xfb,0xef,0xbe,0xfb,0xef,0xbe,0xff,0x87,0xff,0xc2,0x58,
-	0x0e,0x00,0x02,0x02,0xa0,0x00,0x20,0x3a,0x00,0x0d,0x00,0x01,0x01,0xa4,0xcb,0x94,
-	0x73,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,
-	0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,
-	0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,
-	0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,
-	0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,
-	0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,
-	0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,
-	0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,
-	0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,
-	0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,
-	0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,
-	0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,
-	0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xaf,0x00,0x00,0x01,0x25,
-	0x00,0x51,0x2e,0x08,0x08,0x08,0x51,0x31,0x40,0x00,0x55,0xe6,0xfb,0xef,0xbe,0xfb,
-	0xef,0xbe,0xfb,0xef,0xbe,0xfb,0xef,0xbe,0xfb,0xef,0xbe,0xfb,0xef,0xbe,0xfb,0xef,
-	0xbe,0xfb,0xef,0xbe,0xfb,0xef,0xbe,0xfb,0xef,0xbe,0xfb,0xef,0xbe,0xfb,0xef,0xbe,
-	0xfb,0xef,0xbf,0xe1,0xff,0xf0,0x96,0x03,0x80,0x00,0x80,0xa8,0x00,0x08,0x0e,0x80,
-	0x03,0x40,0x00,0x40,0x69,0x32,0xe5,0x1c,0xfa,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,
-	0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,
-	0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,
-	0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,
-	0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,
-	0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,
-	0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,
-	0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,
-	0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,
-	0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,
-	0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,
-	0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,
-	0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,
-	0xae,0xba,0xeb,0xc0,0x00,0x00,0x01,0x25,0x00,0x79,0xae,0x08,0x08,0x08,0x51,0x31,
-	0x40,0x00,0x55,0xe6,0xfb,0xef,0xbe,0xfb,0xef,0xbe,0xfb,0xef,0xbe,0xfb,0xef,0xbe,
-	0xfb,0xef,0xbe,0xfb,0xef,0xbe,0xfb,0xef,0xbe,0xfb,0xef,0xbe,0xfb,0xef,0xbe,0xfb,
-	0xef,0xbe,0xfb,0xef,0xbe,0xfb,0xef,0xbe,0xfb,0xef,0xbf,0xe1,0xff,0xf0,0x96,0x03,
-	0x80,0x00,0x80,0xa8,0x00,0x08,0x0e,0x80,0x03,0x40,0x00,0x40,0x69,0x32,0xe5,0x1c,
-	0xfa,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,
-	0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,
-	0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,
-	0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,
-	0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,
-	0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,
-	0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,
-	0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,
-	0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,
-	0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,
-	0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,
-	0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,
-	0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xc0,0x00,0x00,0x01,0x25,
-	0x00,0x28,0x8b,0x82,0x02,0x02,0x14,0x4c,0x50,0x00,0x15,0x79,0xbe,0xfb,0xef,0xbe,
-	0xfb,0xef,0xbe,0xfb,0xef,0xbe,0xfb,0xef,0xbe,0xfb,0xef,0xbe,0xfb,0xef,0xbe,0xfb,
-	0xef,0xbe,0xfb,0xef,0xbe,0xfb,0xef,0xbe,0xfb,0xef,0xbe,0xfb,0xef,0xbe,0xfb,0xef,
-	0xbe,0xfb,0xef,0xf8,0x7f,0xfc,0x25,0x80,0xe0,0x00,0x20,0x2a,0x00,0x02,0x03,0xa0,
-	0x00,0xd0,0x00,0x10,0x1a,0x4c,0xb9,0x47,0x3e,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,
-	0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,
-	0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,
-	0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,
-	0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,
-	0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,
-	0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,
-	0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,
-	0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,
-	0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,
-	0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,
-	0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,
-	0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,0xeb,0xae,0xba,
-	0xeb,0xae,0xba,0xf0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-};
-
-static const uint8_t uvd_decode_msg[] = {
-	0xe4,0x0d,0x00,0x00,0x01,0x00,0x00,0x00,0x03,0x00,0x44,0x40,0x01,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x60,0x03,0x00,0x00,0xe0,0x01,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x80,0xf9,0xf2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x05,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x04,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0xc0,0x03,0x00,0x00,0x80,0x07,0x00,0x00,0x60,0x09,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-};
-
-static const uint8_t avc_decode_msg[] = {
-	0x02,0x00,0x00,0x00,0x1e,0x00,0x00,0x00,0x85,0x00,0x00,0x00,0x88,0x00,0x00,0x00,
-	0x01,0x00,0x00,0x01,0x00,0x03,0x02,0x00,0x02,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,
-	0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,
-	0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,
-	0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,
-	0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,
-	0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,
-	0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,
-	0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,
-	0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,
-	0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,
-	0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,
-	0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,
-	0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,
-	0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,
-	0x10,0x10,0x10,0x10,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
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-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
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-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
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-};
-
-static const uint8_t uvd_destroy_msg[] = {
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-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
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-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
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-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
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-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
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-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-};
-
-static const uint8_t uvd_it_scaling_table[] = {
-	0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,
-	0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,
-	0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,
-	0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,
-	0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,
-	0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,
-	0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,
-	0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,
-	0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,
-	0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,
-	0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,
-	0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,
-	0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,
-	0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,
-};
-
-static const uint8_t vcn_dec_create_msg[] = {
-	0x28,0x00,0x00,0x00,0x38,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x03,0x00,0x44,0x40,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x28,0x00,0x00,0x00,
-	0x10,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x07,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x60,0x03,0x00,0x00,0xe0,0x01,0x00,0x00,
-};
-
-static const uint8_t vcn_dec_decode_msg[] = {
-	0x28,0x00,0x00,0x00,0x90,0x06,0x00,0x00,0x02,0x00,0x00,0x00,0x01,0x00,0x00,0x00,
-	0x03,0x00,0x44,0x40,0x01,0x00,0x00,0x00,0x02,0x00,0x00,0x00,0x38,0x00,0x00,0x00,
-	0xb4,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x06,0x00,0x00,0x00,0xec,0x00,0x00,0x00,
-	0x5c,0x04,0x00,0x00,0x00,0x00,0x00,0x00,0x07,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x60,0x03,0x00,0x00,0xe0,0x01,0x00,0x00,0x80,0x05,0x00,0x00,0x00,0x94,0x6b,0x00,
-	0x96,0x4e,0x0b,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xaf,0x50,0x00,
-	0x00,0x00,0x02,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,
-	0x00,0x02,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0xc0,0x03,0x00,0x00,0x80,0x07,0x00,0x00,0x60,0x09,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-};
-
-static const uint8_t vcn_dec_destroy_msg[] = {
-	0x28,0x00,0x00,0x00,0x18,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x02,0x00,0x00,0x00,
-	0x03,0x00,0x44,0x40,0x00,0x00,0x00,0x00,
-};
-
-static const uint8_t feedback_msg[] = {
-	0x2c,0x00,0x00,0x00,0x2c,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-};
-
-static const uint8_t jpeg_bitstream[] = {
-	0xFF, 0xD8, 0xFF, 0xDB, 0x01, 0x06, 0x00, 0x08, 0x04, 0x04, 0x04, 0x04, 0x04, 0x05, 0x05, 0x05,
-	0x05, 0x05, 0x05, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06,
-	0x07, 0x07, 0x07, 0x08, 0x08, 0x08, 0x07, 0x07, 0x07, 0x06, 0x06, 0x07, 0x07, 0x08, 0x08, 0x08,
-	0x08, 0x09, 0x09, 0x09, 0x08, 0x08, 0x08, 0x08, 0x09, 0x09, 0x0A, 0x0A, 0x0A, 0x0C, 0x0C, 0x0B,
-	0x0B, 0x0E, 0x0E, 0x0E, 0x11, 0x11, 0x14, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xC4, 0x00, 0x4B, 0x00, 0x01,
-	0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x08, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x10, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xC0, 0x00, 0x11, 0x08, 0x00, 0x08, 0x00, 0x08,
-	0x03, 0x00, 0x22, 0x00, 0x01, 0x11, 0x00, 0x02, 0x11, 0x00, 0xFF, 0xDA, 0x00, 0x0C, 0x03, 0x00,
-	0x00, 0x01, 0x11, 0x02, 0x11, 0x00, 0x3F, 0x00, 0x9F, 0xC0, 0x07, 0xFF, 0xD9, 0xFF, 0xD9,
-};
-
-#endif /* _DECODE_MESSAGES_H_ */

tests/amdgpu/hotunplug_tests.c

@@ -1,447 +0,0 @@
-/*
- * Copyright 2021 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
-*/
-
-#include <stdlib.h>
-#include <unistd.h>
-#include <sys/types.h>
-#include <sys/stat.h>
-#include <fcntl.h>
-#if HAVE_ALLOCA_H
-# include <alloca.h>
-#endif
-
-#include "CUnit/Basic.h"
-
-#include "amdgpu_test.h"
-#include "amdgpu_drm.h"
-#include "amdgpu_internal.h"
-#include "xf86drm.h"
-#include <pthread.h>
-
-#define GFX_COMPUTE_NOP  0xffff1000
-
-static  amdgpu_device_handle device_handle;
-static  uint32_t  major_version;
-static  uint32_t  minor_version;
-static char *sysfs_remove = NULL;
-static bool do_cs;
-
-CU_BOOL suite_hotunplug_tests_enable(void)
-{
-	CU_BOOL enable = CU_TRUE;
-	drmDevicePtr device;
-
-	if (drmGetDevice2(drm_amdgpu[0], DRM_DEVICE_GET_PCI_REVISION, &device)) {
-		printf("\n\nGPU Failed to get DRM device PCI info!\n");
-		return CU_FALSE;
-	}
-
-	if (device->bustype != DRM_BUS_PCI) {
-		printf("\n\nGPU device is not on PCI bus!\n");
-		amdgpu_device_deinitialize(device_handle);
-		return CU_FALSE;
-	}
-
-	if (amdgpu_device_initialize(drm_amdgpu[0], &major_version,
-					     &minor_version, &device_handle))
-		return CU_FALSE;
-	
-	/* Latest tested amdgpu version to work with all the tests */
-        if (minor_version < 46)
-                enable = false;
-
-        /* skip hotplug test on APUs */
-        if(device_handle->dev_info.ids_flags & AMDGPU_IDS_FLAGS_FUSION)
-                enable = false;
-
-	if (amdgpu_device_deinitialize(device_handle))
-		return CU_FALSE;
-
-	return enable;
-}
-
-int suite_hotunplug_tests_init(void)
-{
-	/* We need to open/close device at each test manually */
-	amdgpu_close_devices();
-
-	return CUE_SUCCESS;
-}
-
-int suite_hotunplug_tests_clean(void)
-{
-
-
-	return CUE_SUCCESS;
-}
-
-static int amdgpu_hotunplug_trigger(const char *pathname)
-{
-	int fd, len;
-
-	fd = open(pathname, O_WRONLY);
-	if (fd < 0)
-		return -errno;
-
-	len = write(fd, "1", 1);
-	close(fd);
-
-	return len;
-}
-
-static int amdgpu_hotunplug_setup_test()
-{
-	int r;
-	char *tmp_str;
-
-	if (amdgpu_open_device_on_test_index(open_render_node) < 0) {
-		printf("\n\n Failed to reopen device file!\n");
-		return CUE_SINIT_FAILED;
-
-
-
-	}
-
-	r = amdgpu_device_initialize(drm_amdgpu[0], &major_version,
-				   &minor_version, &device_handle);
-
-	if (r) {
-		if ((r == -EACCES) && (errno == EACCES))
-			printf("\n\nError:%s. "
-				"Hint:Try to run this test program as root.",
-				strerror(errno));
-		return CUE_SINIT_FAILED;
-	}
-
-	tmp_str = amdgpu_get_device_from_fd(drm_amdgpu[0]);
-	if (!tmp_str){
-		printf("\n\n Device path not found!\n");
-		return  CUE_SINIT_FAILED;
-	}
-
-	sysfs_remove = realloc(tmp_str, strlen(tmp_str) * 2);
-	strcat(sysfs_remove, "/remove");
-
-	return 0;
-}
-
-static int amdgpu_hotunplug_teardown_test()
-{
-	if (amdgpu_device_deinitialize(device_handle))
-		return CUE_SCLEAN_FAILED;
-
-	amdgpu_close_devices();
-
-	if (sysfs_remove)
-		free(sysfs_remove);
-
-	return 0;
-}
-
-static inline int amdgpu_hotunplug_remove()
-{
-	return amdgpu_hotunplug_trigger(sysfs_remove);
-}
-
-static inline int amdgpu_hotunplug_rescan()
-{
-	return amdgpu_hotunplug_trigger("/sys/bus/pci/rescan");
-}
-
-static int amdgpu_cs_sync(amdgpu_context_handle context,
-			   unsigned int ip_type,
-			   int ring,
-			   unsigned int seqno)
-{
-	struct amdgpu_cs_fence fence = {
-		.context = context,
-		.ip_type = ip_type,
-		.ring = ring,
-		.fence = seqno,
-	};
-	uint32_t expired;
-
-	return  amdgpu_cs_query_fence_status(&fence,
-					   AMDGPU_TIMEOUT_INFINITE,
-					   0, &expired);
-}
-
-static void *amdgpu_nop_cs()
-{
-	amdgpu_bo_handle ib_result_handle;
-	void *ib_result_cpu;
-	uint64_t ib_result_mc_address;
-	uint32_t *ptr;
-	int i, r;
-	amdgpu_bo_list_handle bo_list;
-	amdgpu_va_handle va_handle;
-	amdgpu_context_handle context;
-	struct amdgpu_cs_request ibs_request;
-	struct amdgpu_cs_ib_info ib_info;
-
-	r = amdgpu_cs_ctx_create(device_handle, &context);
-	CU_ASSERT_EQUAL(r, 0);
-
-	r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096,
-				    AMDGPU_GEM_DOMAIN_GTT, 0,
-				    &ib_result_handle, &ib_result_cpu,
-				    &ib_result_mc_address, &va_handle);
-	CU_ASSERT_EQUAL(r, 0);
-
-	ptr = ib_result_cpu;
-	for (i = 0; i < 16; ++i)
-		ptr[i] = GFX_COMPUTE_NOP;
-
-	r = amdgpu_bo_list_create(device_handle, 1, &ib_result_handle, NULL, &bo_list);
-	CU_ASSERT_EQUAL(r, 0);
-
-	memset(&ib_info, 0, sizeof(struct amdgpu_cs_ib_info));
-	ib_info.ib_mc_address = ib_result_mc_address;
-	ib_info.size = 16;
-
-	memset(&ibs_request, 0, sizeof(struct amdgpu_cs_request));
-	ibs_request.ip_type = AMDGPU_HW_IP_GFX;
-	ibs_request.ring = 0;
-	ibs_request.number_of_ibs = 1;
-	ibs_request.ibs = &ib_info;
-	ibs_request.resources = bo_list;
-
-	while (do_cs)
-		amdgpu_cs_submit(context, 0, &ibs_request, 1);
-
-	amdgpu_cs_sync(context, AMDGPU_HW_IP_GFX, 0, ibs_request.seq_no);
-	amdgpu_bo_list_destroy(bo_list);
-	amdgpu_bo_unmap_and_free(ib_result_handle, va_handle,
-				 ib_result_mc_address, 4096);
-
-	amdgpu_cs_ctx_free(context);
-
-	return (void *)0;
-}
-
-static pthread_t* amdgpu_create_cs_thread()
-{
-	int r;
-	pthread_t *thread = malloc(sizeof(*thread));
-	if (!thread)
-		return NULL;
-
-	do_cs = true;
-
-	r = pthread_create(thread, NULL, amdgpu_nop_cs, NULL);
-	CU_ASSERT_EQUAL(r, 0);
-
-	/* Give thread enough time to start*/
-	usleep(100000);
-	return thread;
-}
-
-static void amdgpu_destroy_cs_thread(pthread_t *thread)
-{
-	void *status;
-
-	do_cs = false;
-
-	pthread_join(*thread, &status);
-	CU_ASSERT_EQUAL(status, 0);
-
-	free(thread);
-}
-
-
-static void amdgpu_hotunplug_test(bool with_cs)
-{
-	int r;
-	pthread_t *thread = NULL;
-
-	r = amdgpu_hotunplug_setup_test();
-	CU_ASSERT_EQUAL(r , 0);
-
-	if (with_cs) {
-		thread = amdgpu_create_cs_thread();
-		CU_ASSERT_NOT_EQUAL(thread, NULL);
-	}
-
-	r = amdgpu_hotunplug_remove();
-	CU_ASSERT_EQUAL(r > 0, 1);
-
-	if (with_cs)
-		amdgpu_destroy_cs_thread(thread);
-
-	r = amdgpu_hotunplug_teardown_test();
-	CU_ASSERT_EQUAL(r , 0);
-
-	r = amdgpu_hotunplug_rescan();
-	CU_ASSERT_EQUAL(r > 0, 1);
-}
-
-static void amdgpu_hotunplug_simple(void)
-{
-	amdgpu_hotunplug_test(false);
-}
-
-static void amdgpu_hotunplug_with_cs(void)
-{
-	amdgpu_hotunplug_test(true);
-}
-
-static void amdgpu_hotunplug_with_exported_bo(void)
-{
-	int r;
-	uint32_t dma_buf_fd;
-	unsigned int *ptr;
-	amdgpu_bo_handle bo_handle;
-
-	struct amdgpu_bo_alloc_request request = {
-		.alloc_size = 4096,
-		.phys_alignment = 4096,
-		.preferred_heap = AMDGPU_GEM_DOMAIN_GTT,
-		.flags = 0,
-	};
-
-	r = amdgpu_hotunplug_setup_test();
-	CU_ASSERT_EQUAL(r , 0);
-
-	amdgpu_bo_alloc(device_handle, &request, &bo_handle);
-	CU_ASSERT_EQUAL(r, 0);
-
-	r = amdgpu_bo_export(bo_handle, amdgpu_bo_handle_type_dma_buf_fd, &dma_buf_fd);
-	CU_ASSERT_EQUAL(r, 0);
-
-	ptr = mmap(NULL, 4096, PROT_READ | PROT_WRITE, MAP_SHARED, dma_buf_fd, 0);
-	CU_ASSERT_NOT_EQUAL(ptr,  MAP_FAILED);
-
-	r = amdgpu_hotunplug_remove();
-	CU_ASSERT_EQUAL(r > 0, 1);
-
-	amdgpu_bo_free(bo_handle);
-
-	r = amdgpu_hotunplug_teardown_test();
-	CU_ASSERT_EQUAL(r , 0);
-
-	*ptr = 0xdeafbeef;
-
-	munmap(ptr, 4096);
-	close (dma_buf_fd);
-
-	r = amdgpu_hotunplug_rescan();
-	CU_ASSERT_EQUAL(r > 0, 1);
-}
-
-static void amdgpu_hotunplug_with_exported_fence(void)
-{
-	amdgpu_bo_handle ib_result_handle;
-	void *ib_result_cpu;
-	uint64_t ib_result_mc_address;
-	uint32_t *ptr, sync_obj_handle, sync_obj_handle2;
-	int i, r;
-	amdgpu_bo_list_handle bo_list;
-	amdgpu_va_handle va_handle;
-	uint32_t major2, minor2;
-	amdgpu_device_handle device2;
-	amdgpu_context_handle context;
-	struct amdgpu_cs_request ibs_request;
-	struct amdgpu_cs_ib_info ib_info;
-	struct amdgpu_cs_fence fence_status = {0};
-	int shared_fd;
-
-	r = amdgpu_hotunplug_setup_test();
-	CU_ASSERT_EQUAL(r , 0);
-
-	r = amdgpu_device_initialize(drm_amdgpu[1], &major2, &minor2, &device2);
-	CU_ASSERT_EQUAL(r, 0);
-
-	r = amdgpu_cs_ctx_create(device_handle, &context);
-	CU_ASSERT_EQUAL(r, 0);
-
-	r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096,
-				    AMDGPU_GEM_DOMAIN_GTT, 0,
-				    &ib_result_handle, &ib_result_cpu,
-				    &ib_result_mc_address, &va_handle);
-	CU_ASSERT_EQUAL(r, 0);
-
-	ptr = ib_result_cpu;
-	for (i = 0; i < 16; ++i)
-		ptr[i] = GFX_COMPUTE_NOP;
-
-	r = amdgpu_bo_list_create(device_handle, 1, &ib_result_handle, NULL, &bo_list);
-	CU_ASSERT_EQUAL(r, 0);
-
-	memset(&ib_info, 0, sizeof(struct amdgpu_cs_ib_info));
-	ib_info.ib_mc_address = ib_result_mc_address;
-	ib_info.size = 16;
-
-	memset(&ibs_request, 0, sizeof(struct amdgpu_cs_request));
-	ibs_request.ip_type = AMDGPU_HW_IP_GFX;
-	ibs_request.ring = 0;
-	ibs_request.number_of_ibs = 1;
-	ibs_request.ibs = &ib_info;
-	ibs_request.resources = bo_list;
-
-	CU_ASSERT_EQUAL(amdgpu_cs_submit(context, 0, &ibs_request, 1), 0);
-
-	fence_status.context = context;
-	fence_status.ip_type = AMDGPU_HW_IP_GFX;
-	fence_status.ip_instance = 0;
-	fence_status.fence = ibs_request.seq_no;
-
-	CU_ASSERT_EQUAL(amdgpu_cs_fence_to_handle(device_handle, &fence_status,
-						AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ,
-						&sync_obj_handle),
-						0);
-
-	CU_ASSERT_EQUAL(amdgpu_cs_export_syncobj(device_handle, sync_obj_handle, &shared_fd), 0);
-
-	CU_ASSERT_EQUAL(amdgpu_cs_import_syncobj(device2, shared_fd, &sync_obj_handle2), 0);
-
-	CU_ASSERT_EQUAL(amdgpu_cs_destroy_syncobj(device_handle, sync_obj_handle), 0);
-
-	CU_ASSERT_EQUAL(amdgpu_bo_list_destroy(bo_list), 0);
-	CU_ASSERT_EQUAL(amdgpu_bo_unmap_and_free(ib_result_handle, va_handle,
-				 ib_result_mc_address, 4096), 0);
-	CU_ASSERT_EQUAL(amdgpu_cs_ctx_free(context), 0);
-
-	r = amdgpu_hotunplug_remove();
-	CU_ASSERT_EQUAL(r > 0, 1);
-
-	CU_ASSERT_EQUAL(amdgpu_cs_syncobj_wait(device2, &sync_obj_handle2, 1, 100000000, 0, NULL), 0);
-
-	CU_ASSERT_EQUAL(amdgpu_cs_destroy_syncobj(device2, sync_obj_handle2), 0);
-
-	amdgpu_device_deinitialize(device2);
-
-	r = amdgpu_hotunplug_teardown_test();
-	CU_ASSERT_EQUAL(r , 0);
-
-	r = amdgpu_hotunplug_rescan();
-	CU_ASSERT_EQUAL(r > 0, 1);
-}
-
-
-CU_TestInfo hotunplug_tests[] = {
-	{ "Unplug card and rescan the bus to plug it back", amdgpu_hotunplug_simple },
-	{ "Same as first test but with command submission", amdgpu_hotunplug_with_cs },
-	{ "Unplug with exported bo", amdgpu_hotunplug_with_exported_bo },
-	{ "Unplug with exported fence", amdgpu_hotunplug_with_exported_fence },
-	CU_TEST_INFO_NULL,
-};

tests/amdgpu/jpeg_tests.c

@@ -1,579 +0,0 @@
-/*
- * Copyright 2017 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-
-#include <inttypes.h>
-#include <stdio.h>
-
-#include "CUnit/Basic.h"
-
-#include "util_math.h"
-
-#include "amdgpu_drm.h"
-#include "amdgpu_internal.h"
-#include "amdgpu_test.h"
-#include "decode_messages.h"
-
-/* jpeg registers */
-#define mmUVD_JPEG_CNTL				0x0200
-#define mmUVD_JPEG_RB_BASE			0x0201
-#define mmUVD_JPEG_RB_WPTR			0x0202
-#define mmUVD_JPEG_RB_RPTR			0x0203
-#define mmUVD_JPEG_RB_SIZE			0x0204
-#define mmUVD_JPEG_TIER_CNTL2			0x021a
-#define mmUVD_JPEG_UV_TILING_CTRL		0x021c
-#define mmUVD_JPEG_TILING_CTRL			0x021e
-#define mmUVD_JPEG_OUTBUF_RPTR			0x0220
-#define mmUVD_JPEG_OUTBUF_WPTR			0x0221
-#define mmUVD_JPEG_PITCH			0x0222
-#define mmUVD_JPEG_INT_EN			0x0229
-#define mmUVD_JPEG_UV_PITCH			0x022b
-#define mmUVD_JPEG_INDEX			0x023e
-#define mmUVD_JPEG_DATA				0x023f
-#define mmUVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH	0x0438
-#define mmUVD_LMI_JPEG_WRITE_64BIT_BAR_LOW	0x0439
-#define mmUVD_LMI_JPEG_READ_64BIT_BAR_HIGH	0x045a
-#define mmUVD_LMI_JPEG_READ_64BIT_BAR_LOW	0x045b
-#define mmUVD_CTX_INDEX				0x0528
-#define mmUVD_CTX_DATA				0x0529
-#define mmUVD_SOFT_RESET			0x05a0
-
-#define vcnipUVD_JPEG_DEC_SOFT_RST		0x402f
-#define vcnipUVD_JRBC_IB_COND_RD_TIMER		0x408e
-#define vcnipUVD_JRBC_IB_REF_DATA		0x408f
-#define vcnipUVD_LMI_JPEG_READ_64BIT_BAR_HIGH	0x40e1
-#define vcnipUVD_LMI_JPEG_READ_64BIT_BAR_LOW	0x40e0
-#define vcnipUVD_JPEG_RB_BASE			0x4001
-#define vcnipUVD_JPEG_RB_SIZE			0x4004
-#define vcnipUVD_JPEG_RB_WPTR			0x4002
-#define vcnipUVD_JPEG_PITCH			0x401f
-#define vcnipUVD_JPEG_UV_PITCH			0x4020
-#define vcnipJPEG_DEC_ADDR_MODE			0x4027
-#define vcnipJPEG_DEC_Y_GFX10_TILING_SURFACE	0x4024
-#define vcnipJPEG_DEC_UV_GFX10_TILING_SURFACE	0x4025
-#define vcnipUVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH	0x40e3
-#define vcnipUVD_LMI_JPEG_WRITE_64BIT_BAR_LOW	0x40e2
-#define vcnipUVD_JPEG_INDEX			0x402c
-#define vcnipUVD_JPEG_DATA			0x402d
-#define vcnipUVD_JPEG_TIER_CNTL2		0x400f
-#define vcnipUVD_JPEG_OUTBUF_RPTR		0x401e
-#define vcnipUVD_JPEG_OUTBUF_CNTL		0x401c
-#define vcnipUVD_JPEG_INT_EN			0x400a
-#define vcnipUVD_JPEG_CNTL			0x4000
-#define vcnipUVD_JPEG_RB_RPTR			0x4003
-#define vcnipUVD_JPEG_OUTBUF_WPTR		0x401d
-
-
-#define RDECODE_PKT_REG_J(x)		((unsigned)(x)&0x3FFFF)
-#define RDECODE_PKT_RES_J(x)		(((unsigned)(x)&0x3F) << 18)
-#define RDECODE_PKT_COND_J(x)		(((unsigned)(x)&0xF) << 24)
-#define RDECODE_PKT_TYPE_J(x)		(((unsigned)(x)&0xF) << 28)
-#define RDECODE_PKTJ(reg, cond, type)	(RDECODE_PKT_REG_J(reg) | \
-					 RDECODE_PKT_RES_J(0) | \
-					 RDECODE_PKT_COND_J(cond) | \
-					 RDECODE_PKT_TYPE_J(type))
-
-#define UVD_BASE_INST0_SEG1		0x00007E00
-#define SOC15_REG_ADDR(reg)		(UVD_BASE_INST0_SEG1 + reg)
-
-#define COND0				0
-#define COND1				1
-#define COND3				3
-#define TYPE0				0
-#define TYPE1				1
-#define TYPE3				3
-#define JPEG_DEC_DT_PITCH		0x100
-#define JPEG_DEC_BSD_SIZE		0x180
-#define JPEG_DEC_LUMA_OFFSET		0
-#define JPEG_DEC_CHROMA_OFFSET		0x1000
-#define JPEG_DEC_SUM			4096
-#define IB_SIZE				4096
-#define MAX_RESOURCES			16
-
-struct amdgpu_jpeg_bo {
-	amdgpu_bo_handle handle;
-	amdgpu_va_handle va_handle;
-	uint64_t addr;
-	uint64_t size;
-	uint8_t *ptr;
-};
-
-static amdgpu_device_handle device_handle;
-static uint32_t major_version;
-static uint32_t minor_version;
-static uint32_t family_id;
-static uint32_t chip_rev;
-static uint32_t chip_id;
-static uint32_t asic_id;
-static uint32_t chip_rev;
-static uint32_t chip_id;
-
-static amdgpu_context_handle context_handle;
-static amdgpu_bo_handle ib_handle;
-static amdgpu_va_handle ib_va_handle;
-static uint64_t ib_mc_address;
-static uint32_t *ib_cpu;
-static uint32_t len;
-
-static amdgpu_bo_handle resources[MAX_RESOURCES];
-static unsigned num_resources;
-bool jpeg_direct_reg;
-
-static void set_reg_jpeg(unsigned reg, unsigned cond, unsigned type,
-                         uint32_t val);
-static void send_cmd_bitstream(uint64_t addr);
-static void send_cmd_target(uint64_t addr);
-static void send_cmd_bitstream_direct(uint64_t addr);
-static void send_cmd_target_direct(uint64_t addr);
-
-static void amdgpu_cs_jpeg_decode(void);
-
-CU_TestInfo jpeg_tests[] = {
-	{"JPEG decode", amdgpu_cs_jpeg_decode},
-	CU_TEST_INFO_NULL,
-};
-
-CU_BOOL suite_jpeg_tests_enable(void)
-{
-	struct drm_amdgpu_info_hw_ip info;
-	int r;
-
-	if (amdgpu_device_initialize(drm_amdgpu[0], &major_version, &minor_version,
-	                             &device_handle))
-		return CU_FALSE;
-
-	family_id = device_handle->info.family_id;
-	asic_id = device_handle->info.asic_id;
-	chip_rev = device_handle->info.chip_rev;
-	chip_id = device_handle->info.chip_external_rev;
-
-	r = amdgpu_query_hw_ip_info(device_handle, AMDGPU_HW_IP_VCN_JPEG, 0, &info);
-
-	if (amdgpu_device_deinitialize(device_handle))
-		return CU_FALSE;
-
-	if (r != 0 || !info.available_rings ||
-	        (family_id < AMDGPU_FAMILY_RV &&
-	         (family_id == AMDGPU_FAMILY_AI &&
-	          (chip_id - chip_rev) < 0x32))) { /* Arcturus */
-		printf("\n\nThe ASIC NOT support JPEG, suite disabled\n");
-		return CU_FALSE;
-	}
-
-	if (info.hw_ip_version_major == 1)
-		jpeg_direct_reg = false;
-	else if (info.hw_ip_version_major > 1 && info.hw_ip_version_major <= 4)
-		jpeg_direct_reg = true;
-	else
-		return CU_FALSE;
-
-	return CU_TRUE;
-}
-
-int suite_jpeg_tests_init(void)
-{
-	int r;
-
-	r = amdgpu_device_initialize(drm_amdgpu[0], &major_version, &minor_version,
-	                             &device_handle);
-	if (r)
-		return CUE_SINIT_FAILED;
-
-	family_id = device_handle->info.family_id;
-
-	r = amdgpu_cs_ctx_create(device_handle, &context_handle);
-	if (r)
-		return CUE_SINIT_FAILED;
-
-	r = amdgpu_bo_alloc_and_map(device_handle, IB_SIZE, 4096,
-	                            AMDGPU_GEM_DOMAIN_GTT, 0, &ib_handle,
-	                            (void **)&ib_cpu, &ib_mc_address, &ib_va_handle);
-	if (r)
-		return CUE_SINIT_FAILED;
-
-	return CUE_SUCCESS;
-}
-
-int suite_jpeg_tests_clean(void)
-{
-	int r;
-
-	r = amdgpu_bo_unmap_and_free(ib_handle, ib_va_handle, ib_mc_address, IB_SIZE);
-	if (r)
-		return CUE_SCLEAN_FAILED;
-
-	r = amdgpu_cs_ctx_free(context_handle);
-	if (r)
-		return CUE_SCLEAN_FAILED;
-
-	r = amdgpu_device_deinitialize(device_handle);
-	if (r)
-		return CUE_SCLEAN_FAILED;
-
-	return CUE_SUCCESS;
-}
-
-static int submit(unsigned ndw, unsigned ip)
-{
-	struct amdgpu_cs_request ibs_request = {0};
-	struct amdgpu_cs_ib_info ib_info = {0};
-	struct amdgpu_cs_fence fence_status = {0};
-	uint32_t expired;
-	int r;
-
-	ib_info.ib_mc_address = ib_mc_address;
-	ib_info.size = ndw;
-
-	ibs_request.ip_type = ip;
-
-	r = amdgpu_bo_list_create(device_handle, num_resources, resources, NULL,
-	                          &ibs_request.resources);
-	if (r)
-		return r;
-
-	ibs_request.number_of_ibs = 1;
-	ibs_request.ibs = &ib_info;
-	ibs_request.fence_info.handle = NULL;
-
-	r = amdgpu_cs_submit(context_handle, 0, &ibs_request, 1);
-	if (r)
-		return r;
-
-	r = amdgpu_bo_list_destroy(ibs_request.resources);
-	if (r)
-		return r;
-
-	fence_status.context = context_handle;
-	fence_status.ip_type = ip;
-	fence_status.fence = ibs_request.seq_no;
-
-	r = amdgpu_cs_query_fence_status(&fence_status, AMDGPU_TIMEOUT_INFINITE, 0,
-	                                 &expired);
-	if (r)
-		return r;
-
-	return 0;
-}
-
-static void alloc_resource(struct amdgpu_jpeg_bo *jpeg_bo, unsigned size,
-                           unsigned domain)
-{
-	struct amdgpu_bo_alloc_request req = {0};
-	amdgpu_bo_handle buf_handle;
-	amdgpu_va_handle va_handle;
-	uint64_t va = 0;
-	int r;
-
-	req.alloc_size = ALIGN(size, 4096);
-	req.preferred_heap = domain;
-	r = amdgpu_bo_alloc(device_handle, &req, &buf_handle);
-	CU_ASSERT_EQUAL(r, 0);
-	r = amdgpu_va_range_alloc(device_handle, amdgpu_gpu_va_range_general,
-	                          req.alloc_size, 1, 0, &va, &va_handle, 0);
-	CU_ASSERT_EQUAL(r, 0);
-	r = amdgpu_bo_va_op(buf_handle, 0, req.alloc_size, va, 0, AMDGPU_VA_OP_MAP);
-	CU_ASSERT_EQUAL(r, 0);
-	jpeg_bo->addr = va;
-	jpeg_bo->handle = buf_handle;
-	jpeg_bo->size = req.alloc_size;
-	jpeg_bo->va_handle = va_handle;
-	r = amdgpu_bo_cpu_map(jpeg_bo->handle, (void **)&jpeg_bo->ptr);
-	CU_ASSERT_EQUAL(r, 0);
-	memset(jpeg_bo->ptr, 0, size);
-	r = amdgpu_bo_cpu_unmap(jpeg_bo->handle);
-	CU_ASSERT_EQUAL(r, 0);
-}
-
-static void free_resource(struct amdgpu_jpeg_bo *jpeg_bo)
-{
-	int r;
-
-	r = amdgpu_bo_va_op(jpeg_bo->handle, 0, jpeg_bo->size, jpeg_bo->addr, 0,
-	                    AMDGPU_VA_OP_UNMAP);
-	CU_ASSERT_EQUAL(r, 0);
-
-	r = amdgpu_va_range_free(jpeg_bo->va_handle);
-	CU_ASSERT_EQUAL(r, 0);
-
-	r = amdgpu_bo_free(jpeg_bo->handle);
-	CU_ASSERT_EQUAL(r, 0);
-	memset(jpeg_bo, 0, sizeof(*jpeg_bo));
-}
-
-static void set_reg_jpeg(unsigned reg, unsigned cond, unsigned type,
-                         uint32_t val)
-{
-	ib_cpu[len++] = RDECODE_PKTJ(reg, cond, type);
-	ib_cpu[len++] = val;
-}
-
-/* send a bitstream buffer command */
-static void send_cmd_bitstream(uint64_t addr)
-{
-
-	/* jpeg soft reset */
-	set_reg_jpeg(SOC15_REG_ADDR(mmUVD_JPEG_CNTL), COND0, TYPE0, 1);
-
-	/* ensuring the Reset is asserted in SCLK domain */
-	set_reg_jpeg(SOC15_REG_ADDR(mmUVD_CTX_INDEX), COND0, TYPE0, 0x01C2);
-	set_reg_jpeg(SOC15_REG_ADDR(mmUVD_CTX_DATA), COND0, TYPE0, 0x01400200);
-	set_reg_jpeg(SOC15_REG_ADDR(mmUVD_CTX_INDEX), COND0, TYPE0, 0x01C3);
-	set_reg_jpeg(SOC15_REG_ADDR(mmUVD_CTX_DATA), COND0, TYPE0, (1 << 9));
-	set_reg_jpeg(SOC15_REG_ADDR(mmUVD_SOFT_RESET), COND0, TYPE3, (1 << 9));
-
-	/* wait mem */
-	set_reg_jpeg(SOC15_REG_ADDR(mmUVD_JPEG_CNTL), COND0, TYPE0, 0);
-
-	/* ensuring the Reset is de-asserted in SCLK domain */
-	set_reg_jpeg(SOC15_REG_ADDR(mmUVD_CTX_INDEX), COND0, TYPE0, 0x01C3);
-	set_reg_jpeg(SOC15_REG_ADDR(mmUVD_CTX_DATA), COND0, TYPE0, (0 << 9));
-	set_reg_jpeg(SOC15_REG_ADDR(mmUVD_SOFT_RESET), COND0, TYPE3, (1 << 9));
-
-	/* set UVD_LMI_JPEG_READ_64BIT_BAR_LOW/HIGH based on bitstream buffer address */
-	set_reg_jpeg(SOC15_REG_ADDR(mmUVD_LMI_JPEG_READ_64BIT_BAR_HIGH), COND0, TYPE0,
-	             (addr >> 32));
-	set_reg_jpeg(SOC15_REG_ADDR(mmUVD_LMI_JPEG_READ_64BIT_BAR_LOW), COND0, TYPE0,
-	             (unsigned int)addr);
-
-	/* set jpeg_rb_base */
-	set_reg_jpeg(SOC15_REG_ADDR(mmUVD_JPEG_RB_BASE), COND0, TYPE0, 0);
-
-	/* set jpeg_rb_base */
-	set_reg_jpeg(SOC15_REG_ADDR(mmUVD_JPEG_RB_SIZE), COND0, TYPE0, 0xFFFFFFF0);
-
-	/* set jpeg_rb_wptr */
-	set_reg_jpeg(SOC15_REG_ADDR(mmUVD_JPEG_RB_WPTR), COND0, TYPE0,
-	             (JPEG_DEC_BSD_SIZE >> 2));
-}
-
-/* send a target buffer command */
-static void send_cmd_target(uint64_t addr)
-{
-
-	set_reg_jpeg(SOC15_REG_ADDR(mmUVD_JPEG_PITCH), COND0, TYPE0,
-	             (JPEG_DEC_DT_PITCH >> 4));
-	set_reg_jpeg(SOC15_REG_ADDR(mmUVD_JPEG_UV_PITCH), COND0, TYPE0,
-	             (JPEG_DEC_DT_PITCH >> 4));
-
-	set_reg_jpeg(SOC15_REG_ADDR(mmUVD_JPEG_TILING_CTRL), COND0, TYPE0, 0);
-	set_reg_jpeg(SOC15_REG_ADDR(mmUVD_JPEG_UV_TILING_CTRL), COND0, TYPE0, 0);
-
-	/* set UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW/HIGH based on target buffer address */
-	set_reg_jpeg(SOC15_REG_ADDR(mmUVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH), COND0,
-	             TYPE0, (addr >> 32));
-	set_reg_jpeg(SOC15_REG_ADDR(mmUVD_LMI_JPEG_WRITE_64BIT_BAR_LOW), COND0, TYPE0,
-	             (unsigned int)addr);
-
-	/* set output buffer data address */
-	set_reg_jpeg(SOC15_REG_ADDR(mmUVD_JPEG_INDEX), COND0, TYPE0, 0);
-	set_reg_jpeg(SOC15_REG_ADDR(mmUVD_JPEG_DATA), COND0, TYPE0,
-	             JPEG_DEC_LUMA_OFFSET);
-	set_reg_jpeg(SOC15_REG_ADDR(mmUVD_JPEG_INDEX), COND0, TYPE0, 1);
-	set_reg_jpeg(SOC15_REG_ADDR(mmUVD_JPEG_DATA), COND0, TYPE0,
-	             JPEG_DEC_CHROMA_OFFSET);
-	set_reg_jpeg(SOC15_REG_ADDR(mmUVD_JPEG_TIER_CNTL2), COND0, TYPE3, 0);
-
-	/* set output buffer read pointer */
-	set_reg_jpeg(SOC15_REG_ADDR(mmUVD_JPEG_OUTBUF_RPTR), COND0, TYPE0, 0);
-
-	/* enable error interrupts */
-	set_reg_jpeg(SOC15_REG_ADDR(mmUVD_JPEG_INT_EN), COND0, TYPE0, 0xFFFFFFFE);
-
-	/* start engine command */
-	set_reg_jpeg(SOC15_REG_ADDR(mmUVD_JPEG_CNTL), COND0, TYPE0, 0x6);
-
-	/* wait for job completion, wait for job JBSI fetch done */
-	set_reg_jpeg(SOC15_REG_ADDR(mmUVD_CTX_INDEX), COND0, TYPE0, 0x01C3);
-	set_reg_jpeg(SOC15_REG_ADDR(mmUVD_CTX_DATA), COND0, TYPE0,
-	             (JPEG_DEC_BSD_SIZE >> 2));
-	set_reg_jpeg(SOC15_REG_ADDR(mmUVD_CTX_INDEX), COND0, TYPE0, 0x01C2);
-	set_reg_jpeg(SOC15_REG_ADDR(mmUVD_CTX_DATA), COND0, TYPE0, 0x01400200);
-	set_reg_jpeg(SOC15_REG_ADDR(mmUVD_JPEG_RB_RPTR), COND0, TYPE3, 0xFFFFFFFF);
-
-	/* wait for job jpeg outbuf idle */
-	set_reg_jpeg(SOC15_REG_ADDR(mmUVD_CTX_INDEX), COND0, TYPE0, 0x01C3);
-	set_reg_jpeg(SOC15_REG_ADDR(mmUVD_CTX_DATA), COND0, TYPE0, 0xFFFFFFFF);
-	set_reg_jpeg(SOC15_REG_ADDR(mmUVD_JPEG_OUTBUF_WPTR), COND0, TYPE3,
-	             0x00000001);
-
-	/* stop engine */
-	set_reg_jpeg(SOC15_REG_ADDR(mmUVD_JPEG_CNTL), COND0, TYPE0, 0x4);
-
-	/* asserting jpeg lmi drop */
-	set_reg_jpeg(SOC15_REG_ADDR(mmUVD_CTX_INDEX), COND0, TYPE0, 0x0005);
-	set_reg_jpeg(SOC15_REG_ADDR(mmUVD_CTX_DATA), COND0, TYPE0,
-	             (1 << 23 | 1 << 0));
-	set_reg_jpeg(SOC15_REG_ADDR(mmUVD_CTX_DATA), COND0, TYPE1, 0);
-	set_reg_jpeg(SOC15_REG_ADDR(mmUVD_CTX_DATA), COND0, TYPE0, 0);
-
-	/* asserting jpeg reset */
-	set_reg_jpeg(SOC15_REG_ADDR(mmUVD_JPEG_CNTL), COND0, TYPE0, 1);
-
-	/* ensure reset is asserted in sclk domain */
-	set_reg_jpeg(SOC15_REG_ADDR(mmUVD_CTX_INDEX), COND0, TYPE0, 0x01C3);
-	set_reg_jpeg(SOC15_REG_ADDR(mmUVD_CTX_DATA), COND0, TYPE0, (1 << 9));
-	set_reg_jpeg(SOC15_REG_ADDR(mmUVD_SOFT_RESET), COND0, TYPE3, (1 << 9));
-
-	/* de-assert jpeg reset */
-	set_reg_jpeg(SOC15_REG_ADDR(mmUVD_JPEG_CNTL), COND0, TYPE0, 0);
-
-	/* ensure reset is de-asserted in sclk domain */
-	set_reg_jpeg(SOC15_REG_ADDR(mmUVD_CTX_INDEX), COND0, TYPE0, 0x01C3);
-	set_reg_jpeg(SOC15_REG_ADDR(mmUVD_CTX_DATA), COND0, TYPE0, (0 << 9));
-	set_reg_jpeg(SOC15_REG_ADDR(mmUVD_SOFT_RESET), COND0, TYPE3, (1 << 9));
-
-	/* de-asserting jpeg lmi drop */
-	set_reg_jpeg(SOC15_REG_ADDR(mmUVD_CTX_INDEX), COND0, TYPE0, 0x0005);
-	set_reg_jpeg(SOC15_REG_ADDR(mmUVD_CTX_DATA), COND0, TYPE0, 0);
-}
-
-/* send a bitstream buffer command */
-static void send_cmd_bitstream_direct(uint64_t addr)
-{
-
-	/* jpeg soft reset */
-	set_reg_jpeg(vcnipUVD_JPEG_DEC_SOFT_RST, COND0, TYPE0, 1);
-
-	/* ensuring the Reset is asserted in SCLK domain */
-	set_reg_jpeg(vcnipUVD_JRBC_IB_COND_RD_TIMER, COND0, TYPE0, 0x01400200);
-	set_reg_jpeg(vcnipUVD_JRBC_IB_REF_DATA, COND0, TYPE0, (0x1 << 0x10));
-	set_reg_jpeg(vcnipUVD_JPEG_DEC_SOFT_RST, COND3, TYPE3, (0x1 << 0x10));
-
-	/* wait mem */
-	set_reg_jpeg(vcnipUVD_JPEG_DEC_SOFT_RST, COND0, TYPE0, 0);
-
-	/* ensuring the Reset is de-asserted in SCLK domain */
-	set_reg_jpeg(vcnipUVD_JRBC_IB_REF_DATA, COND0, TYPE0, (0 << 0x10));
-	set_reg_jpeg(vcnipUVD_JPEG_DEC_SOFT_RST, COND3, TYPE3, (0x1 << 0x10));
-
-	/* set UVD_LMI_JPEG_READ_64BIT_BAR_LOW/HIGH based on bitstream buffer address */
-	set_reg_jpeg(vcnipUVD_LMI_JPEG_READ_64BIT_BAR_HIGH, COND0, TYPE0,
-	             (addr >> 32));
-	set_reg_jpeg(vcnipUVD_LMI_JPEG_READ_64BIT_BAR_LOW, COND0, TYPE0, addr);
-
-	/* set jpeg_rb_base */
-	set_reg_jpeg(vcnipUVD_JPEG_RB_BASE, COND0, TYPE0, 0);
-
-	/* set jpeg_rb_base */
-	set_reg_jpeg(vcnipUVD_JPEG_RB_SIZE, COND0, TYPE0, 0xFFFFFFF0);
-
-	/* set jpeg_rb_wptr */
-	set_reg_jpeg(vcnipUVD_JPEG_RB_WPTR, COND0, TYPE0, (JPEG_DEC_BSD_SIZE >> 2));
-}
-
-/* send a target buffer command */
-static void send_cmd_target_direct(uint64_t addr)
-{
-
-	set_reg_jpeg(vcnipUVD_JPEG_PITCH, COND0, TYPE0, (JPEG_DEC_DT_PITCH >> 4));
-	set_reg_jpeg(vcnipUVD_JPEG_UV_PITCH, COND0, TYPE0, (JPEG_DEC_DT_PITCH >> 4));
-
-	set_reg_jpeg(vcnipJPEG_DEC_ADDR_MODE, COND0, TYPE0, 0);
-	set_reg_jpeg(vcnipJPEG_DEC_Y_GFX10_TILING_SURFACE, COND0, TYPE0, 0);
-	set_reg_jpeg(vcnipJPEG_DEC_UV_GFX10_TILING_SURFACE, COND0, TYPE0, 0);
-
-	/* set UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW/HIGH based on target buffer address */
-	set_reg_jpeg(vcnipUVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH, COND0, TYPE0,
-	             (addr >> 32));
-	set_reg_jpeg(vcnipUVD_LMI_JPEG_WRITE_64BIT_BAR_LOW, COND0, TYPE0, addr);
-
-	/* set output buffer data address */
-	set_reg_jpeg(vcnipUVD_JPEG_INDEX, COND0, TYPE0, 0);
-	set_reg_jpeg(vcnipUVD_JPEG_DATA, COND0, TYPE0, JPEG_DEC_LUMA_OFFSET);
-	set_reg_jpeg(vcnipUVD_JPEG_INDEX, COND0, TYPE0, 1);
-	set_reg_jpeg(vcnipUVD_JPEG_DATA, COND0, TYPE0, JPEG_DEC_CHROMA_OFFSET);
-	set_reg_jpeg(vcnipUVD_JPEG_TIER_CNTL2, COND0, 0, 0);
-
-	/* set output buffer read pointer */
-	set_reg_jpeg(vcnipUVD_JPEG_OUTBUF_RPTR, COND0, TYPE0, 0);
-	set_reg_jpeg(vcnipUVD_JPEG_OUTBUF_CNTL, COND0, TYPE0,
-	             ((0x00001587 & (~0x00000180L)) | (0x1 << 0x7) | (0x1 << 0x6)));
-
-	/* enable error interrupts */
-	set_reg_jpeg(vcnipUVD_JPEG_INT_EN, COND0, TYPE0, 0xFFFFFFFE);
-
-	/* start engine command */
-	set_reg_jpeg(vcnipUVD_JPEG_CNTL, COND0, TYPE0, 0xE);
-
-	/* wait for job completion, wait for job JBSI fetch done */
-	set_reg_jpeg(vcnipUVD_JRBC_IB_REF_DATA, COND0, TYPE0,
-	             (JPEG_DEC_BSD_SIZE >> 2));
-	set_reg_jpeg(vcnipUVD_JRBC_IB_COND_RD_TIMER, COND0, TYPE0, 0x01400200);
-	set_reg_jpeg(vcnipUVD_JPEG_RB_RPTR, COND3, TYPE3, 0xFFFFFFFF);
-
-	/* wait for job jpeg outbuf idle */
-	set_reg_jpeg(vcnipUVD_JRBC_IB_REF_DATA, COND0, TYPE0, 0xFFFFFFFF);
-	set_reg_jpeg(vcnipUVD_JPEG_OUTBUF_WPTR, COND3, TYPE3, 0x00000001);
-
-	/* stop engine */
-	set_reg_jpeg(vcnipUVD_JPEG_CNTL, COND0, TYPE0, 0x4);
-}
-
-static void amdgpu_cs_jpeg_decode(void)
-{
-
-	struct amdgpu_jpeg_bo dec_buf;
-	int size, r;
-	uint8_t *dec;
-	int sum = 0, i, j;
-
-	size = 16 * 1024; /* 8K bitstream + 8K output */
-	num_resources = 0;
-	alloc_resource(&dec_buf, size, AMDGPU_GEM_DOMAIN_VRAM);
-	resources[num_resources++] = dec_buf.handle;
-	resources[num_resources++] = ib_handle;
-	r = amdgpu_bo_cpu_map(dec_buf.handle, (void **)&dec_buf.ptr);
-	CU_ASSERT_EQUAL(r, 0);
-	memcpy(dec_buf.ptr, jpeg_bitstream, sizeof(jpeg_bitstream));
-
-	len = 0;
-
-	if (jpeg_direct_reg == true) {
-		send_cmd_bitstream_direct(dec_buf.addr);
-		send_cmd_target_direct(dec_buf.addr + (size / 2));
-	} else {
-		send_cmd_bitstream(dec_buf.addr);
-		send_cmd_target(dec_buf.addr + (size / 2));
-	}
-
-	amdgpu_bo_cpu_unmap(dec_buf.handle);
-	r = submit(len, AMDGPU_HW_IP_VCN_JPEG);
-	CU_ASSERT_EQUAL(r, 0);
-
-	r = amdgpu_bo_cpu_map(dec_buf.handle, (void **)&dec_buf.ptr);
-	CU_ASSERT_EQUAL(r, 0);
-
-	dec = dec_buf.ptr + (size / 2);
-
-	/* calculate result checksum */
-	for (i = 0; i < 8; i++)
-		for (j = 0; j < 8; j++)
-			sum += *((dec + JPEG_DEC_LUMA_OFFSET + i * JPEG_DEC_DT_PITCH) + j);
-	for (i = 0; i < 4; i++)
-		for (j = 0; j < 8; j++)
-			sum += *((dec + JPEG_DEC_CHROMA_OFFSET + i * JPEG_DEC_DT_PITCH) + j);
-
-	amdgpu_bo_cpu_unmap(dec_buf.handle);
-	CU_ASSERT_EQUAL(sum, JPEG_DEC_SUM);
-
-	free_resource(&dec_buf);
-}

tests/amdgpu/meson.build

@@ -18,22 +18,6 @@
 # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 # SOFTWARE.
 
-if dep_cunit.found()
-  amdgpu_test = executable(
-    'amdgpu_test',
-    files(
-      'amdgpu_test.c', 'basic_tests.c', 'bo_tests.c', 'cs_tests.c',
-      'vce_tests.c', 'uvd_enc_tests.c', 'vcn_tests.c', 'deadlock_tests.c',
-      'vm_tests.c', 'ras_tests.c', 'syncobj_tests.c', 'security_tests.c',
-      'hotunplug_tests.c', 'jpeg_tests.c', 'cp_dma_tests.c', 'shader_test_util.c'
-    ),
-    dependencies : [dep_cunit, dep_threads, dep_atomic_ops],
-    include_directories : [inc_root, inc_drm, include_directories('../../amdgpu')],
-    link_with : [libdrm, libdrm_amdgpu],
-    install : with_install_tests,
-  )
-endif
-
 amdgpu_stress = executable(
   'amdgpu_stress',
   files(

tests/amdgpu/security_tests.c

@@ -1,486 +0,0 @@
-/*
- * Copyright 2019 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-
-#include "CUnit/Basic.h"
-
-#include "amdgpu_test.h"
-#include "amdgpu_drm.h"
-#include "amdgpu_internal.h"
-
-#include <string.h>
-#include <unistd.h>
-#ifdef __FreeBSD__
-#include <sys/endian.h>
-#else
-#include <endian.h>
-#endif
-#include <strings.h>
-#include <xf86drm.h>
-
-static amdgpu_device_handle device_handle;
-static uint32_t major_version;
-static uint32_t minor_version;
-
-static struct drm_amdgpu_info_hw_ip  sdma_info;
-
-#ifndef ARRAY_SIZE
-#define ARRAY_SIZE(_Arr)  (sizeof(_Arr)/sizeof((_Arr)[0]))
-#endif
-
-
-/* --------------------- Secure bounce test ------------------------ *
- *
- * The secure bounce test tests that we can evict a TMZ buffer,
- * and page it back in, via a bounce buffer, as it encryption/decryption
- * depends on its physical address, and have the same data, i.e. data
- * integrity is preserved.
- *
- * The steps are as follows (from Christian K.):
- *
- * Buffer A which is TMZ protected and filled by the CPU with a
- * certain pattern. That the GPU is reading only random nonsense from
- * that pattern is irrelevant for the test.
- *
- * This buffer A is then secure copied into buffer B which is also
- * TMZ protected.
- *
- * Buffer B is moved around, from VRAM to GTT, GTT to SYSTEM,
- * etc.
- *
- * Then, we use another secure copy of buffer B back to buffer A.
- *
- * And lastly we check with the CPU the pattern.
- *
- * Assuming that we don't have memory contention and buffer A stayed
- * at the same place, we should still see the same pattern when read
- * by the CPU.
- *
- * If we don't see the same pattern then something in the buffer
- * migration code is not working as expected.
- */
-
-#define SECURE_BOUNCE_TEST_STR    "secure bounce"
-#define SECURE_BOUNCE_FAILED_STR  SECURE_BOUNCE_TEST_STR " failed"
-
-#define PRINT_ERROR(_Res)   fprintf(stderr, "%s:%d: %s (%d)\n",	\
-				    __func__, __LINE__, strerror(-(_Res)), _Res)
-
-#define PACKET_LCOPY_SIZE         7
-#define PACKET_NOP_SIZE          12
-
-struct sec_amdgpu_bo {
-	struct amdgpu_bo *bo;
-	struct amdgpu_va *va;
-};
-
-struct command_ctx {
-	struct amdgpu_device    *dev;
-	struct amdgpu_cs_ib_info cs_ibinfo;
-	struct amdgpu_cs_request cs_req;
-	struct amdgpu_context   *context;
-	int ring_id;
-};
-
-/**
- * amdgpu_bo_alloc_map -- Allocate and map a buffer object (BO)
- * @dev: The AMDGPU device this BO belongs to.
- * @size: The size of the BO.
- * @alignment: Alignment of the BO.
- * @gem_domain: One of AMDGPU_GEM_DOMAIN_xyz.
- * @alloc_flags: One of AMDGPU_GEM_CREATE_xyz.
- * @sbo: the result
- *
- * Allocate a buffer object (BO) with the desired attributes
- * as specified by the argument list and write out the result
- * into @sbo.
- *
- * Return 0 on success and @sbo->bo and @sbo->va are set,
- * or -errno on error.
- */
-static int amdgpu_bo_alloc_map(struct amdgpu_device *dev,
-			       unsigned size,
-			       unsigned alignment,
-			       unsigned gem_domain,
-			       uint64_t alloc_flags,
-			       struct sec_amdgpu_bo *sbo)
-{
-	void *cpu;
-	uint64_t mc_addr;
-
-	return amdgpu_bo_alloc_and_map_raw(dev,
-					   size,
-					   alignment,
-					   gem_domain,
-					   alloc_flags,
-					   0,
-					   &sbo->bo,
-					   &cpu, &mc_addr,
-					   &sbo->va);
-}
-
-static void amdgpu_bo_unmap_free(struct sec_amdgpu_bo *sbo,
-				 const uint64_t size)
-{
-	(void) amdgpu_bo_unmap_and_free(sbo->bo,
-					sbo->va,
-					sbo->va->address,
-					size);
-	sbo->bo = NULL;
-	sbo->va = NULL;
-}
-
-static void amdgpu_sdma_lcopy(uint32_t *packet,
-			      const uint64_t dst,
-			      const uint64_t src,
-			      const uint32_t size,
-			      const int secure)
-{
-	/* Set the packet to Linear copy with TMZ set.
-	 */
-	packet[0] = htole32(secure << 18 | 1);
-	packet[1] = htole32(size-1);
-	packet[2] = htole32(0);
-	packet[3] = htole32((uint32_t)(src & 0xFFFFFFFFU));
-	packet[4] = htole32((uint32_t)(src >> 32));
-	packet[5] = htole32((uint32_t)(dst & 0xFFFFFFFFU));
-	packet[6] = htole32((uint32_t)(dst >> 32));
-}
-
-static void amdgpu_sdma_nop(uint32_t *packet, uint32_t nop_count)
-{
-	/* A packet of the desired number of NOPs.
-	 */
-	packet[0] = htole32(nop_count << 16);
-	for ( ; nop_count > 0; nop_count--)
-		packet[nop_count-1] = 0;
-}
-
-/**
- * amdgpu_bo_lcopy -- linear copy with TMZ set, using sDMA
- * @dev: AMDGPU device to which both buffer objects belong to
- * @dst: destination buffer object
- * @src: source buffer object
- * @size: size of memory to move, in bytes.
- * @secure: Set to 1 to perform secure copy, 0 for clear
- *
- * Issues and waits for completion of a Linear Copy with TMZ
- * set, to the sDMA engine. @size should be a multiple of
- * at least 16 bytes.
- */
-static void amdgpu_bo_lcopy(struct command_ctx *ctx,
-			    struct sec_amdgpu_bo *dst,
-			    struct sec_amdgpu_bo *src,
-			    const uint32_t size,
-			    int secure)
-{
-	struct amdgpu_bo *bos[] = { dst->bo, src->bo };
-	uint32_t packet[PACKET_LCOPY_SIZE];
-
-	amdgpu_sdma_lcopy(packet,
-			  dst->va->address,
-			  src->va->address,
-			  size, secure);
-	amdgpu_test_exec_cs_helper_raw(ctx->dev, ctx->context,
-				       AMDGPU_HW_IP_DMA, ctx->ring_id,
-				       ARRAY_SIZE(packet), packet,
-				       ARRAY_SIZE(bos), bos,
-				       &ctx->cs_ibinfo, &ctx->cs_req,
-				       secure == 1);
-}
-
-/**
- * amdgpu_bo_move -- Evoke a move of the buffer object (BO)
- * @dev: device to which this buffer object belongs to
- * @bo: the buffer object to be moved
- * @whereto: one of AMDGPU_GEM_DOMAIN_xyz
- * @secure: set to 1 to submit secure IBs
- *
- * Evokes a move of the buffer object @bo to the GEM domain
- * descibed by @whereto.
- *
- * Returns 0 on sucess; -errno on error.
- */
-static int amdgpu_bo_move(struct command_ctx *ctx,
-			  struct amdgpu_bo *bo,
-			  uint64_t whereto,
-			  int secure)
-{
-	struct amdgpu_bo *bos[] = { bo };
-	struct drm_amdgpu_gem_op gop = {
-		.handle  = bo->handle,
-		.op      = AMDGPU_GEM_OP_SET_PLACEMENT,
-		.value   = whereto,
-	};
-	uint32_t packet[PACKET_NOP_SIZE];
-	int res;
-
-	/* Change the buffer's placement.
-	 */
-	res = drmIoctl(ctx->dev->fd, DRM_IOCTL_AMDGPU_GEM_OP, &gop);
-	if (res)
-		return -errno;
-
-	/* Now issue a NOP to actually evoke the MM to move
-	 * it to the desired location.
-	 */
-	amdgpu_sdma_nop(packet, PACKET_NOP_SIZE);
-	amdgpu_test_exec_cs_helper_raw(ctx->dev, ctx->context,
-				       AMDGPU_HW_IP_DMA, ctx->ring_id,
-				       ARRAY_SIZE(packet), packet,
-				       ARRAY_SIZE(bos), bos,
-				       &ctx->cs_ibinfo, &ctx->cs_req,
-				       secure == 1);
-	return 0;
-}
-
-/* Safe, O Sec!
- */
-static const uint8_t secure_pattern[] = { 0x5A, 0xFE, 0x05, 0xEC };
-
-#define SECURE_BUFFER_SIZE       (4 * 1024 * sizeof(secure_pattern))
-
-static void amdgpu_secure_bounce(void)
-{
-	struct sec_amdgpu_bo alice, bob;
-	struct command_ctx   sb_ctx;
-	long page_size;
-	uint8_t *pp;
-	int res;
-
-	page_size = sysconf(_SC_PAGESIZE);
-
-	memset(&sb_ctx, 0, sizeof(sb_ctx));
-	sb_ctx.dev = device_handle;
-	res = amdgpu_cs_ctx_create(sb_ctx.dev, &sb_ctx.context);
-	if (res) {
-		PRINT_ERROR(res);
-		CU_FAIL(SECURE_BOUNCE_FAILED_STR);
-		return;
-	}
-
-	/* Use the first present ring.
-	 */
-	res = ffs(sdma_info.available_rings) - 1;
-	if (res == -1) {
-		PRINT_ERROR(-ENOENT);
-		CU_FAIL(SECURE_BOUNCE_FAILED_STR);
-		goto Out_free_ctx;
-	}
-	sb_ctx.ring_id = res;
-
-	/* Allocate a buffer named Alice in VRAM.
-	 */
-	res = amdgpu_bo_alloc_map(device_handle,
-				  SECURE_BUFFER_SIZE,
-				  page_size,
-				  AMDGPU_GEM_DOMAIN_VRAM,
-				  AMDGPU_GEM_CREATE_ENCRYPTED,
-				  &alice);
-	if (res) {
-		PRINT_ERROR(res);
-		CU_FAIL(SECURE_BOUNCE_FAILED_STR);
-		return;
-	}
-
-	/* Fill Alice with a pattern.
-	 */
-	for (pp = alice.bo->cpu_ptr;
-	     pp < (__typeof__(pp)) alice.bo->cpu_ptr + SECURE_BUFFER_SIZE;
-	     pp += sizeof(secure_pattern))
-		memcpy(pp, secure_pattern, sizeof(secure_pattern));
-
-	/* Allocate a buffer named Bob in VRAM.
-	 */
-	res = amdgpu_bo_alloc_map(device_handle,
-				  SECURE_BUFFER_SIZE,
-				  page_size,
-				  AMDGPU_GEM_DOMAIN_VRAM,
-				  AMDGPU_GEM_CREATE_ENCRYPTED,
-				  &bob);
-	if (res) {
-		PRINT_ERROR(res);
-		CU_FAIL(SECURE_BOUNCE_FAILED_STR);
-		goto Out_free_Alice;
-	}
-
-	/* sDMA TMZ copy from Alice to Bob.
-	 */
-	amdgpu_bo_lcopy(&sb_ctx, &bob, &alice, SECURE_BUFFER_SIZE, 1);
-
-	/* Move Bob to the GTT domain.
-	 */
-	res = amdgpu_bo_move(&sb_ctx, bob.bo, AMDGPU_GEM_DOMAIN_GTT, 0);
-	if (res) {
-		PRINT_ERROR(res);
-		CU_FAIL(SECURE_BOUNCE_FAILED_STR);
-		goto Out_free_all;
-	}
-
-	/* sDMA TMZ copy from Bob to Alice.
-	 */
-	amdgpu_bo_lcopy(&sb_ctx, &alice, &bob, SECURE_BUFFER_SIZE, 1);
-
-	/* Verify the contents of Alice.
-	 */
-	for (pp = alice.bo->cpu_ptr;
-	     pp < (__typeof__(pp)) alice.bo->cpu_ptr + SECURE_BUFFER_SIZE;
-	     pp += sizeof(secure_pattern)) {
-		res = memcmp(pp, secure_pattern, sizeof(secure_pattern));
-		if (res) {
-			fprintf(stderr, SECURE_BOUNCE_FAILED_STR);
-			CU_FAIL(SECURE_BOUNCE_FAILED_STR);
-			break;
-		}
-	}
-
-Out_free_all:
-	amdgpu_bo_unmap_free(&bob, SECURE_BUFFER_SIZE);
-Out_free_Alice:
-	amdgpu_bo_unmap_free(&alice, SECURE_BUFFER_SIZE);
-Out_free_ctx:
-	res = amdgpu_cs_ctx_free(sb_ctx.context);
-	CU_ASSERT_EQUAL(res, 0);
-}
-
-/* ----------------------------------------------------------------- */
-
-static void amdgpu_security_alloc_buf_test(void)
-{
-	amdgpu_bo_handle bo;
-	amdgpu_va_handle va_handle;
-	uint64_t bo_mc;
-	int r;
-
-	/* Test secure buffer allocation in VRAM */
-	bo = gpu_mem_alloc(device_handle, 4096, 4096,
-			   AMDGPU_GEM_DOMAIN_VRAM,
-			   AMDGPU_GEM_CREATE_ENCRYPTED,
-			   &bo_mc, &va_handle);
-
-	r = gpu_mem_free(bo, va_handle, bo_mc, 4096);
-	CU_ASSERT_EQUAL(r, 0);
-
-	/* Test secure buffer allocation in system memory */
-	bo = gpu_mem_alloc(device_handle, 4096, 4096,
-			   AMDGPU_GEM_DOMAIN_GTT,
-			   AMDGPU_GEM_CREATE_ENCRYPTED,
-			   &bo_mc, &va_handle);
-
-	r = gpu_mem_free(bo, va_handle, bo_mc, 4096);
-	CU_ASSERT_EQUAL(r, 0);
-
-	/* Test secure buffer allocation in invisible VRAM */
-	bo = gpu_mem_alloc(device_handle, 4096, 4096,
-			   AMDGPU_GEM_DOMAIN_GTT,
-			   AMDGPU_GEM_CREATE_ENCRYPTED |
-			   AMDGPU_GEM_CREATE_NO_CPU_ACCESS,
-			   &bo_mc, &va_handle);
-
-	r = gpu_mem_free(bo, va_handle, bo_mc, 4096);
-	CU_ASSERT_EQUAL(r, 0);
-}
-
-static void amdgpu_security_gfx_submission_test(void)
-{
-	amdgpu_command_submission_write_linear_helper_with_secure(device_handle,
-								  AMDGPU_HW_IP_GFX,
-								  true);
-}
-
-static void amdgpu_security_sdma_submission_test(void)
-{
-	amdgpu_command_submission_write_linear_helper_with_secure(device_handle,
-								  AMDGPU_HW_IP_DMA,
-								  true);
-}
-
-/* ----------------------------------------------------------------- */
-
-CU_TestInfo security_tests[] = {
-	{ "allocate secure buffer test",        amdgpu_security_alloc_buf_test },
-	{ "graphics secure command submission", amdgpu_security_gfx_submission_test },
-	{ "sDMA secure command submission",     amdgpu_security_sdma_submission_test },
-	{ SECURE_BOUNCE_TEST_STR,               amdgpu_secure_bounce },
-	CU_TEST_INFO_NULL,
-};
-
-CU_BOOL suite_security_tests_enable(void)
-{
-	CU_BOOL enable = CU_TRUE;
-
-	if (amdgpu_device_initialize(drm_amdgpu[0], &major_version,
-				     &minor_version, &device_handle))
-		return CU_FALSE;
-
-
-	if (!(device_handle->dev_info.ids_flags & AMDGPU_IDS_FLAGS_TMZ)) {
-		printf("\n\nDon't support TMZ (trust memory zone), security suite disabled\n");
-		enable = CU_FALSE;
-	}
-
-	if ((major_version < 3) ||
-		((major_version == 3) && (minor_version < 37))) {
-		printf("\n\nDon't support TMZ (trust memory zone), kernel DRM version (%d.%d)\n",
-			major_version, minor_version);
-		printf("is older, security suite disabled\n");
-		enable = CU_FALSE;
-	}
-
-	if (amdgpu_device_deinitialize(device_handle))
-		return CU_FALSE;
-
-	return enable;
-}
-
-int suite_security_tests_init(void)
-{
-	int res;
-
-	res = amdgpu_device_initialize(drm_amdgpu[0], &major_version,
-				       &minor_version, &device_handle);
-	if (res) {
-		PRINT_ERROR(res);
-		return CUE_SINIT_FAILED;
-	}
-
-	res = amdgpu_query_hw_ip_info(device_handle,
-				      AMDGPU_HW_IP_DMA,
-				      0, &sdma_info);
-	if (res) {
-		PRINT_ERROR(res);
-		return CUE_SINIT_FAILED;
-	}
-
-	return CUE_SUCCESS;
-}
-
-int suite_security_tests_clean(void)
-{
-	int res;
-
-	res = amdgpu_device_deinitialize(device_handle);
-	if (res)
-		return CUE_SCLEAN_FAILED;
-
-	return CUE_SUCCESS;
-}

tests/amdgpu/shader_code.h

@@ -1,153 +0,0 @@
-/*
- * Copyright 2022 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
-*/
-
-#ifndef _shader_code_h_
-#define _shader_code_h_
-
-#ifndef ARRAY_SIZE
-#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
-#endif
-
-enum amdgpu_test_gfx_version {
-	AMDGPU_TEST_GFX_V9 = 0,
-	AMDGPU_TEST_GFX_V10,
-	AMDGPU_TEST_GFX_V11,
-	AMDGPU_TEST_GFX_MAX,
-};
-
-enum cs_type {
-	CS_BUFFERCLEAR = 0,
-	CS_BUFFERCOPY,
-	CS_HANG,
-	CS_HANG_SLOW,
-};
-
-enum ps_type {
-	PS_CONST,
-	PS_TEX,
-	PS_HANG,
-	PS_HANG_SLOW
-};
-
-enum vs_type {
-	VS_RECTPOSTEXFAST,
-};
-
-struct reg_info {
-	uint32_t reg_offset;			///< Memory mapped register offset
-	uint32_t reg_value;			///< register value
-};
-
-#include "shader_code_hang.h"
-#include "shader_code_gfx9.h"
-#include "shader_code_gfx10.h"
-#include "shader_code_gfx11.h"
-
-struct shader_test_cs_shader {
-	const uint32_t *shader;
-	uint32_t shader_size;
-	const struct reg_info *sh_reg;
-	uint32_t num_sh_reg;
-	const struct reg_info *context_reg;
-	uint32_t num_context_reg;
-};
-
-struct shader_test_ps_shader {
-	const uint32_t *shader;
-	unsigned shader_size;
-	uint32_t patchinfo_code_size;
-	const uint32_t *patchinfo_code;
-	const uint32_t *patchinfo_code_offset;
-	const struct reg_info *sh_reg;
-	uint32_t num_sh_reg;
-	const struct reg_info *context_reg;
-	uint32_t num_context_reg;
-};
-
-struct shader_test_vs_shader {
-	const uint32_t *shader;
-	uint32_t shader_size;
-	const struct reg_info *sh_reg;
-	uint32_t num_sh_reg;
-	const struct reg_info *context_reg;
-	uint32_t num_context_reg;
-};
-
-static const struct shader_test_cs_shader shader_test_cs[AMDGPU_TEST_GFX_MAX][2] = {
-	// gfx9, cs_bufferclear
-	{{bufferclear_cs_shader_gfx9, sizeof(bufferclear_cs_shader_gfx9), bufferclear_cs_shader_registers_gfx9, ARRAY_SIZE(bufferclear_cs_shader_registers_gfx9)},
-	// gfx9, cs_buffercopy
-	{buffercopy_cs_shader_gfx9, sizeof(buffercopy_cs_shader_gfx9), bufferclear_cs_shader_registers_gfx9, ARRAY_SIZE(bufferclear_cs_shader_registers_gfx9)}},
-	// gfx10, cs_bufferclear
-	{{bufferclear_cs_shader_gfx10, sizeof(bufferclear_cs_shader_gfx10), bufferclear_cs_shader_registers_gfx9, ARRAY_SIZE(bufferclear_cs_shader_registers_gfx9)},
-	// gfx10, cs_buffercopy
-	{buffercopy_cs_shader_gfx10, sizeof(bufferclear_cs_shader_gfx10), bufferclear_cs_shader_registers_gfx9, ARRAY_SIZE(bufferclear_cs_shader_registers_gfx9)}},
-	// gfx11, cs_bufferclear
-	{{bufferclear_cs_shader_gfx11, sizeof(bufferclear_cs_shader_gfx11), bufferclear_cs_shader_registers_gfx11, ARRAY_SIZE(bufferclear_cs_shader_registers_gfx11)},
-	// gfx11, cs_buffercopy
-	{buffercopy_cs_shader_gfx11, sizeof(bufferclear_cs_shader_gfx11), bufferclear_cs_shader_registers_gfx11, ARRAY_SIZE(bufferclear_cs_shader_registers_gfx11)}},
-};
-
-#define SHADER_PS_INFO(_ps, _n) \
-	{ps_##_ps##_shader_gfx##_n, sizeof(ps_##_ps##_shader_gfx##_n), \
-	ps_##_ps##_shader_patchinfo_code_size_gfx##_n, \
-	&(ps_##_ps##_shader_patchinfo_code_gfx##_n)[0][0][0], \
-	ps_##_ps##_shader_patchinfo_offset_gfx##_n, \
-	ps_##_ps##_sh_registers_gfx##_n, ps_##_ps##_num_sh_registers_gfx##_n, \
-	ps_##_ps##_context_registers_gfx##_n, ps_##_ps##_num_context_registers_gfx##_n}
-static const struct shader_test_ps_shader shader_test_ps[AMDGPU_TEST_GFX_MAX][2] = {
-	{SHADER_PS_INFO(const, 9), SHADER_PS_INFO(tex, 9)},
-	{SHADER_PS_INFO(const, 10), SHADER_PS_INFO(tex, 10)},
-	{SHADER_PS_INFO(const, 11), SHADER_PS_INFO(tex, 11)},
-};
-
-#define SHADER_VS_INFO(_vs, _n) \
-	{vs_##_vs##_shader_gfx##_n, sizeof(vs_##_vs##_shader_gfx##_n), \
-	vs_##_vs##_sh_registers_gfx##_n, vs_##_vs##_num_sh_registers_gfx##_n, \
-	vs_##_vs##_context_registers_gfx##_n, vs_##_vs##_num_context_registers_gfx##_n}
-static const struct shader_test_vs_shader shader_test_vs[AMDGPU_TEST_GFX_MAX][1] = {
-	{SHADER_VS_INFO(RectPosTexFast, 9)},
-	{SHADER_VS_INFO(RectPosTexFast, 10)},
-	{SHADER_VS_INFO(RectPosTexFast, 11)},
-};
-
-struct shader_test_gfx_info {
-	const uint32_t *preamble_cache;
-	uint32_t size_preamble_cache;
-	const uint32_t *cached_cmd;
-	uint32_t size_cached_cmd;
-	uint32_t sh_reg_base;
-	uint32_t context_reg_base;
-};
-
-#define SHADER_TEST_GFX_INFO(_n) \
-	preamblecache_gfx##_n, sizeof(preamblecache_gfx##_n), \
-	cached_cmd_gfx##_n, sizeof(cached_cmd_gfx##_n), \
-	sh_reg_base_gfx##_n, context_reg_base_gfx##_n
-
-static struct shader_test_gfx_info shader_test_gfx_info[AMDGPU_TEST_GFX_MAX] = {
-	{SHADER_TEST_GFX_INFO(9),},
-	{SHADER_TEST_GFX_INFO(10),},
-	{SHADER_TEST_GFX_INFO(11),},
-};
-#endif

tests/amdgpu/shader_code_gfx10.h

@@ -1,202 +0,0 @@
-/*
- * Copyright 2022 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
-*/
-
-#ifndef _shader_code_gfx10_h_
-#define _shader_code_gfx10_h_
-
-static const uint32_t bufferclear_cs_shader_gfx10[] = {
-	0xD7460004, 0x04010C08, 0x7E000204, 0x7E020205,
-	0x7E040206, 0x7E060207, 0xE01C2000, 0x80000004,
-	0xBF810000
-};
-
-static const uint32_t buffercopy_cs_shader_gfx10[] = {
-	0xD7460001, 0x04010C08, 0xE00C2000, 0x80000201,
-	0xBF8C3F70, 0xE01C2000, 0x80010201, 0xBF810000
-};
-
-static const uint32_t ps_const_shader_gfx10[] = {
-    0x7E000200, 0x7E020201, 0x7E040202, 0x7E060203,
-    0x5E000300, 0x5E020702, 0xBF800000, 0xBF800000,
-    0xF8001C0F, 0x00000100, 0xBF810000
-};
-
-#define ps_const_shader_patchinfo_code_size_gfx10 6
-
-static const uint32_t ps_const_shader_patchinfo_code_gfx10[][10][6] = {
-    {{ 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF8001890, 0x00000000 },
-     { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF8001801, 0x00000000 },
-     { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF8001803, 0x00000100 },
-     { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF8001803, 0x00000300 },
-     { 0x5E000300, 0x5E020702, 0xBF800000, 0xBF800000, 0xF8001C0F, 0x00000100 },
-     { 0xD7690000, 0x00020300, 0xD7690001, 0x00020702, 0xF8001C0F, 0x00000100 },
-     { 0xD7680000, 0x00020300, 0xD7680001, 0x00020702, 0xF8001C0F, 0x00000100 },
-     { 0xD76A0000, 0x00020300, 0xD76A0001, 0x00020702, 0xF8001C0F, 0x00000100 },
-     { 0xD76B0000, 0x00020300, 0xD76B0001, 0x00020702, 0xF8001C0F, 0x00000100 },
-     { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF800180F, 0x03020100 }
-    }
-};
-
-static const uint32_t ps_const_shader_patchinfo_offset_gfx10[] = {
-    0x00000004
-};
-
-#define ps_const_num_sh_registers_gfx10 2
-
-static const struct reg_info ps_const_sh_registers_gfx10[] = {
-	{0x2C0A, 0x000C0000},//{ mmSPI_SHADER_PGM_RSRC1_PS, 0x000C0000 },
-	{0x2C0B, 0x00000008}, //{ mmSPI_SHADER_PGM_RSRC2_PS, 0x00000008 }
-};
-
-static const struct reg_info ps_const_context_registers_gfx10[] =
-{
-    {0xA1B4, 0x00000002}, //{ mmSPI_PS_INPUT_ADDR,       0x00000002 },
-    {0xA1B6, 0x00000000}, //{ mmSPI_PS_IN_CONTROL,       0x00000000 },
-    {0xA08F, 0x0000000F}, //{ mmCB_SHADER_MASK,          0x0000000F },
-    {0xA203, 0x00000010}, //{ mmDB_SHADER_CONTROL,       0x00000010 },
-    {0xA1C4, 0x00000000}, //{ mmSPI_SHADER_Z_FORMAT,     0x00000000 },
-    {0xA1B8, 0x00000000}, //{ mmSPI_BARYC_CNTL,          0x00000000 /* Always 0 for now */},
-    {0xA1C5, 0x00000004}, //{ mmSPI_SHADER_COL_FORMAT,   0x00000004 /* SI_EXPORT_FMT_FP16_ABGR */ }
-};
-
-#define ps_const_num_context_registers_gfx10 7
-
-static const uint32_t ps_tex_shader_gfx10[] = {
-    0xBEFC030C, 0xBE8E047E, 0xBEFE0A7E, 0xC8080000,
-    0xC80C0100, 0xC8090001, 0xC80D0101, 0xF0800F0A,
-    0x00400402, 0x00000003, 0xBEFE040E, 0xBF8C0F70,
-    0x5E000B04, 0x5E020F06, 0xBF800000, 0xBF800000,
-    0xF8001C0F, 0x00000100, 0xBF810000
-};
-
-static const uint32_t ps_tex_shader_patchinfo_offset_gfx10[] = {
-    0x0000000C
-};
-
-#define ps_tex_shader_patchinfo_code_size_gfx10 6
-
-static const uint32_t ps_tex_shader_patchinfo_code_gfx10[][10][6] = {
-    {{ 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF8001890, 0x00000000 },
-     { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF8001801, 0x00000004 },
-     { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF8001803, 0x00000504 },
-     { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF8001803, 0x00000704 },
-     { 0x5E000B04, 0x5E020F06, 0xBF800000, 0xBF800000, 0xF8001C0F, 0x00000100 },
-     { 0xD7690000, 0x00020B04, 0xD7690001, 0x00020F06, 0xF8001C0F, 0x00000100 },
-     { 0xD7680000, 0x00020B04, 0xD7680001, 0x00020F06, 0xF8001C0F, 0x00000100 },
-     { 0xD76A0000, 0x00020B04, 0xD76A0001, 0x00020F06, 0xF8001C0F, 0x00000100 },
-     { 0xD76B0000, 0x00020B04, 0xD76B0001, 0x00020F06, 0xF8001C0F, 0x00000100 },
-     { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF800180F, 0x07060504 }
-    }
-};
-
-static const struct reg_info ps_tex_sh_registers_gfx10[] =
-{
-     {0x2C0A, 0xc0081}, //0x020C0080 }, //{ mmSPI_SHADER_PGM_RSRC1_PS, 0x020C0080 },
-     {0x2C0B, 0x00000018 }, //{ mmSPI_SHADER_PGM_RSRC2_PS, 0x00000018 }
-};
-
-#define ps_tex_num_sh_registers_gfx10 2
-
-// Holds Context Register Information
-static const struct reg_info ps_tex_context_registers_gfx10[] =
-{
-    {0xA1B4, 0x00000002}, //{ mmSPI_PS_INPUT_ADDR,       0x00000002 },
-    {0xA1B6, 0x00000001}, //{ mmSPI_PS_IN_CONTROL,       0x00000001 },
-    {0xA08F, 0x0000000F}, //{ mmCB_SHADER_MASK,          0x0000000F },
-    {0xA203, 0x00000010}, //{ mmDB_SHADER_CONTROL,       0x00000010 },
-    {0xA1C4, 0x00000000}, //{ mmSPI_SHADER_Z_FORMAT,     0x00000000 },
-    {0xA1B8, 0x00000000}, //{ mmSPI_BARYC_CNTL,          0x00000000 /* Always 0 for now */},
-    {0xA1C5, 0x00000004}, //{ mmSPI_SHADER_COL_FORMAT,   0x00000004 /* SI_EXPORT_FMT_FP16_ABGR */ }
-};
-
-#define ps_tex_num_context_registers_gfx10 7
-
-static const uint32_t vs_RectPosTexFast_shader_gfx10[] = {
-    0x7E000B00, 0x060000F3, 0x7E020202, 0x7E040206,
-    0x7C040080, 0x060000F3, 0xD5010001, 0x01AA0200,
-    0x7E060203, 0xD5010002, 0x01AA0404, 0x7E080207,
-    0x7C040080, 0xD5010000, 0x01A80101, 0xD5010001,
-    0x01AA0601, 0x7E060208, 0x7E0A02F2, 0xD5010002,
-    0x01A80902, 0xD5010004, 0x01AA0805, 0x7E0C0209,
-    0xF80008CF, 0x05030100, 0xF800020F, 0x05060402,
-    0xBF810000
-};
-
-static const struct reg_info vs_RectPosTexFast_sh_registers_gfx10[] =
-{
-    {0x2C4A, 0x080C0041 }, //{ mmSPI_SHADER_PGM_RSRC1_VS, 0x080C0041 },
-    {0x2C4B, 0x00000018 }, //{ mmSPI_SHADER_PGM_RSRC2_VS, 0x00000018 }
-};
-
-#define vs_RectPosTexFast_num_sh_registers_gfx10 2
-
-// Holds Context Register Information
-static const struct reg_info vs_RectPosTexFast_context_registers_gfx10[] =
-{
-    {0xA1B1, 0x00000000}, //{ mmSPI_VS_OUT_CONFIG, 0x00000000 },
-    {0xA1C3, 0x00000000}, //{ mmSPI_SHADER_POS_FORMAT, 0x00000000 /* Always 0 for now */}
-};
-
-#define vs_RectPosTexFast_num_context_registers_gfx10 2
-
-static const uint32_t preamblecache_gfx10[] = {
-	0xc0026900, 0x81, 0x80000000, 0x40004000, 0xc0026900, 0x8c, 0xaa99aaaa, 0x0,
-	0xc0026900, 0x90, 0x80000000, 0x40004000, 0xc0026900, 0x94, 0x80000000, 0x40004000,
-	0xc0026900, 0xb4, 0x0, 0x3f800000, 0xc0016900, 0x103, 0x0,
-	0xc0016900, 0x208, 0x0, 0xc0016900, 0x290, 0x0,
-	0xc0016900, 0x2a1, 0x0, 0xc0026900, 0x2ad, 0x0, 0x0,
-	0xc0016900, 0x2d5, 0x10000, 0xc0016900, 0x2dc, 0x0,
-	0xc0066900, 0x2de, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xc0026900, 0x2e5, 0x0, 0x0,
-	0xc0056900, 0x2f9, 0x5, 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000,
-	0xc0046900, 0x310, 0, 0x3, 0, 0x100000, 0xc0026900, 0x316, 0xe, 0x20,
-	0xc0016900, 0x349, 0x0, 0xc0016900, 0x358, 0x0, 0xc0016900, 0x367, 0x0,
-	0xc0016900, 0x376, 0x0, 0xc0016900, 0x385, 0x0, 0xc0016900, 0x6, 0x0,
-	0xc0056900, 0xe8, 0x0, 0x0, 0x0, 0x0, 0x0,
-	0xc0076900, 0x1e1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
-	0xc0026900, 0x204, 0x90000, 0x4, 0xc0046900, 0x20c, 0x0, 0x0, 0x0, 0x0,
-	0xc0016900, 0x2b2, 0x0, 0xc0026900, 0x30e, 0xffffffff, 0xffffffff,
-	0xc0016900, 0x314, 0x0, 0xc0016900, 0x10a, 0, 0xc0016900, 0x2a6, 0, 0xc0016900, 0x210, 0,
-	0xc0016900, 0x2db, 0, 0xc0016900, 0x1d4, 0, 0xc0002f00, 0x1, 0xc0016900, 0x1, 0x1, 0xc0016900, 0xe, 0x2,
-	0xc0016900, 0x206, 0x300, 0xc0016900, 0x212, 0x200, 0xc0017900, 0x7b, 0x20, 0xc0017a00, 0x20000243, 0x0,
-	0xc0017900, 0x249, 0, 0xc0017900, 0x24a, 0, 0xc0017900, 0x24b, 0, 0xc0017900, 0x259, 0xffffffff,
-	0xc0017900, 0x25f, 0, 0xc0017900, 0x260, 0, 0xc0017900, 0x262, 0,
-	0xc0017600, 0x45, 0x0, 0xc0017600, 0x6, 0x0,
-	0xc0067600, 0x70, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
-	0xc0067600, 0x30, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0
-};
-
-static const uint32_t cached_cmd_gfx10[] = {
-	0xc0016900, 0x0, 0x0, 0xc0026900, 0x3, 0x2a, 0x0,
-	0xc0046900, 0xa, 0x0, 0x0, 0x0, 0x200020,
-	0xc0016900, 0x83, 0xffff, 0xc0026900, 0x8e, 0xf, 0xf,
-	0xc0056900, 0x105, 0x0, 0x0, 0x0, 0x0, 0x18,
-	0xc0026900, 0x10b, 0x0, 0x0, 0xc0016900, 0x1e0, 0x0,
-	0xc0036900, 0x200, 0x0, 0x10000, 0xcc0011,
-	0xc0026900, 0x292, 0x20, 0x6020000,
-	0xc0026900, 0x2b0, 0x0, 0x0, 0xc0016900, 0x2f8, 0x0
-};
-
-#define sh_reg_base_gfx10 0x2C00
-#define context_reg_base_gfx10 0xA000
-
-#endif

tests/amdgpu/shader_code_gfx11.h

@@ -1,320 +0,0 @@
-/*
- * Copyright 2022 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
-*/
-
-#ifndef _shader_code_gfx11_h_
-#define _shader_code_gfx11_h_
-
-static const uint32_t bufferclear_cs_shader_gfx11[] = {
-	0xB0802006, 0xBF840003, 0x360000FF, 0x000003FF,
-	0x7E020205, 0x7E040206, 0x7E060207, 0xBF870004,
-	0xD6460004, 0x04010C08, 0x7E000204, 0xE01C0000,
-	0x80800004, 0xBFB60003, 0xBFB00000, 0xBF9F0000,
-	0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
-	0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
-	0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
-	0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
-	0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
-	0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
-	0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
-	0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
-	0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
-	0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
-	0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
-	0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
-	0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
-	0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
-	0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
-	0xBF9F0000, 0xBF9F0000, 0xBF9F0000
-};
-
-static const struct reg_info bufferclear_cs_shader_registers_gfx11[] = {
-	{0x2e12, 0x600C0041},	//{ mmCOMPUTE_PGM_RSRC1,	  0x600C0041 },
-	{0x2e13, 0x00000090},	//{ mmCOMPUTE_PGM_RSRC2,	  0x00000090 },
-	{0x2e07, 0x00000040},	//{ mmCOMPUTE_NUM_THREAD_X, 0x00000040 },
-	{0x2e08, 0x00000001},	//{ mmCOMPUTE_NUM_THREAD_Y, 0x00000001 },
-	{0x2e09, 0x00000001},	//{ mmCOMPUTE_NUM_THREAD_Z, 0x00000001 }
-};
-
-static const uint32_t buffercopy_cs_shader_gfx11[] = {
-	0xB0802006, 0xBF840003, 0x360000FF, 0x000003FF,
-	0xBF870001, 0xD6460001, 0x04010C08, 0xE00C0000,
-	0x80800201, 0xBF8903F7, 0xE01C0000, 0x80810201,
-	0xBFB60003, 0xBFB00000, 0xBF9F0000, 0xBF9F0000,
-	0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
-	0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
-	0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
-	0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
-	0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
-	0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
-	0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
-	0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
-	0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
-	0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
-	0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
-	0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
-	0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
-	0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
-	0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
-	0xBF9F0000, 0xBF9F0000
-};
-
-static const uint32_t ps_const_shader_gfx11[] = {
-    0xB0802006, 0xBF840003, 0x7E000200, 0x7E020201,
-    0x7E040202, 0x7E060203, 0x5E000300, 0x5E020702,
-    0xBF800000, 0xBF800000, 0xF8000803, 0x00000100,
-    0xBFB00000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
-    0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
-    0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
-    0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
-    0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
-    0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
-    0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
-    0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
-    0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
-    0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
-    0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
-    0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
-    0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
-    0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
-    0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
-    0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
-    0xBF9F0000
-};
-
-#define ps_const_shader_patchinfo_code_size_gfx11 6
-
-static const uint32_t ps_const_shader_patchinfo_code_gfx11[][10][6] = {
-	{{ 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF8000890, 0x00000000 },  // SI_EXPORT_FMT_ZERO
-	{ 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF8000801, 0x00000000 },  // SI_EXPORT_FMT_32_R
-	{ 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF8000803, 0x00000100 },  // SI_EXPORT_FMT_32_GR
-	{ 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF8000803, 0x00000300 },  // SI_EXPORT_FMT_32_AR
-	{ 0x5E000300, 0x5E020702, 0xBF800000, 0xBF800000, 0xF8000803, 0x00000100 },  // SI_EXPORT_FMT_FP16_ABGR
-	{ 0xD7220000, 0x00020300, 0xD7220001, 0x00020702, 0xF8000803, 0x00000100 },  // SI_EXPORT_FMT_UNORM16_ABGR
-	{ 0xD7210000, 0x00020300, 0xD7210001, 0x00020702, 0xF8000803, 0x00000100 },  // SI_EXPORT_FMT_SNORM16_ABGR
-	{ 0xD7230000, 0x00020300, 0xD7230001, 0x00020702, 0xF8000803, 0x00000100 },  // SI_EXPORT_FMT_uint32_t16_ABGR
-	{ 0xD7240000, 0x00020300, 0xD7240001, 0x00020702, 0xF8000803, 0x00000100 },  // SI_EXPORT_FMT_SINT16_ABGR
-	{ 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF800080F, 0x03020100 }   // SI_EXPORT_FMT_32_ABGR
-	}
-};
-
-static const uint32_t ps_const_shader_patchinfo_offset_gfx11[] = {
-	0x00000006
-};
-
-#define ps_const_num_sh_registers_gfx11 2
-
-static const struct reg_info ps_const_sh_registers_gfx11[] = {
-	{0x2C0A, 0x020C0000}, //{ mmSPI_SHADER_PGM_RSRC1_PS, 0x020C0000 },
-	{0x2C0B, 0x00000008}, //{ mmSPI_SHADER_PGM_RSRC2_PS, 0x00000008 }
-};
-
-static const struct reg_info ps_const_context_registers_gfx11[] = {
-	{0xA1B4, 0x00000002 }, //{ mmSPI_PS_INPUT_ADDR,       0x00000002 },
-	{0xA1B6, 0x00000000 }, //{ mmSPI_PS_IN_CONTROL,       0x00000000 },
-	{0xA08F, 0x0000000F }, //{ mmCB_SHADER_MASK,          0x0000000F },
-	{0xA203, 0x00000010 }, //{ mmDB_SHADER_CONTROL,       0x00000010 },
-	{0xA1C4, 0x00000000 }, //{ mmSPI_SHADER_Z_FORMAT,     0x00000000 },
-	{0xA1B8, 0x00000000 }, //{ mmSPI_BARYC_CNTL,          0x00000000 /* Always 0 for now */},
-	{0xA1C5, 0x00000004 }, //{ mmSPI_SHADER_COL_FORMAT,   0x00000004 /* SI_EXPORT_FMT_FP16_ABGR */ }
-};
-
-#define ps_const_num_context_registers_gfx11 7
-
-static const uint32_t ps_tex_shader_gfx11[] =
-{
-    0xB0802006, 0xBF840003, 0xBEFD000C, 0xBE8E017E,
-    0xBEFE1D7E, 0xCE000003, 0xCE000102, 0xCD000104,
-    0x040E0103, 0xCD000000, 0x040A0102, 0xBF870112,
-    0xCD010703, 0x04120303, 0xCD010700, 0x04020302,
-    0x8BFE0E7E, 0xF06C0F05, 0x08000003, 0x00000000,
-    0xBEFE010E, 0xBF8903F7, 0x5E000300, 0x5E020702,
-    0xBF800000, 0xBF800000, 0xF8000803, 0x00000100,
-    0xBFB00000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
-    0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
-    0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
-    0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
-    0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
-    0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
-    0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
-    0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
-    0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
-    0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
-    0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
-    0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
-    0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
-    0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
-    0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
-    0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
-    0xBF9F0000
-};
-
-static const uint32_t ps_tex_shader_patchinfo_offset_gfx11[] =
-{
-    0x00000016
-};
-
-// Denotes the Patch Info Code Length
-#define ps_tex_shader_patchinfo_code_size_gfx11 6
-
-static const uint32_t ps_tex_shader_patchinfo_code_gfx11[][10][6] =
-{
-    {{ 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF8000890, 0x00000000 },  // SI_EXPORT_FMT_ZERO
-     { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF8000801, 0x00000000 },  // SI_EXPORT_FMT_32_R
-     { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF8000803, 0x00000100 },  // SI_EXPORT_FMT_32_GR
-     { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF8000803, 0x00000300 },  // SI_EXPORT_FMT_32_AR
-     { 0x5E000300, 0x5E020702, 0xBF800000, 0xBF800000, 0xF8000803, 0x00000100 },  // SI_EXPORT_FMT_FP16_ABGR
-     { 0xD7220000, 0x00020300, 0xD7220001, 0x00020702, 0xF8000803, 0x00000100 },  // SI_EXPORT_FMT_UNORM16_ABGR
-     { 0xD7210000, 0x00020300, 0xD7210001, 0x00020702, 0xF8000803, 0x00000100 },  // SI_EXPORT_FMT_SNORM16_ABGR
-     { 0xD7230000, 0x00020300, 0xD7230001, 0x00020702, 0xF8000803, 0x00000100 },  // SI_EXPORT_FMT_uint32_t16_ABGR
-     { 0xD7240000, 0x00020300, 0xD7240001, 0x00020702, 0xF8000803, 0x00000100 },  // SI_EXPORT_FMT_SINT16_ABGR
-     { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF800080F, 0x03020100 }   // SI_EXPORT_FMT_32_ABGR
-    }
-};
-// Holds Sh Register Information
-static const struct reg_info ps_tex_sh_registers_gfx11[] =
-{
-    {0x2C0A, 0x020C0081 }, //{ mmSPI_SHADER_PGM_RSRC1_PS, 0x020C0081 },
-    {0x2C0B, 0x00000018 } //{ mmSPI_SHADER_PGM_RSRC2_PS, 0x00000018 }
-};
-
-#define ps_tex_num_sh_registers_gfx11 2
-
-// Holds Context Register Information
-static const struct reg_info ps_tex_context_registers_gfx11[] =
-{
-    {0xA1B4, 0x00000002 }, //{ mmSPI_PS_INPUT_ADDR,       0x00000002 },
-    {0xA1B6, 0x00000001 }, //{ mmSPI_PS_IN_CONTROL,       0x00000001 },
-    {0xA08F, 0x0000000F }, //{ mmCB_SHADER_MASK,          0x0000000F },
-    {0xA203, 0x00000010 }, //{ mmDB_SHADER_CONTROL,       0x00000010 },
-    {0xA1C4, 0x00000000 }, //{ mmSPI_SHADER_Z_FORMAT,     0x00000000 },
-    {0xA1B8, 0x00000000 }, //{ mmSPI_BARYC_CNTL,          0x00000000 /* Always 0 for now */},
-    {0xA1C5, 0x00000004 } //{ mmSPI_SHADER_COL_FORMAT,   0x00000004 /* SI_EXPORT_FMT_FP16_ABGR */ }
-};
-
-#define ps_tex_num_context_registers_gfx11 7
-
-static const uint32_t vs_RectPosTexFast_shader_gfx11[] =
-{
-	0xB0802006, 0xBEFE01C1, 0xBF840003, 0xF408050A,
-	0xF80000B0, 0xD71F0001, 0x000100C1, 0x9300FF03,
-	0x00040018, 0x9301FF02, 0x0009000C, 0xBF870091,
-	0xD7200001, 0x000202C1, 0xD60B0001, 0x04058000,
-	0xBF870001, 0xD4490000, 0x00000301, 0xBE862100,
-	0x7E040B05, 0xBFA5001C, 0x7E06020A, 0x7E08020E,
-	0x7E0A020F, 0xBF8701B4, 0x060404F3, 0x7E140211,
-	0x7E0E0210, 0x7C240480, 0x060404F3, 0xD5010003,
-	0x01AA0608, 0xD5010004, 0x01AA080C, 0xBF870003,
-	0xD4120012, 0x00010102, 0x7E04020B, 0xBEEA1F12,
-	0xBF870483, 0xD5010008, 0x01AA080C, 0xD5010006,
-	0x01AA0608, 0xBF870003, 0xD5010004, 0x004A0409,
-	0xD5010009, 0x004A0A0D, 0xBEFE0106, 0x9302FF02,
-	0x00090016, 0xBF870009, 0xD4C9007E, 0x00000501,
-	0xBFA50002, 0xF8000941, 0x00000000, 0xBF89FFF0,
-	0x8BFE0006, 0xD71F0000, 0x000100C1, 0xBFA50013,
-	0x7E1602F2, 0x9300FF03, 0x00040018, 0x8B01FF05,
-	0x00007FFF, 0xBF8704B2, 0xD7200000, 0x000200C1,
-	0x7E0202F2, 0x84018901, 0x80018001, 0xBF870002,
-	0xD60B0000, 0x04018000, 0xF80008CF, 0x01070406,
-	0xBF89FC07, 0xE0744000, 0x01850800, 0xBFB00000,
-	0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
-	0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
-	0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
-	0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
-	0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
-	0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
-	0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
-	0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
-	0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
-	0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
-	0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
-	0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
-	0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
-	0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
-	0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
-	0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000
-};
-
-static const struct reg_info vs_RectPosTexFast_sh_registers_gfx11[] =
-{
-	{0x2C8A, 0x020C00C2}, //{ mmSPI_SHADER_PGM_RSRC1_GS, 0x020C00C2 },
-	{0x2C8B, 0x0008001C}, //{ mmSPI_SHADER_PGM_RSRC2_GS, 0x0008001C }
-};
-
-#define vs_RectPosTexFast_num_sh_registers_gfx11 2
-
-// Holds Context Register Information
-static const struct reg_info vs_RectPosTexFast_context_registers_gfx11[] =
-{
-	{0xA1B1, 0x00000000}, //{ mmSPI_VS_OUT_CONFIG, 0x00000000 },
-	{0xA1C2, 0x00000001}, //{ mmSPI_SHADER_IDX_FORMAT, 0x00000001 },
-	{0xA1C3, 0x00000000}, //{ mmSPI_SHADER_POS_FORMAT, 0x00000000 /* Always 0 for now */},
-	{0xA2E4, 0x00000000}, //{ mmVGT_GS_INSTANCE_CNT, 0x00000000 },
-	{0xA2AB, 0x00000004}, //{ mmVGT_ESGS_RING_ITEMSIZE, 0x00000004 },
-	{0xA2CE, 0x00000001}, //{ mmVGT_GS_MAX_VERT_OUT, 0x00000001 }
-};
-
-#define vs_RectPosTexFast_num_context_registers_gfx11 6
-
-static const uint32_t preamblecache_gfx11[] = {
-	0xc0026900, 0x81, 0x80000000, 0x40004000, 0xc0026900, 0x8c, 0xaa99aaaa, 0x0,
-	0xc0026900, 0x90, 0x80000000, 0x40004000, 0xc0026900, 0x94,  0x80000000, 0x40004000,
-	0xc0026900, 0xb4, 0x0, 0x3f800000, 0xc0016900, 0x103, 0x0, 0xc0016900, 0x208, 0x0,
-	0xc0016900, 0x2a1, 0x0, 0xc0016900,  0x2ad, 0x0, 0xc0016900, 0x2dc, 0x0,
-	0xc0066900, 0x2de, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
-	0xc0056900, 0x2f9, 0x5, 0x3f800000, 0x3f800000, 0x3f800000,  0x3f800000,
-	0xc0046900, 0x310, 0x0, 0x3, 0x0, 0x100000, 0xc0016900, 0x349, 0x0,
-	0xc0016900, 0x358, 0x0, 0xc0016900, 0x367, 0x0, 0xc0016900, 0x376,  0x0,
-	0xc0016900, 0x385, 0x0, 0xc0076900, 0x1e1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
-	0xc0026900, 0x204, 0x90000, 0x4, 0xc0016900, 0x20c, 0x0,  0xc0026900, 0x20e, 0x0, 0x0,
-	0xc0016900, 0x2b2, 0x0, 0xc0026900, 0x30e, 0xffffffff, 0xffffffff,
-	0xc0016900, 0x314, 0x0, 0xc0016900, 0x10a, 0x0,  0xc0016900, 0x2a6, 0x0,
-	0xc0016900, 0x210, 0x0, 0xc0016900, 0x2db, 0x0, 0xc0016900, 0x2e4, 0x0,
-	0xc0002f00, 0x1, 0xc0016900, 0x1, 0x0, 0xc0016900,  0x206, 0x300,
-	0xc0016900, 0x212, 0x200, 0xc0016900, 0xf4, 0x0, 0xc0016900, 0x18, 0x0,
-	0xc0016900, 0x1d4, 0xff, 0xc0016900, 0x2ce, 0x1, 0xc0016900, 0x2d3, 0x20001,
-	0xc0016900, 0x1ff, 0x80,  0xc0016900, 0x2d5, 0x6012010, 0xc0017a00, 0x20000243, 0x0,
-	0xc0017900, 0x249, 0x0, 0xc0017900, 0x24a, 0x0, 0xc0017900, 0x24b, 0x0,
-	0xc0017900,  0x259, 0xffffffff, 0xc0017900, 0x25f, 0x0, 0xc0017900, 0x260, 0x0,
-	0xc0017900, 0x262, 0x0, 0xc0017900, 0x444, 0x0, 0xc0017900, 0x445, 0x0,
-	0xc0017600, 0x6, 0x0, 0xc0017600, 0x80, 0x0, 0xc0017600, 0xb0, 0x0,
-	0xc0047600, 0xb2, 0x0, 0x0, 0x0, 0x0, 0xc0017600, 0x30, 0x0,
-	0xc0047600, 0x32, 0x0, 0x0, 0x0, 0x0
-};
-
-static const uint32_t cached_cmd_gfx11[] = {
-	0xc0016900, 0x0, 0x0, 0xc0026900, 0x3, 0x2a, 0x0,
-	0xc0046900, 0xa, 0x0, 0x0, 0x0, 0x200020,
-	0xc0016900, 0x83, 0xffff, 0xc0026900, 0x8e, 0xf, 0xf,
-	0xc0056900, 0x105, 0x0, 0x0, 0x0, 0x0, 0x0,
-	0xc0026900, 0x10b, 0x0, 0x0, 0xc0016900, 0x1e0, 0x0,
-	0xc0036900, 0x200, 0x0, 0x10000, 0xcc0011,
-	0xc0026900, 0x292, 0x20, 0x6020000,
-	0xc0026900, 0x2b0, 0x0, 0x0, 0xc0016900, 0x2f8, 0x0,
-	0xc0046900, 0x1d5, 0x0, 0x0, 0x0, 0x0, 0xc0016900, 0x104, 0x4a00005,
-	0xc0016900, 0x1f, 0xf2a0055, 0xc0017900, 0x266, 0x4
-};
-
-#define sh_reg_base_gfx11 0x2C00
-#define context_reg_base_gfx11 0xA000
-
-#endif

tests/amdgpu/shader_code_gfx9.h

@@ -1,205 +0,0 @@
-/*
- * Copyright 2022 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
-*/
-
-#ifndef _shader_code_gfx9_h_
-#define _shader_code_gfx9_h_
-
-static const uint32_t bufferclear_cs_shader_gfx9[] = {
-	0x260000ff, 0x000003ff, 0xd1fd0000, 0x04010c08,
-	0x7e020280, 0x7e040204, 0x7e060205, 0x7e080206,
-	0x7e0a0207, 0xe01c2000, 0x80000200, 0xbf8c0000,
-	0xbf810000
-};
-
-static const struct reg_info bufferclear_cs_shader_registers_gfx9[] = {
-	{0x2e12, 0x000C0041},	//{ mmCOMPUTE_PGM_RSRC1,	  0x000C0041 },
-	{0x2e13, 0x00000090},	//{ mmCOMPUTE_PGM_RSRC2,	  0x00000090 },
-	{0x2e07, 0x00000040},	//{ mmCOMPUTE_NUM_THREAD_X, 0x00000040 },
-	{0x2e08, 0x00000001},	//{ mmCOMPUTE_NUM_THREAD_Y, 0x00000001 },
-	{0x2e09, 0x00000001},	//{ mmCOMPUTE_NUM_THREAD_Z, 0x00000001 }
-};
-
-static const uint32_t buffercopy_cs_shader_gfx9[] = {
-	0x260000ff, 0x000003ff, 0xd1fd0000, 0x04010c08,
-	0x7e020280, 0xe00c2000, 0x80000200, 0xbf8c0f70,
-	0xe01c2000, 0x80010200, 0xbf810000
-};
-
-static const uint32_t ps_const_shader_gfx9[] = {
-	0x7E000200, 0x7E020201, 0x7E040202, 0x7E060203,
-	0xD2960000, 0x00020300, 0xD2960001, 0x00020702,
-	0xC4001C0F, 0x00000100, 0xBF810000
-};
-
-#define ps_const_shader_patchinfo_code_size_gfx9 6
-
-static const uint32_t ps_const_shader_patchinfo_code_gfx9[][10][6] = {
-    {{ 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xC4001890, 0x00000000 },
-     { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xC4001801, 0x00000000 },
-     { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xC4001803, 0x00000100 },
-     { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xC4001803, 0x00000300 },
-     { 0xD2960000, 0x00020300, 0xD2960001, 0x00020702, 0xC4001C0F, 0x00000100 },
-     { 0xD2950000, 0x00020300, 0xD2950001, 0x00020702, 0xC4001C0F, 0x00000100 },
-     { 0xD2940000, 0x00020300, 0xD2940001, 0x00020702, 0xC4001C0F, 0x00000100 },
-     { 0xD2970000, 0x00020300, 0xD2970001, 0x00020702, 0xC4001C0F, 0x00000100 },
-     { 0xD2980000, 0x00020300, 0xD2980001, 0x00020702, 0xC4001C0F, 0x00000100 },
-     { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xC400180F, 0x03020100 }
-    }
-};
-
-static const uint32_t ps_const_shader_patchinfo_offset_gfx9[] = {
-	0x00000004
-};
-
-#define ps_const_num_sh_registers_gfx9 2
-
-static const struct reg_info ps_const_sh_registers_gfx9[] = {
-	{0x2C0A, 0x000C0040},//{ mmSPI_SHADER_PGM_RSRC1_PS, 0x000C0040 },
-	{0x2C0B, 0x00000008}, //{ mmSPI_SHADER_PGM_RSRC2_PS, 0x00000008 }
-};
-
-#define ps_const_num_context_registers_gfx9 7
-
-static const struct reg_info ps_const_context_registers_gfx9[] = {
-    {0xA1B4, 0x00000002}, //{ mmSPI_PS_INPUT_ADDR,       0x00000002 },
-    {0xA1B6, 0x00000000}, //{ mmSPI_PS_IN_CONTROL,       0x00000000 },
-    {0xA08F, 0x0000000F}, //{ mmCB_SHADER_MASK,          0x0000000F },
-    {0xA203, 0x00000010}, //{ mmDB_SHADER_CONTROL,       0x00000010 },
-    {0xA1C4, 0x00000000}, //{ mmSPI_SHADER_Z_FORMAT,     0x00000000 },
-    {0xA1B8, 0x00000000}, //{ mmSPI_BARYC_CNTL,          0x00000000 /* Always 0 for now */},
-    {0xA1C5, 0x00000004}, //{ mmSPI_SHADER_COL_FORMAT,   0x00000004 }
-};
-
-static const uint32_t ps_tex_shader_gfx9[] = {
-    0xBEFC000C, 0xBE8E017E, 0xBEFE077E, 0xD4180000,
-    0xD4190001, 0xD41C0100, 0xD41D0101, 0xF0800F00,
-    0x00400206, 0xBEFE010E, 0xBF8C0F70, 0xD2960000,
-    0x00020702, 0xD2960001, 0x00020B04, 0xC4001C0F,
-    0x00000100, 0xBF810000
-};
-
-static const uint32_t ps_tex_shader_patchinfo_offset_gfx9[] = {
-    0x0000000B
-};
-
-#define ps_tex_shader_patchinfo_code_size_gfx9 6
-
-static const uint32_t ps_tex_shader_patchinfo_code_gfx9[][10][6] = {
-    {{ 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xC4001890, 0x00000000 },
-     { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xC4001801, 0x00000002 },
-     { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xC4001803, 0x00000302 },
-     { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xC4001803, 0x00000502 },
-     { 0xD2960000, 0x00020702, 0xD2960001, 0x00020B04, 0xC4001C0F, 0x00000100 },
-     { 0xD2950000, 0x00020702, 0xD2950001, 0x00020B04, 0xC4001C0F, 0x00000100 },
-     { 0xD2940000, 0x00020702, 0xD2940001, 0x00020B04, 0xC4001C0F, 0x00000100 },
-     { 0xD2970000, 0x00020702, 0xD2970001, 0x00020B04, 0xC4001C0F, 0x00000100 },
-     { 0xD2980000, 0x00020702, 0xD2980001, 0x00020B04, 0xC4001C0F, 0x00000100 },
-     { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xC400180F, 0x05040302 }
-    }
-};
-
-#define ps_tex_num_sh_registers_gfx9 2
-
-static const struct reg_info ps_tex_sh_registers_gfx9[] = {
-    {0x2C0A, 0x000C0081},//{ mmSPI_SHADER_PGM_RSRC1_PS, 0x000C0081 },
-    {0x2C0B, 0x00000018}, //{ mmSPI_SHADER_PGM_RSRC2_PS, 0x00000018 }
-};
-
-#define ps_tex_num_context_registers_gfx9 7
-
-static const struct reg_info ps_tex_context_registers_gfx9[] = {
-    {0xA1B4, 0x00000002}, //{ mmSPI_PS_INPUT_ADDR,       0x00000002 },
-    {0xA1B6, 0x00000001}, //{ mmSPI_PS_IN_CONTROL,       0x00000001 },
-    {0xA08F, 0x0000000F}, //{ mmCB_SHADER_MASK,          0x0000000F },
-    {0xA203, 0x00000010}, //{ mmDB_SHADER_CONTROL,       0x00000010 },
-    {0xA1C4, 0x00000000}, //{ mmSPI_SHADER_Z_FORMAT,     0x00000000 },
-    {0xA1B8, 0x00000000}, //{ mmSPI_BARYC_CNTL,          0x00000000 /* Always 0 for now */},
-    {0xA1C5, 0x00000004}, //{ mmSPI_SHADER_COL_FORMAT,   0x00000004  }
-};
-
-static const uint32_t vs_RectPosTexFast_shader_gfx9[] = {
-    0x7E000B00, 0x020000F3, 0xD042000A, 0x00010100,
-    0x7E020202, 0x7E040200, 0x020000F3, 0x7E060206,
-    0x7E080204, 0xD1000001, 0x002A0302, 0x7C840080,
-    0x7E000200, 0x7E040203, 0x7E0A0201, 0xD1000003,
-    0x002A0704, 0x7E0C0207, 0x7E0E0205, 0x00000101,
-    0x00020505, 0x7E040208, 0x7E0A02F2, 0x00060903,
-    0x00080D07, 0x7E0C0209, 0xC40008CF, 0x05020100,
-    0xC400020F, 0x05060403, 0xBF810000
-};
-
-static const struct reg_info vs_RectPosTexFast_sh_registers_gfx9[] =
-{
-    {0x2C4A, 0x000C0081}, //{ mmSPI_SHADER_PGM_RSRC1_VS, 0x000C0081 },
-    {0x2C4B, 0x00000018}, //{ mmSPI_SHADER_PGM_RSRC2_VS, 0x00000018 }
-};
-
-#define vs_RectPosTexFast_num_sh_registers_gfx9 2
-
-// Holds Context Register Information
-static const struct reg_info vs_RectPosTexFast_context_registers_gfx9[] =
-{
-    {0xA1B1, 0x00000000}, //{ mmSPI_VS_OUT_CONFIG, 0x00000000 },
-    {0xA1C3, 0x00000000}, //{ mmSPI_SHADER_POS_FORMAT, 0x00000000 /* Always 0 for now */}
-};
-
-#define vs_RectPosTexFast_num_context_registers_gfx9 2
-
-static const uint32_t preamblecache_gfx9[] = {
-	0xc0026900, 0x81, 0x80000000, 0x40004000, 0xc0026900, 0x8c, 0xaa99aaaa, 0x0,
-	0xc0026900, 0x90, 0x80000000, 0x40004000, 0xc0026900, 0x94, 0x80000000, 0x40004000,
-	0xc0026900, 0xb4,  0x0, 0x3f800000, 0xc0016900, 0x103, 0x0,
-	0xc0016900, 0x208, 0x0, 0xc0016900, 0x290, 0x0,
-	0xc0016900, 0x2a1, 0x0, 0xc0026900, 0x2ad, 0x0, 0x0,
-	0xc0016900, 0x2d5, 0x10000, 0xc0016900,  0x2dc, 0x0,
-	0xc0066900, 0x2de, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xc0026900, 0x2e5, 0x0, 0x0,
-	0xc0056900, 0x2f9, 0x5, 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000,
-	0xc0036900, 0x311, 0x3, 0, 0x100000, 0xc0026900, 0x316, 0x1e, 0x20,
-	0xc0016900, 0x349, 0x0, 0xc0016900, 0x358, 0x0, 0xc0016900, 0x367, 0x0,
-	0xc0016900, 0x376, 0x0, 0xc0016900, 0x385, 0x0, 0xc0016900, 0x19, 0x0,
-	0xc0056900, 0xe8, 0x0, 0x0, 0x0, 0x0, 0x0,
-	0xc0076900, 0x1e1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
-	0xc0026900, 0x204, 0x90000, 0x4, 0xc0046900, 0x20c, 0x0, 0x0, 0x0, 0x0,
-	0xc0016900, 0x2b2, 0x0, 0xc0026900, 0x30e, 0xffffffff, 0xffffffff,
-	0xc0016900, 0x314, 0x0, 0xc0016900, 0x2a6, 0, 0xc0016900, 0x210, 0,
-	0xc0002f00, 0x1, 0xc0016900, 0x1, 0x1,
-	0xc0016900, 0x18, 0x2, 0xc0016900, 0x206, 0x300, 0xc0017900, 0x20000243, 0x0,
-	0xc0017900, 0x248, 0xffffffff, 0xc0017900, 0x249, 0x0, 0xc0017900, 0x24a, 0x0,
-	0xc0017900, 0x24b, 0x0
-};
-
-static const uint32_t cached_cmd_gfx9[] = {
-	0xc0016900, 0x0, 0x0, 0xc0026900, 0x3, 0x2a, 0x0,
-	0xc0046900, 0xa, 0x0, 0x0, 0x0, 0x200020,
-	0xc0016900, 0x83, 0xffff, 0xc0026900, 0x8e, 0xf, 0xf,
-	0xc0056900, 0x105, 0x0, 0x0,  0x0, 0x0, 0x12,
-	0xc0026900, 0x10b, 0x0, 0x0, 0xc0016900, 0x1e0, 0x0,
-	0xc0036900, 0x200, 0x0, 0x10000, 0xcc0011,
-	0xc0026900, 0x292, 0x20, 0x60201b8,
-	0xc0026900, 0x2b0, 0x0, 0x0, 0xc0016900, 0x2f8, 0x0
-};
-
-#define sh_reg_base_gfx9 0x2C00
-#define context_reg_base_gfx9 0xA000
-
-#endif

tests/amdgpu/shader_code_hang.h

@@ -1,104 +0,0 @@
-/*
- * Copyright 2022 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
-*/
-
-#ifndef _shader_code_hang_h_
-#define _shader_code_hang_h_
-
-static const unsigned int memcpy_shader_hang[] = {
-        0xFFFFFFFF, 0xBEFE0A7E, 0xBEFC0304, 0xC0C20100,
-        0xC0800300, 0xC8080000, 0xC80C0100, 0xC8090001,
-        0xC80D0101, 0xBF8C007F, 0xF0800F00, 0x00010002,
-        0xBEFE040C, 0xBF8C0F70, 0xBF800000, 0xBF800000,
-        0xF800180F, 0x03020100, 0xBF810000
-};
-
-struct shader_test_shader_bin {
-	const uint32_t *shader;
-	uint32_t header_length;
-	uint32_t body_length;
-	uint32_t foot_length;
-};
-
-static const unsigned int memcpy_cs_hang_slow_ai_codes[] = {
-    0xd1fd0000, 0x04010c08, 0xe00c2000, 0x80000100,
-    0xbf8c0f70, 0xe01c2000, 0x80010100, 0xbf810000
-};
-
-static struct shader_test_shader_bin memcpy_cs_hang_slow_ai = {
-        memcpy_cs_hang_slow_ai_codes, 4, 3, 1
-};
-
-static const unsigned int memcpy_cs_hang_slow_rv_codes[] = {
-    0x8e00860c, 0x32000000, 0xe00c2000, 0x80010100,
-    0xbf8c0f70, 0xe01c2000, 0x80020100, 0xbf810000
-};
-
-static struct shader_test_shader_bin memcpy_cs_hang_slow_rv = {
-        memcpy_cs_hang_slow_rv_codes, 4, 3, 1
-};
-
-static const unsigned int memcpy_cs_hang_slow_nv_codes[] = {
-    0xd7460000, 0x04010c08, 0xe00c2000, 0x80000100,
-    0xbf8c0f70, 0xe01ca000, 0x80010100, 0xbf810000
-};
-
-static struct shader_test_shader_bin memcpy_cs_hang_slow_nv = {
-        memcpy_cs_hang_slow_nv_codes, 4, 3, 1
-};
-
-
-static const unsigned int memcpy_ps_hang_slow_ai_codes[] = {
-	0xbefc000c, 0xbe8e017e, 0xbefe077e, 0xd4080000,
-	0xd4090001, 0xd40c0100, 0xd40d0101, 0xf0800f00,
-	0x00400002, 0xbefe010e, 0xbf8c0f70, 0xbf800000,
-	0xbf800000, 0xbf800000, 0xbf800000, 0xc400180f,
-	0x03020100, 0xbf810000
-};
-
-static struct shader_test_shader_bin memcpy_ps_hang_slow_ai = {
-        memcpy_ps_hang_slow_ai_codes, 7, 2, 9
-};
-
-static const unsigned int memcpy_ps_hang_slow_navi10_codes[] = {
-	0xBEFC030C,0xBE8E047E,0xBEFE0A7E,0xC8080000,
-	0xC80C0100,0xC8090001,0xC80D0101,0xF0800F0A,
-	0x00400402,0x00000003,0xBEFE040E,0xBF8C0F70,
-	0xBF800000,0xBF800000,0xBF800000,0xBF800000,
-	0xF800180F,0x07060504,0xBF810000
-};
-
-static struct shader_test_shader_bin memcpy_ps_hang_slow_navi10 = {
-	memcpy_ps_hang_slow_navi10_codes, 7, 3, 9
-};
-
-static const unsigned int memcpy_ps_hang_slow_navi21_codes[] = {
-    0xBEFC030C, 0xBE8E047E, 0xBEFE0A7E, 0xC8080000, 0xC8000100, 0xC8090001, 0xC8010101, 0x87FE0E7E, // header
-    0xF0800F0A, 0x00400002, 0x00000000, // body - image_sample instruction
-    0xBFA3FFE3, 0xBEFE040E, 0xBF8C3F70, 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF800180F, 0x03020100, 0xBF810000 // footer
-};
-
-static struct shader_test_shader_bin memcpy_ps_hang_slow_navi21 = {
-	memcpy_ps_hang_slow_navi21_codes, 8, 3, 10
-};
-
-#endif

tests/amdgpu/syncobj_tests.c

@@ -1,314 +0,0 @@
-/*
- * Copyright 2017 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
-*/
-
-#include "CUnit/Basic.h"
-#include "xf86drm.h"
-
-#include "amdgpu_test.h"
-#include "amdgpu_drm.h"
-#include "amdgpu_internal.h"
-#include <pthread.h>
-
-static  amdgpu_device_handle device_handle;
-static  uint32_t  major_version;
-static  uint32_t  minor_version;
-
-static  uint32_t  family_id;
-static  uint32_t  chip_id;
-static  uint32_t  chip_rev;
-
-static void amdgpu_syncobj_timeline_test(void);
-
-CU_BOOL suite_syncobj_timeline_tests_enable(void)
-{
-	int r;
-	uint64_t cap = 0;
-
-	r = drmGetCap(drm_amdgpu[0], DRM_CAP_SYNCOBJ_TIMELINE, &cap);
-	if (r || cap == 0)
-		return CU_FALSE;
-
-	return CU_TRUE;
-}
-
-int suite_syncobj_timeline_tests_init(void)
-{
-	int r;
-
-	r = amdgpu_device_initialize(drm_amdgpu[0], &major_version,
-				   &minor_version, &device_handle);
-
-	if (r) {
-		if ((r == -EACCES) && (errno == EACCES))
-			printf("\n\nError:%s. "
-				"Hint:Try to run this test program as root.",
-				strerror(errno));
-		return CUE_SINIT_FAILED;
-	}
-
-	return CUE_SUCCESS;
-}
-
-int suite_syncobj_timeline_tests_clean(void)
-{
-	int r = amdgpu_device_deinitialize(device_handle);
-
-	if (r == 0)
-		return CUE_SUCCESS;
-	else
-		return CUE_SCLEAN_FAILED;
-}
-
-
-CU_TestInfo syncobj_timeline_tests[] = {
-	{ "syncobj timeline test",  amdgpu_syncobj_timeline_test },
-	CU_TEST_INFO_NULL,
-};
-
-#define GFX_COMPUTE_NOP  0xffff1000
-#define SDMA_NOP  0x0
-static int syncobj_command_submission_helper(uint32_t syncobj_handle, bool
-					     wait_or_signal, uint64_t point)
-{
-	amdgpu_context_handle context_handle;
-	amdgpu_bo_handle ib_result_handle;
-	void *ib_result_cpu;
-	uint64_t ib_result_mc_address;
-	struct drm_amdgpu_cs_chunk chunks[2];
-	struct drm_amdgpu_cs_chunk_data chunk_data;
-	struct drm_amdgpu_cs_chunk_syncobj syncobj_data;
-	struct amdgpu_cs_fence fence_status;
-	amdgpu_bo_list_handle bo_list;
-	amdgpu_va_handle va_handle;
-	uint32_t expired;
-	int i, r;
-	uint64_t seq_no;
-	static uint32_t *ptr;
-	struct amdgpu_gpu_info gpu_info = {0};
-	unsigned gc_ip_type;
-
-	r = amdgpu_query_gpu_info(device_handle, &gpu_info);
-	CU_ASSERT_EQUAL(r, 0);
-
-	family_id = device_handle->info.family_id;
-	chip_id = device_handle->info.chip_external_rev;
-	chip_rev = device_handle->info.chip_rev;
-
-	gc_ip_type = (asic_is_gfx_pipe_removed(family_id, chip_id, chip_rev)) ?
-			AMDGPU_HW_IP_COMPUTE : AMDGPU_HW_IP_GFX;
-
-	r = amdgpu_cs_ctx_create(device_handle, &context_handle);
-	CU_ASSERT_EQUAL(r, 0);
-
-	r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096,
-				    AMDGPU_GEM_DOMAIN_GTT, 0,
-				    &ib_result_handle, &ib_result_cpu,
-				    &ib_result_mc_address, &va_handle);
-	CU_ASSERT_EQUAL(r, 0);
-
-	r = amdgpu_get_bo_list(device_handle, ib_result_handle, NULL,
-			       &bo_list);
-	CU_ASSERT_EQUAL(r, 0);
-
-	ptr = ib_result_cpu;
-
-	for (i = 0; i < 16; ++i)
-		ptr[i] = wait_or_signal ? GFX_COMPUTE_NOP: SDMA_NOP;
-
-	chunks[0].chunk_id = AMDGPU_CHUNK_ID_IB;
-	chunks[0].length_dw = sizeof(struct drm_amdgpu_cs_chunk_ib) / 4;
-	chunks[0].chunk_data = (uint64_t)(uintptr_t)&chunk_data;
-	chunk_data.ib_data._pad = 0;
-	chunk_data.ib_data.va_start = ib_result_mc_address;
-	chunk_data.ib_data.ib_bytes = 16 * 4;
-	chunk_data.ib_data.ip_type = wait_or_signal ? gc_ip_type :
-		AMDGPU_HW_IP_DMA;
-	chunk_data.ib_data.ip_instance = 0;
-	chunk_data.ib_data.ring = 0;
-	chunk_data.ib_data.flags = AMDGPU_IB_FLAG_EMIT_MEM_SYNC;
-
-	chunks[1].chunk_id = wait_or_signal ?
-		AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT :
-		AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL;
-	chunks[1].length_dw = sizeof(struct drm_amdgpu_cs_chunk_syncobj) / 4;
-	chunks[1].chunk_data = (uint64_t)(uintptr_t)&syncobj_data;
-	syncobj_data.handle = syncobj_handle;
-	syncobj_data.point = point;
-	syncobj_data.flags = DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT;
-
-	r = amdgpu_cs_submit_raw(device_handle,
-				 context_handle,
-				 bo_list,
-				 2,
-				 chunks,
-				 &seq_no);
-	CU_ASSERT_EQUAL(r, 0);
-
-
-	memset(&fence_status, 0, sizeof(struct amdgpu_cs_fence));
-	fence_status.context = context_handle;
-	fence_status.ip_type = wait_or_signal ? gc_ip_type :
-		AMDGPU_HW_IP_DMA;
-	fence_status.ip_instance = 0;
-	fence_status.ring = 0;
-	fence_status.fence = seq_no;
-
-	r = amdgpu_cs_query_fence_status(&fence_status,
-			AMDGPU_TIMEOUT_INFINITE,0, &expired);
-	CU_ASSERT_EQUAL(r, 0);
-
-	r = amdgpu_bo_list_destroy(bo_list);
-	CU_ASSERT_EQUAL(r, 0);
-
-	r = amdgpu_bo_unmap_and_free(ib_result_handle, va_handle,
-				     ib_result_mc_address, 4096);
-	CU_ASSERT_EQUAL(r, 0);
-
-	r = amdgpu_cs_ctx_free(context_handle);
-	CU_ASSERT_EQUAL(r, 0);
-
-	return r;
-}
-
-struct syncobj_point {
-	uint32_t syncobj_handle;
-	uint64_t point;
-};
-
-static void *syncobj_wait(void *data)
-{
-	struct syncobj_point *sp = (struct syncobj_point *)data;
-	int r;
-
-	r = syncobj_command_submission_helper(sp->syncobj_handle, true,
-					      sp->point);
-	CU_ASSERT_EQUAL(r, 0);
-
-	return (void *)(long)r;
-}
-
-static void *syncobj_signal(void *data)
-{
-	struct syncobj_point *sp = (struct syncobj_point *)data;
-	int r;
-
-	r = syncobj_command_submission_helper(sp->syncobj_handle, false,
-					      sp->point);
-	CU_ASSERT_EQUAL(r, 0);
-
-	return (void *)(long)r;
-}
-
-static void amdgpu_syncobj_timeline_test(void)
-{
-	static pthread_t wait_thread;
-	static pthread_t signal_thread;
-	static pthread_t c_thread;
-	struct syncobj_point sp1, sp2, sp3;
-	uint32_t syncobj_handle;
-	uint64_t payload;
-	uint64_t wait_point, signal_point;
-	uint64_t timeout;
-	struct timespec tp;
-	int r, sync_fd;
-	void *tmp;
-
-	r =  amdgpu_cs_create_syncobj2(device_handle, 0, &syncobj_handle);
-	CU_ASSERT_EQUAL(r, 0);
-
-	// wait on point 5
-	sp1.syncobj_handle = syncobj_handle;
-	sp1.point = 5;
-	r = pthread_create(&wait_thread, NULL, syncobj_wait, &sp1);
-	CU_ASSERT_EQUAL(r, 0);
-
-	// signal on point 10
-	sp2.syncobj_handle = syncobj_handle;
-	sp2.point = 10;
-	r = pthread_create(&signal_thread, NULL, syncobj_signal, &sp2);
-	CU_ASSERT_EQUAL(r, 0);
-
-	r = pthread_join(wait_thread, &tmp);
-	CU_ASSERT_EQUAL(r, 0);
-	CU_ASSERT_EQUAL(tmp, 0);
-
-	r = pthread_join(signal_thread, &tmp);
-	CU_ASSERT_EQUAL(r, 0);
-	CU_ASSERT_EQUAL(tmp, 0);
-
-	//query timeline payload
-	r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
-				    &payload, 1);
-	CU_ASSERT_EQUAL(r, 0);
-	CU_ASSERT_EQUAL(payload, 10);
-
-	//signal on point 16
-	sp3.syncobj_handle = syncobj_handle;
-	sp3.point = 16;
-	r = pthread_create(&c_thread, NULL, syncobj_signal, &sp3);
-	CU_ASSERT_EQUAL(r, 0);
-	//CPU wait on point 16
-	wait_point = 16;
-	timeout = 0;
-	clock_gettime(CLOCK_MONOTONIC, &tp);
-	timeout = tp.tv_sec * 1000000000ULL + tp.tv_nsec;
-	timeout += 0x10000000000; //10s
-	r = amdgpu_cs_syncobj_timeline_wait(device_handle, &syncobj_handle,
-					    &wait_point, 1, timeout,
-					    DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL |
-					    DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
-					    NULL);
-
-	CU_ASSERT_EQUAL(r, 0);
-	r = pthread_join(c_thread, &tmp);
-	CU_ASSERT_EQUAL(r, 0);
-	CU_ASSERT_EQUAL(tmp, 0);
-
-	// export point 16 and import to point 18
-	r = amdgpu_cs_syncobj_export_sync_file2(device_handle, syncobj_handle,
-						16,
-						DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
-						&sync_fd);
-	CU_ASSERT_EQUAL(r, 0);
-	r = amdgpu_cs_syncobj_import_sync_file2(device_handle, syncobj_handle,
-						18, sync_fd);
-	CU_ASSERT_EQUAL(r, 0);
-	r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
-				    &payload, 1);
-	CU_ASSERT_EQUAL(r, 0);
-	CU_ASSERT_EQUAL(payload, 18);
-
-	// CPU signal on point 20
-	signal_point = 20;
-	r = amdgpu_cs_syncobj_timeline_signal(device_handle, &syncobj_handle,
-					      &signal_point, 1);
-	CU_ASSERT_EQUAL(r, 0);
-	r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
-				    &payload, 1);
-	CU_ASSERT_EQUAL(r, 0);
-	CU_ASSERT_EQUAL(payload, 20);
-
-	r = amdgpu_cs_destroy_syncobj(device_handle, syncobj_handle);
-	CU_ASSERT_EQUAL(r, 0);
-
-}

tests/amdgpu/uvd_enc_tests.c

@@ -1,491 +0,0 @@
-/*
- * Copyright 2017 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
-*/
-
-#include <stdio.h>
-#include <inttypes.h>
-
-#include "CUnit/Basic.h"
-
-#include "util_math.h"
-
-#include "amdgpu_test.h"
-#include "amdgpu_drm.h"
-#include "amdgpu_internal.h"
-#include "frame.h"
-#include "uve_ib.h"
-
-#define IB_SIZE		4096
-#define MAX_RESOURCES	16
-
-struct amdgpu_uvd_enc_bo {
-	amdgpu_bo_handle handle;
-	amdgpu_va_handle va_handle;
-	uint64_t addr;
-	uint64_t size;
-	uint8_t *ptr;
-};
-
-struct amdgpu_uvd_enc {
-	unsigned width;
-	unsigned height;
-	struct amdgpu_uvd_enc_bo session;
-	struct amdgpu_uvd_enc_bo vbuf;
-	struct amdgpu_uvd_enc_bo bs;
-	struct amdgpu_uvd_enc_bo fb;
-	struct amdgpu_uvd_enc_bo cpb;
-};
-
-static amdgpu_device_handle device_handle;
-static uint32_t major_version;
-static uint32_t minor_version;
-static uint32_t family_id;
-
-static amdgpu_context_handle context_handle;
-static amdgpu_bo_handle ib_handle;
-static amdgpu_va_handle ib_va_handle;
-static uint64_t ib_mc_address;
-static uint32_t *ib_cpu;
-
-static struct amdgpu_uvd_enc enc;
-static amdgpu_bo_handle resources[MAX_RESOURCES];
-static unsigned num_resources;
-
-static void amdgpu_cs_uvd_enc_create(void);
-static void amdgpu_cs_uvd_enc_session_init(void);
-static void amdgpu_cs_uvd_enc_encode(void);
-static void amdgpu_cs_uvd_enc_destroy(void);
-
-
-CU_TestInfo uvd_enc_tests[] = {
-	{ "UVD ENC create",  amdgpu_cs_uvd_enc_create },
-	{ "UVD ENC session init",  amdgpu_cs_uvd_enc_session_init },
-	{ "UVD ENC encode",  amdgpu_cs_uvd_enc_encode },
-	{ "UVD ENC destroy",  amdgpu_cs_uvd_enc_destroy },
-	CU_TEST_INFO_NULL,
-};
-
-CU_BOOL suite_uvd_enc_tests_enable(void)
-{
-	int r;
-	struct drm_amdgpu_info_hw_ip info;
-
-	if (amdgpu_device_initialize(drm_amdgpu[0], &major_version,
-					     &minor_version, &device_handle))
-		return CU_FALSE;
-
-	r = amdgpu_query_hw_ip_info(device_handle, AMDGPU_HW_IP_UVD_ENC, 0, &info);
-
-	if (amdgpu_device_deinitialize(device_handle))
-		return CU_FALSE;
-
-	if (!info.available_rings)
-		printf("\n\nThe ASIC NOT support UVD ENC, suite disabled.\n");
-
-	return (r == 0 && (info.available_rings ? CU_TRUE : CU_FALSE));
-}
-
-
-int suite_uvd_enc_tests_init(void)
-{
-	int r;
-
-	r = amdgpu_device_initialize(drm_amdgpu[0], &major_version,
-				     &minor_version, &device_handle);
-	if (r)
-		return CUE_SINIT_FAILED;
-
-	family_id = device_handle->info.family_id;
-
-	r = amdgpu_cs_ctx_create(device_handle, &context_handle);
-	if (r)
-		return CUE_SINIT_FAILED;
-
-	r = amdgpu_bo_alloc_and_map(device_handle, IB_SIZE, 4096,
-				    AMDGPU_GEM_DOMAIN_GTT, 0,
-				    &ib_handle, (void**)&ib_cpu,
-				    &ib_mc_address, &ib_va_handle);
-	if (r)
-		return CUE_SINIT_FAILED;
-
-	return CUE_SUCCESS;
-}
-
-int suite_uvd_enc_tests_clean(void)
-{
-	int r;
-
-	r = amdgpu_bo_unmap_and_free(ib_handle, ib_va_handle,
-				     ib_mc_address, IB_SIZE);
-	if (r)
-		return CUE_SCLEAN_FAILED;
-
-	r = amdgpu_cs_ctx_free(context_handle);
-	if (r)
-		return CUE_SCLEAN_FAILED;
-
-	r = amdgpu_device_deinitialize(device_handle);
-	if (r)
-		return CUE_SCLEAN_FAILED;
-
-	return CUE_SUCCESS;
-}
-
-static int submit(unsigned ndw, unsigned ip)
-{
-	struct amdgpu_cs_request ibs_request = {0};
-	struct amdgpu_cs_ib_info ib_info = {0};
-	struct amdgpu_cs_fence fence_status = {0};
-	uint32_t expired;
-	int r;
-
-	ib_info.ib_mc_address = ib_mc_address;
-	ib_info.size = ndw;
-
-	ibs_request.ip_type = ip;
-
-	r = amdgpu_bo_list_create(device_handle, num_resources, resources,
-				  NULL, &ibs_request.resources);
-	if (r)
-		return r;
-
-	ibs_request.number_of_ibs = 1;
-	ibs_request.ibs = &ib_info;
-	ibs_request.fence_info.handle = NULL;
-
-	r = amdgpu_cs_submit(context_handle, 0, &ibs_request, 1);
-	if (r)
-		return r;
-
-	r = amdgpu_bo_list_destroy(ibs_request.resources);
-	if (r)
-		return r;
-
-	fence_status.context = context_handle;
-	fence_status.ip_type = ip;
-	fence_status.fence = ibs_request.seq_no;
-
-	r = amdgpu_cs_query_fence_status(&fence_status,
-					 AMDGPU_TIMEOUT_INFINITE,
-					 0, &expired);
-	if (r)
-		return r;
-
-	return 0;
-}
-
-static void alloc_resource(struct amdgpu_uvd_enc_bo *uvd_enc_bo,
-			unsigned size, unsigned domain)
-{
-	struct amdgpu_bo_alloc_request req = {0};
-	amdgpu_bo_handle buf_handle;
-	amdgpu_va_handle va_handle;
-	uint64_t va = 0;
-	int r;
-
-	req.alloc_size = ALIGN(size, 4096);
-	req.preferred_heap = domain;
-	r = amdgpu_bo_alloc(device_handle, &req, &buf_handle);
-	CU_ASSERT_EQUAL(r, 0);
-	r = amdgpu_va_range_alloc(device_handle,
-				  amdgpu_gpu_va_range_general,
-				  req.alloc_size, 1, 0, &va,
-				  &va_handle, 0);
-	CU_ASSERT_EQUAL(r, 0);
-	r = amdgpu_bo_va_op(buf_handle, 0, req.alloc_size, va, 0,
-			    AMDGPU_VA_OP_MAP);
-	CU_ASSERT_EQUAL(r, 0);
-	uvd_enc_bo->addr = va;
-	uvd_enc_bo->handle = buf_handle;
-	uvd_enc_bo->size = req.alloc_size;
-	uvd_enc_bo->va_handle = va_handle;
-	r = amdgpu_bo_cpu_map(uvd_enc_bo->handle, (void **)&uvd_enc_bo->ptr);
-	CU_ASSERT_EQUAL(r, 0);
-	memset(uvd_enc_bo->ptr, 0, size);
-	r = amdgpu_bo_cpu_unmap(uvd_enc_bo->handle);
-	CU_ASSERT_EQUAL(r, 0);
-}
-
-static void free_resource(struct amdgpu_uvd_enc_bo *uvd_enc_bo)
-{
-	int r;
-
-	r = amdgpu_bo_va_op(uvd_enc_bo->handle, 0, uvd_enc_bo->size,
-			    uvd_enc_bo->addr, 0, AMDGPU_VA_OP_UNMAP);
-	CU_ASSERT_EQUAL(r, 0);
-
-	r = amdgpu_va_range_free(uvd_enc_bo->va_handle);
-	CU_ASSERT_EQUAL(r, 0);
-
-	r = amdgpu_bo_free(uvd_enc_bo->handle);
-	CU_ASSERT_EQUAL(r, 0);
-	memset(uvd_enc_bo, 0, sizeof(*uvd_enc_bo));
-}
-
-static void amdgpu_cs_uvd_enc_create(void)
-{
-	enc.width = 160;
-	enc.height = 128;
-
-	num_resources  = 0;
-	alloc_resource(&enc.session, 128 * 1024, AMDGPU_GEM_DOMAIN_GTT);
-	resources[num_resources++] = enc.session.handle;
-	resources[num_resources++] = ib_handle;
-}
-
-static void check_result(struct amdgpu_uvd_enc *enc)
-{
-	uint64_t sum;
-	uint32_t s = 175602;
-	uint32_t *ptr, size;
-	int j, r;
-
-	r = amdgpu_bo_cpu_map(enc->fb.handle, (void **)&enc->fb.ptr);
-	CU_ASSERT_EQUAL(r, 0);
-	ptr = (uint32_t *)enc->fb.ptr;
-	size = ptr[6];
-	r = amdgpu_bo_cpu_unmap(enc->fb.handle);
-	CU_ASSERT_EQUAL(r, 0);
-	r = amdgpu_bo_cpu_map(enc->bs.handle, (void **)&enc->bs.ptr);
-	CU_ASSERT_EQUAL(r, 0);
-	for (j = 0, sum = 0; j < size; ++j)
-		sum += enc->bs.ptr[j];
-	CU_ASSERT_EQUAL(sum, s);
-	r = amdgpu_bo_cpu_unmap(enc->bs.handle);
-	CU_ASSERT_EQUAL(r, 0);
-
-}
-
-static void amdgpu_cs_uvd_enc_session_init(void)
-{
-	int len, r;
-
-	len = 0;
-	memcpy((ib_cpu + len), uve_session_info, sizeof(uve_session_info));
-	len += sizeof(uve_session_info) / 4;
-	ib_cpu[len++] = enc.session.addr >> 32;
-	ib_cpu[len++] = enc.session.addr;
-
-	memcpy((ib_cpu + len), uve_task_info, sizeof(uve_task_info));
-	len += sizeof(uve_task_info) / 4;
-	ib_cpu[len++] = 0x000000d8;
-	ib_cpu[len++] = 0x00000000;
-	ib_cpu[len++] = 0x00000000;
-
-	memcpy((ib_cpu + len), uve_op_init, sizeof(uve_op_init));
-	len += sizeof(uve_op_init) / 4;
-
-	memcpy((ib_cpu + len), uve_session_init, sizeof(uve_session_init));
-	len += sizeof(uve_session_init) / 4;
-
-	memcpy((ib_cpu + len), uve_layer_ctrl, sizeof(uve_layer_ctrl));
-	len += sizeof(uve_layer_ctrl) / 4;
-
-	memcpy((ib_cpu + len), uve_slice_ctrl, sizeof(uve_slice_ctrl));
-	len += sizeof(uve_slice_ctrl) / 4;
-
-	memcpy((ib_cpu + len), uve_spec_misc, sizeof(uve_spec_misc));
-	len += sizeof(uve_spec_misc) / 4;
-
-	memcpy((ib_cpu + len), uve_rc_session_init, sizeof(uve_rc_session_init));
-	len += sizeof(uve_rc_session_init) / 4;
-
-	memcpy((ib_cpu + len), uve_deblocking_filter, sizeof(uve_deblocking_filter));
-	len += sizeof(uve_deblocking_filter) / 4;
-
-	memcpy((ib_cpu + len), uve_quality_params, sizeof(uve_quality_params));
-	len += sizeof(uve_quality_params) / 4;
-
-	memcpy((ib_cpu + len), uve_op_init_rc, sizeof(uve_op_init_rc));
-	len += sizeof(uve_op_init_rc) / 4;
-
-	memcpy((ib_cpu + len), uve_op_init_rc_vbv_level, sizeof(uve_op_init_rc_vbv_level));
-	len += sizeof(uve_op_init_rc_vbv_level) / 4;
-
-	r = submit(len, AMDGPU_HW_IP_UVD_ENC);
-	CU_ASSERT_EQUAL(r, 0);
-}
-
-static void amdgpu_cs_uvd_enc_encode(void)
-{
-	int len, r, i;
-	uint64_t luma_offset, chroma_offset;
-	uint32_t vbuf_size, bs_size = 0x003f4800, cpb_size;
-	unsigned align = (family_id >= AMDGPU_FAMILY_AI) ? 256 : 16;
-	vbuf_size = ALIGN(enc.width, align) * ALIGN(enc.height, 16) * 1.5;
-	cpb_size = vbuf_size * 10;
-
-
-	num_resources  = 0;
-	alloc_resource(&enc.fb, 4096, AMDGPU_GEM_DOMAIN_VRAM);
-	resources[num_resources++] = enc.fb.handle;
-	alloc_resource(&enc.bs, bs_size, AMDGPU_GEM_DOMAIN_VRAM);
-	resources[num_resources++] = enc.bs.handle;
-	alloc_resource(&enc.vbuf, vbuf_size, AMDGPU_GEM_DOMAIN_VRAM);
-	resources[num_resources++] = enc.vbuf.handle;
-	alloc_resource(&enc.cpb, cpb_size, AMDGPU_GEM_DOMAIN_VRAM);
-	resources[num_resources++] = enc.cpb.handle;
-	resources[num_resources++] = ib_handle;
-
-	r = amdgpu_bo_cpu_map(enc.vbuf.handle, (void **)&enc.vbuf.ptr);
-	CU_ASSERT_EQUAL(r, 0);
-
-	memset(enc.vbuf.ptr, 0, vbuf_size);
-	for (i = 0; i < enc.height; ++i) {
-		memcpy(enc.vbuf.ptr, (frame + i * enc.width), enc.width);
-		enc.vbuf.ptr += ALIGN(enc.width, align);
-	}
-	for (i = 0; i < enc.height / 2; ++i) {
-		memcpy(enc.vbuf.ptr, ((frame + enc.height * enc.width) + i * enc.width), enc.width);
-		enc.vbuf.ptr += ALIGN(enc.width, align);
-	}
-
-	r = amdgpu_bo_cpu_unmap(enc.vbuf.handle);
-	CU_ASSERT_EQUAL(r, 0);
-
-	len = 0;
-	memcpy((ib_cpu + len), uve_session_info, sizeof(uve_session_info));
-	len += sizeof(uve_session_info) / 4;
-	ib_cpu[len++] = enc.session.addr >> 32;
-	ib_cpu[len++] = enc.session.addr;
-
-	memcpy((ib_cpu + len), uve_task_info, sizeof(uve_task_info));
-	len += sizeof(uve_task_info) / 4;
-	ib_cpu[len++] = 0x000005e0;
-	ib_cpu[len++] = 0x00000001;
-	ib_cpu[len++] = 0x00000001;
-
-	memcpy((ib_cpu + len), uve_nalu_buffer_1, sizeof(uve_nalu_buffer_1));
-	len += sizeof(uve_nalu_buffer_1) / 4;
-
-	memcpy((ib_cpu + len), uve_nalu_buffer_2, sizeof(uve_nalu_buffer_2));
-	len += sizeof(uve_nalu_buffer_2) / 4;
-
-	memcpy((ib_cpu + len), uve_nalu_buffer_3, sizeof(uve_nalu_buffer_3));
-	len += sizeof(uve_nalu_buffer_3) / 4;
-
-	memcpy((ib_cpu + len), uve_nalu_buffer_4, sizeof(uve_nalu_buffer_4));
-	len += sizeof(uve_nalu_buffer_4) / 4;
-
-	memcpy((ib_cpu + len), uve_slice_header, sizeof(uve_slice_header));
-	len += sizeof(uve_slice_header) / 4;
-
-	ib_cpu[len++] = 0x00000254;
-	ib_cpu[len++] = 0x00000010;
-	ib_cpu[len++] = enc.cpb.addr >> 32;
-	ib_cpu[len++] = enc.cpb.addr;
-	memcpy((ib_cpu + len), uve_ctx_buffer, sizeof(uve_ctx_buffer));
-	len += sizeof(uve_ctx_buffer) / 4;
-
-	memcpy((ib_cpu + len), uve_bitstream_buffer, sizeof(uve_bitstream_buffer));
-	len += sizeof(uve_bitstream_buffer) / 4;
-	ib_cpu[len++] = 0x00000000;
-	ib_cpu[len++] = enc.bs.addr >> 32;
-	ib_cpu[len++] = enc.bs.addr;
-	ib_cpu[len++] = 0x003f4800;
-	ib_cpu[len++] = 0x00000000;
-
-	memcpy((ib_cpu + len), uve_feedback_buffer, sizeof(uve_feedback_buffer));
-	len += sizeof(uve_feedback_buffer) / 4;
-	ib_cpu[len++] = enc.fb.addr >> 32;
-	ib_cpu[len++] = enc.fb.addr;
-	ib_cpu[len++] = 0x00000010;
-	ib_cpu[len++] = 0x00000028;
-
-	memcpy((ib_cpu + len), uve_feedback_buffer_additional, sizeof(uve_feedback_buffer_additional));
-	len += sizeof(uve_feedback_buffer_additional) / 4;
-
-	memcpy((ib_cpu + len), uve_intra_refresh, sizeof(uve_intra_refresh));
-	len += sizeof(uve_intra_refresh) / 4;
-
-	memcpy((ib_cpu + len), uve_layer_select, sizeof(uve_layer_select));
-	len += sizeof(uve_layer_select) / 4;
-
-	memcpy((ib_cpu + len), uve_rc_layer_init, sizeof(uve_rc_layer_init));
-	len += sizeof(uve_rc_layer_init) / 4;
-
-	memcpy((ib_cpu + len), uve_layer_select, sizeof(uve_layer_select));
-	len += sizeof(uve_layer_select) / 4;
-
-	memcpy((ib_cpu + len), uve_rc_per_pic, sizeof(uve_rc_per_pic));
-	len += sizeof(uve_rc_per_pic) / 4;
-
-	unsigned luma_size = ALIGN(enc.width, align) * ALIGN(enc.height, 16);
-	luma_offset = enc.vbuf.addr;
-	chroma_offset = luma_offset + luma_size;
-	ib_cpu[len++] = 0x00000054;
-	ib_cpu[len++] = 0x0000000c;
-	ib_cpu[len++] = 0x00000002;
-	ib_cpu[len++] = 0x003f4800;
-	ib_cpu[len++] = luma_offset >> 32;
-	ib_cpu[len++] = luma_offset;
-	ib_cpu[len++] = chroma_offset >> 32;
-	ib_cpu[len++] = chroma_offset;
-	memcpy((ib_cpu + len), uve_encode_param, sizeof(uve_encode_param));
-	ib_cpu[len] = ALIGN(enc.width, align);
-	ib_cpu[len + 1] = ALIGN(enc.width, align);
-	len += sizeof(uve_encode_param) / 4;
-
-	memcpy((ib_cpu + len), uve_op_speed_enc_mode, sizeof(uve_op_speed_enc_mode));
-	len += sizeof(uve_op_speed_enc_mode) / 4;
-
-	memcpy((ib_cpu + len), uve_op_encode, sizeof(uve_op_encode));
-	len += sizeof(uve_op_encode) / 4;
-
-	r = submit(len, AMDGPU_HW_IP_UVD_ENC);
-	CU_ASSERT_EQUAL(r, 0);
-
-	check_result(&enc);
-
-	free_resource(&enc.fb);
-	free_resource(&enc.bs);
-	free_resource(&enc.vbuf);
-	free_resource(&enc.cpb);
-}
-
-static void amdgpu_cs_uvd_enc_destroy(void)
-{
-	int len, r;
-
-	num_resources  = 0;
-	resources[num_resources++] = ib_handle;
-
-	len = 0;
-	memcpy((ib_cpu + len), uve_session_info, sizeof(uve_session_info));
-	len += sizeof(uve_session_info) / 4;
-	ib_cpu[len++] = enc.session.addr >> 32;
-	ib_cpu[len++] = enc.session.addr;
-
-	memcpy((ib_cpu + len), uve_task_info, sizeof(uve_task_info));
-	len += sizeof(uve_task_info) / 4;
-	ib_cpu[len++] = 0xffffffff;
-	ib_cpu[len++] = 0x00000002;
-	ib_cpu[len++] = 0x00000000;
-
-	memcpy((ib_cpu + len), uve_op_close, sizeof(uve_op_close));
-	len += sizeof(uve_op_close) / 4;
-
-	r = submit(len, AMDGPU_HW_IP_UVD_ENC);
-	CU_ASSERT_EQUAL(r, 0);
-
-	free_resource(&enc.session);
-}

tests/amdgpu/uve_ib.h

@@ -1,527 +0,0 @@
-/*
- * Copyright 2017 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
-*/
-
-#ifndef _uve_ib_h_
-#define _uve_ib_h_
-
-static const uint32_t uve_session_info[] = {
-	0x00000018,
-	0x00000001,
-	0x00000000,
-	0x00010000,
-};
-
-static const uint32_t uve_task_info[] = {
-	0x00000014,
-	0x00000002,
-};
-
-static const uint32_t uve_session_init[] = {
-	0x00000020,
-	0x00000003,
-	0x000000c0,
-	0x00000080,
-	0x00000020,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-};
-
-static const uint32_t uve_layer_ctrl[] = {
-	0x00000010,
-	0x00000004,
-	0x00000001,
-	0x00000001,
-};
-
-static const uint32_t uve_layer_select[] = {
-	0x0000000c,
-	0x00000005,
-	0x00000000,
-};
-
-static const uint32_t uve_slice_ctrl[] = {
-	0x00000014,
-	0x00000006,
-	0x00000000,
-	0x00000006,
-	0x00000006,
-};
-
-static const uint32_t uve_spec_misc[] = {
-	0x00000024,
-	0x00000007,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000001,
-	0x00000001,
-};
-
-static const uint32_t uve_rc_session_init[] = {
-	0x00000010,
-	0x00000008,
-	0x00000000,
-	0x00000040,
-};
-
-static const uint32_t uve_rc_layer_init[] = {
-	0x00000028,
-	0x00000009,
-	0x001e8480,
-	0x001e8480,
-	0x0000001e,
-	0x00000001,
-	0x0001046a,
-	0x0001046a,
-	0x0001046a,
-	0xaaaaaaaa,
-};
-
-static const uint32_t uve_deblocking_filter[] = {
-	0x00000020,
-	0x0000000e,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-};
-
-static const uint32_t uve_quality_params[] = {
-	0x00000014,
-	0x0000000d,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-};
-
-static const uint32_t uve_feedback_buffer[] = {
-	0x0000001c,
-	0x00000012,
-	0x00000000,
-};
-
-static const uint32_t uve_feedback_buffer_additional[] = {
-	0x00000108,
-	0x00000014,
-	0x00000001,
-	0x00000010,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-};
-
-static const uint32_t uve_nalu_buffer_1[] = {
-	0x00000018,
-	0x00000013,
-	0x00000001,
-	0x00000007,
-	0x00000001,
-	0x46011000,
-};
-
-static const uint32_t uve_nalu_buffer_2[] = {
-	0x0000002c,
-	0x00000013,
-	0x00000002,
-	0x0000001b,
-	0x00000001,
-	0x40010c01,
-	0xffff0160,
-	0x00000300,
-	0xb0000003,
-	0x00000300,
-	0x962c0900,
-};
-
-static const uint32_t uve_nalu_buffer_3[] = {
-	0x00000034,
-	0x00000013,
-	0x00000003,
-	0x00000023,
-	0x00000001,
-	0x42010101,
-	0x60000003,
-	0x00b00000,
-	0x03000003,
-	0x0096a018,
-	0x2020708f,
-	0xcb924295,
-	0x12e08000,
-};
-
-static const uint32_t uve_nalu_buffer_4[] = {
-	0x0000001c,
-	0x00000013,
-	0x00000004,
-	0x0000000b,
-	0x00000001,
-	0x4401e0f1,
-	0x80992000,
-};
-
-static const uint32_t uve_slice_header[] = {
-	0x000000c8,
-	0x0000000b,
-	0x28010000,
-	0x40000000,
-	0x60000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000002,
-	0x00000010,
-	0x00000003,
-	0x00000000,
-	0x00000002,
-	0x00000002,
-	0x00000004,
-	0x00000000,
-	0x00000001,
-	0x00000000,
-	0x00000002,
-	0x00000003,
-	0x00000005,
-	0x00000000,
-	0x00000002,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-};
-
-static const uint32_t uve_encode_param[] = {
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0xffffffff,
-	0x00000001,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-};
-
-static const uint32_t uve_intra_refresh[] = {
-	0x00000014,
-	0x0000000f,
-	0x00000000,
-	0x00000000,
-	0x00000001,
-};
-
-static const uint32_t uve_ctx_buffer[] = {
-	0x00000000,
-	0x00000000,
-	0x000000a0,
-	0x000000a0,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-};
-
-static const uint32_t uve_bitstream_buffer[] = {
-	0x0000001c,
-	0x00000011,
-};
-
-static const uint32_t uve_rc_per_pic[] = {
-	0x00000024,
-	0x0000000a,
-	0x0000001a,
-	0x00000000,
-	0x00000033,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000001,
-};
-
-static const uint32_t uve_op_init[] = {
-	0x00000008,
-	0x08000001,
-};
-
-static const uint32_t uve_op_close[] = {
-	0x00000008,
-	0x08000002,
-};
-
-static const uint32_t uve_op_encode[] = {
-	0x00000008,
-	0x08000003,
-};
-
-static const uint32_t uve_op_init_rc[] = {
-	0x00000008,
-	0x08000004,
-};
-
-static const uint32_t uve_op_init_rc_vbv_level[] = {
-	0x00000008,
-	0x08000005,
-};
-
-static const uint32_t uve_op_speed_enc_mode[] = {
-	0x00000008,
-	0x08000006,
-};
-
-static const uint32_t uve_op_balance_enc_mode[] = {
-	0x00000008,
-	0x08000007,
-};
-
-static const uint32_t uve_op_quality_enc_mode[] = {
-	0x00000008,
-	0x08000008,
-};
-#endif /*_uve_ib_h*/

tests/amdgpu/vce_ib.h

@@ -1,335 +0,0 @@
-/*
- * Copyright 2015 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
-*/
-
-#ifndef _vce_ib_h_
-#define _vce_ib_h_
-
-static const uint32_t vce_session[] = {
-	0x0000000c,
-	0x00000001,
-	0x400c0001,
-};
-
-static uint32_t vce_taskinfo[8] = {
-	0x00000020,
-	0x00000002,
-	0xffffffff,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-};
-
-static const uint32_t vce_create[] = {
-	0x00000030,
-	0x01000001,
-	0x00000000,
-	0x00000042,
-	0x0000002a,
-	0x00000000,
-	0x000000a0,
-	0x00000080,
-	0x000000a0,
-	0x000000a0,
-	0x00000010,
-	0x00000201,
-};
-
-static const uint32_t vce_rate_ctrl[] = {
-	0x00000070,
-	0x04000005,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x0000001c,
-	0x0000001c,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000033,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-};
-
-static const uint32_t vce_config_ext[] = {
-	0x0000000c,
-	0x04000001,
-	0x00000003,
-};
-
-static const uint32_t vce_motion_est[] = {
-	0x00000068,
-	0x04000007,
-	0x00000001,
-	0x00000001,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000010,
-	0x00000010,
-	0x00000010,
-	0x00000010,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x000000fe,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000001,
-	0x00000001,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-};
-
-static const uint32_t vce_rdo[] = {
-	0x0000004c,
-	0x04000008,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-};
-
-static const uint32_t vce_pic_ctrl[] = {
-	0x00000074,
-	0x04000002,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000aa0,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000040,
-	0x00000000,
-	0x00000000,
-	0x00000001,
-	0x00000002,
-	0x00000001,
-	0x00000001,
-	0x00000000,
-	0x00000000,
-};
-
-static const uint32_t vce_feedback[] = {
-	0x00000014,
-	0x05000005,
-	0x00000000,
-	0xffffffff,
-	0x00000001,
-};
-
-static const uint32_t vce_context_buffer[] = {
-	0x00000010,
-	0x05000001,
-	0x00000000,
-	0xffffffff,
-};
-
-static const uint32_t vce_bs_buffer[] = {
-	0x00000014,
-	0x05000004,
-	0x00000000,
-	0xffffffff,
-	0x00154000,
-};
-
-static const uint32_t vce_aux_buffer[] = {
-	0x00000048,
-	0x05000002,
-	0x0000f000,
-	0x00016800,
-	0x0001e000,
-	0x00025800,
-	0x0002d000,
-	0x00034800,
-	0x0003c000,
-	0x00043800,
-	0x00007800,
-	0x00007800,
-	0x00007800,
-	0x00007800,
-	0x00007800,
-	0x00007800,
-	0x00007800,
-	0x00007800,
-};
-
-static uint32_t vce_encode[88] = {
-	0x00000160,
-	0x03000001,
-	0x00000011,
-	0x00000000,
-	0x00154000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0xffffffff,
-	0x00000000,
-	0xffffffff,
-	0x00000080,
-	0x000000a0,
-	0x000000a0,
-	0x00010000,
-	0x00000000,
-	0x00000003,
-	0x00000001,
-	0x00000000,
-	0x00000000,
-	0x00000001,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0xffffffff,
-	0xffffffff,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0xffffffff,
-	0xffffffff,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0xffffffff,
-	0xffffffff,
-	0xffffffff,
-	0xffffffff,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-};
-
-static const uint32_t vce_destroy[] = {
-	0x00000008,
-	0x02000001,
-};
-
-static const uint32_t vce_mv_buffer[] = {
-	0x00000038,
-	0x0500000d,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-};
-#endif /*_vce_ib_h*/

tests/amdgpu/vce_tests.c

@@ -1,764 +0,0 @@
-/*
- * Copyright 2015 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
-*/
-
-#include <stdio.h>
-#include <inttypes.h>
-
-#include "CUnit/Basic.h"
-
-#include "util_math.h"
-
-#include "amdgpu_test.h"
-#include "amdgpu_drm.h"
-#include "amdgpu_internal.h"
-
-#include "vce_ib.h"
-#include "frame.h"
-
-#define IB_SIZE		4096
-#define MAX_RESOURCES	16
-#define FW_53_0_03 ((53 << 24) | (0 << 16) | (03 << 8))
-
-struct amdgpu_vce_bo {
-	amdgpu_bo_handle handle;
-	amdgpu_va_handle va_handle;
-	uint64_t addr;
-	uint64_t size;
-	uint8_t *ptr;
-};
-
-struct amdgpu_vce_encode {
-	unsigned width;
-	unsigned height;
-	struct amdgpu_vce_bo vbuf;
-	struct amdgpu_vce_bo bs[2];
-	struct amdgpu_vce_bo fb[2];
-	struct amdgpu_vce_bo cpb;
-	unsigned ib_len;
-	bool two_instance;
-	struct amdgpu_vce_bo mvrefbuf;
-	struct amdgpu_vce_bo mvb;
-	unsigned mvbuf_size;
-};
-
-static amdgpu_device_handle device_handle;
-static uint32_t major_version;
-static uint32_t minor_version;
-static uint32_t family_id;
-static uint32_t vce_harvest_config;
-static uint32_t chip_rev;
-static uint32_t chip_id;
-static uint32_t ids_flags;
-static bool is_mv_supported = true;
-
-static amdgpu_context_handle context_handle;
-static amdgpu_bo_handle ib_handle;
-static amdgpu_va_handle ib_va_handle;
-static uint64_t ib_mc_address;
-static uint32_t *ib_cpu;
-
-static struct amdgpu_vce_encode enc;
-static amdgpu_bo_handle resources[MAX_RESOURCES];
-static unsigned num_resources;
-
-static void amdgpu_cs_vce_create(void);
-static void amdgpu_cs_vce_encode(void);
-static void amdgpu_cs_vce_encode_mv(void);
-static void amdgpu_cs_vce_destroy(void);
-
-CU_TestInfo vce_tests[] = {
-	{ "VCE create",  amdgpu_cs_vce_create },
-	{ "VCE encode",  amdgpu_cs_vce_encode },
-	{ "VCE MV dump",  amdgpu_cs_vce_encode_mv },
-	{ "VCE destroy",  amdgpu_cs_vce_destroy },
-	CU_TEST_INFO_NULL,
-};
-
-CU_BOOL suite_vce_tests_enable(void)
-{
-	uint32_t version, feature;
-	CU_BOOL ret_mv = CU_FALSE;
-
-	if (amdgpu_device_initialize(drm_amdgpu[0], &major_version,
-					     &minor_version, &device_handle))
-		return CU_FALSE;
-
-	family_id = device_handle->info.family_id;
-	chip_rev = device_handle->info.chip_rev;
-	chip_id = device_handle->info.chip_external_rev;
-	ids_flags = device_handle->info.ids_flags;
-
-	amdgpu_query_firmware_version(device_handle, AMDGPU_INFO_FW_VCE, 0,
-					  0, &version, &feature);
-
-	if (amdgpu_device_deinitialize(device_handle))
-		return CU_FALSE;
-
-	if (family_id >= AMDGPU_FAMILY_RV || family_id == AMDGPU_FAMILY_SI ||
-		asic_is_gfx_pipe_removed(family_id, chip_id, chip_rev)) {
-		printf("\n\nThe ASIC NOT support VCE, suite disabled\n");
-		return CU_FALSE;
-	}
-
-	if (!(chip_id == (chip_rev + 0x3C) || /* FIJI */
-			chip_id == (chip_rev + 0x50) || /* Polaris 10*/
-			chip_id == (chip_rev + 0x5A) || /* Polaris 11*/
-			chip_id == (chip_rev + 0x64) || /* Polaris 12*/
-			(family_id >= AMDGPU_FAMILY_AI && !ids_flags))) /* dGPU > Polaris */
-		printf("\n\nThe ASIC NOT support VCE MV, suite disabled\n");
-	else if (FW_53_0_03 > version)
-		printf("\n\nThe ASIC FW version NOT support VCE MV, suite disabled\n");
-	else
-		ret_mv = CU_TRUE;
-
-	if (ret_mv == CU_FALSE) {
-		amdgpu_set_test_active("VCE Tests", "VCE MV dump", ret_mv);
-		is_mv_supported = false;
-	}
-
-	return CU_TRUE;
-}
-
-int suite_vce_tests_init(void)
-{
-	int r;
-
-	r = amdgpu_device_initialize(drm_amdgpu[0], &major_version,
-				     &minor_version, &device_handle);
-	if (r) {
-		if ((r == -EACCES) && (errno == EACCES))
-			printf("\n\nError:%s. "
-				"Hint:Try to run this test program as root.",
-				strerror(errno));
-
-		return CUE_SINIT_FAILED;
-	}
-
-	family_id = device_handle->info.family_id;
-	vce_harvest_config = device_handle->info.vce_harvest_config;
-
-	r = amdgpu_cs_ctx_create(device_handle, &context_handle);
-	if (r)
-		return CUE_SINIT_FAILED;
-
-	r = amdgpu_bo_alloc_and_map(device_handle, IB_SIZE, 4096,
-				    AMDGPU_GEM_DOMAIN_GTT, 0,
-				    &ib_handle, (void**)&ib_cpu,
-				    &ib_mc_address, &ib_va_handle);
-	if (r)
-		return CUE_SINIT_FAILED;
-
-	memset(&enc, 0, sizeof(struct amdgpu_vce_encode));
-
-	return CUE_SUCCESS;
-}
-
-int suite_vce_tests_clean(void)
-{
-	int r;
-
-	r = amdgpu_bo_unmap_and_free(ib_handle, ib_va_handle,
-				     ib_mc_address, IB_SIZE);
-	if (r)
-		return CUE_SCLEAN_FAILED;
-
-	r = amdgpu_cs_ctx_free(context_handle);
-	if (r)
-		return CUE_SCLEAN_FAILED;
-
-	r = amdgpu_device_deinitialize(device_handle);
-	if (r)
-		return CUE_SCLEAN_FAILED;
-
-	return CUE_SUCCESS;
-}
-
-static int submit(unsigned ndw, unsigned ip)
-{
-	struct amdgpu_cs_request ibs_request = {0};
-	struct amdgpu_cs_ib_info ib_info = {0};
-	struct amdgpu_cs_fence fence_status = {0};
-	uint32_t expired;
-	int r;
-
-	ib_info.ib_mc_address = ib_mc_address;
-	ib_info.size = ndw;
-
-	ibs_request.ip_type = ip;
-
-	r = amdgpu_bo_list_create(device_handle, num_resources, resources,
-				  NULL, &ibs_request.resources);
-	if (r)
-		return r;
-
-	ibs_request.number_of_ibs = 1;
-	ibs_request.ibs = &ib_info;
-	ibs_request.fence_info.handle = NULL;
-
-	r = amdgpu_cs_submit(context_handle, 0, &ibs_request, 1);
-	if (r)
-		return r;
-
-	r = amdgpu_bo_list_destroy(ibs_request.resources);
-	if (r)
-		return r;
-
-	fence_status.context = context_handle;
-	fence_status.ip_type = ip;
-	fence_status.fence = ibs_request.seq_no;
-
-	r = amdgpu_cs_query_fence_status(&fence_status,
-					 AMDGPU_TIMEOUT_INFINITE,
-					 0, &expired);
-	if (r)
-		return r;
-
-	return 0;
-}
-
-static void alloc_resource(struct amdgpu_vce_bo *vce_bo, unsigned size, unsigned domain)
-{
-	struct amdgpu_bo_alloc_request req = {0};
-	amdgpu_bo_handle buf_handle;
-	amdgpu_va_handle va_handle;
-	uint64_t va = 0;
-	int r;
-
-	req.alloc_size = ALIGN(size, 4096);
-	req.preferred_heap = domain;
-	r = amdgpu_bo_alloc(device_handle, &req, &buf_handle);
-	CU_ASSERT_EQUAL(r, 0);
-	r = amdgpu_va_range_alloc(device_handle,
-				  amdgpu_gpu_va_range_general,
-				  req.alloc_size, 1, 0, &va,
-				  &va_handle, 0);
-	CU_ASSERT_EQUAL(r, 0);
-	r = amdgpu_bo_va_op(buf_handle, 0, req.alloc_size, va, 0,
-			    AMDGPU_VA_OP_MAP);
-	CU_ASSERT_EQUAL(r, 0);
-	vce_bo->addr = va;
-	vce_bo->handle = buf_handle;
-	vce_bo->size = req.alloc_size;
-	vce_bo->va_handle = va_handle;
-	r = amdgpu_bo_cpu_map(vce_bo->handle, (void **)&vce_bo->ptr);
-	CU_ASSERT_EQUAL(r, 0);
-	memset(vce_bo->ptr, 0, size);
-	r = amdgpu_bo_cpu_unmap(vce_bo->handle);
-	CU_ASSERT_EQUAL(r, 0);
-}
-
-static void free_resource(struct amdgpu_vce_bo *vce_bo)
-{
-	int r;
-
-	r = amdgpu_bo_va_op(vce_bo->handle, 0, vce_bo->size,
-			    vce_bo->addr, 0, AMDGPU_VA_OP_UNMAP);
-	CU_ASSERT_EQUAL(r, 0);
-
-	r = amdgpu_va_range_free(vce_bo->va_handle);
-	CU_ASSERT_EQUAL(r, 0);
-
-	r = amdgpu_bo_free(vce_bo->handle);
-	CU_ASSERT_EQUAL(r, 0);
-	memset(vce_bo, 0, sizeof(*vce_bo));
-}
-
-static void amdgpu_cs_vce_create(void)
-{
-	unsigned align = (family_id >= AMDGPU_FAMILY_AI) ? 256 : 16;
-	int len, r;
-
-	enc.width = vce_create[6];
-	enc.height = vce_create[7];
-
-	num_resources  = 0;
-	alloc_resource(&enc.fb[0], 4096, AMDGPU_GEM_DOMAIN_GTT);
-	resources[num_resources++] = enc.fb[0].handle;
-	resources[num_resources++] = ib_handle;
-
-	len = 0;
-	memcpy(ib_cpu, vce_session, sizeof(vce_session));
-	len += sizeof(vce_session) / 4;
-	memcpy((ib_cpu + len), vce_taskinfo, sizeof(vce_taskinfo));
-	len += sizeof(vce_taskinfo) / 4;
-	memcpy((ib_cpu + len), vce_create, sizeof(vce_create));
-	ib_cpu[len + 8] = ALIGN(enc.width, align);
-	ib_cpu[len + 9] = ALIGN(enc.width, align);
-	if (is_mv_supported == true) {/* disableTwoInstance */
-		if (family_id >= AMDGPU_FAMILY_AI)
-			ib_cpu[len + 11] = 0x01000001;
-		else
-			ib_cpu[len + 11] = 0x01000201;
-	}
-	len += sizeof(vce_create) / 4;
-	memcpy((ib_cpu + len), vce_feedback, sizeof(vce_feedback));
-	ib_cpu[len + 2] = enc.fb[0].addr >> 32;
-	ib_cpu[len + 3] = enc.fb[0].addr;
-	len += sizeof(vce_feedback) / 4;
-
-	r = submit(len, AMDGPU_HW_IP_VCE);
-	CU_ASSERT_EQUAL(r, 0);
-
-	free_resource(&enc.fb[0]);
-}
-
-static void amdgpu_cs_vce_config(void)
-{
-	int len = 0, r;
-
-	memcpy((ib_cpu + len), vce_session, sizeof(vce_session));
-	len += sizeof(vce_session) / 4;
-	memcpy((ib_cpu + len), vce_taskinfo, sizeof(vce_taskinfo));
-	ib_cpu[len + 3] = 2;
-	ib_cpu[len + 6] = 0xffffffff;
-	len += sizeof(vce_taskinfo) / 4;
-	memcpy((ib_cpu + len), vce_rate_ctrl, sizeof(vce_rate_ctrl));
-	len += sizeof(vce_rate_ctrl) / 4;
-	memcpy((ib_cpu + len), vce_config_ext, sizeof(vce_config_ext));
-	len += sizeof(vce_config_ext) / 4;
-	memcpy((ib_cpu + len), vce_motion_est, sizeof(vce_motion_est));
-	len += sizeof(vce_motion_est) / 4;
-	memcpy((ib_cpu + len), vce_rdo, sizeof(vce_rdo));
-	len += sizeof(vce_rdo) / 4;
-	memcpy((ib_cpu + len), vce_pic_ctrl, sizeof(vce_pic_ctrl));
-	if (is_mv_supported == true)
-		ib_cpu[len + 27] = 0x00000001; /* encSliceMode */
-	len += sizeof(vce_pic_ctrl) / 4;
-
-	r = submit(len, AMDGPU_HW_IP_VCE);
-	CU_ASSERT_EQUAL(r, 0);
-}
-
-static void amdgpu_cs_vce_encode_idr(struct amdgpu_vce_encode *enc)
-{
-
-	uint64_t luma_offset, chroma_offset;
-	unsigned align = (family_id >= AMDGPU_FAMILY_AI) ? 256 : 16;
-	unsigned luma_size = ALIGN(enc->width, align) * ALIGN(enc->height, 16);
-	int len = 0, i, r;
-
-	luma_offset = enc->vbuf.addr;
-	chroma_offset = luma_offset + luma_size;
-
-	memcpy((ib_cpu + len), vce_session, sizeof(vce_session));
-	len += sizeof(vce_session) / 4;
-	memcpy((ib_cpu + len), vce_taskinfo, sizeof(vce_taskinfo));
-	len += sizeof(vce_taskinfo) / 4;
-	memcpy((ib_cpu + len), vce_bs_buffer, sizeof(vce_bs_buffer));
-	ib_cpu[len + 2] = enc->bs[0].addr >> 32;
-	ib_cpu[len + 3] = enc->bs[0].addr;
-	len += sizeof(vce_bs_buffer) / 4;
-	memcpy((ib_cpu + len), vce_context_buffer, sizeof(vce_context_buffer));
-	ib_cpu[len + 2] = enc->cpb.addr >> 32;
-	ib_cpu[len + 3] = enc->cpb.addr;
-	len += sizeof(vce_context_buffer) / 4;
-	memcpy((ib_cpu + len), vce_aux_buffer, sizeof(vce_aux_buffer));
-	for (i = 0; i <  8; ++i)
-		ib_cpu[len + 2 + i] = luma_size * 1.5 * (i + 2);
-	for (i = 0; i <  8; ++i)
-		ib_cpu[len + 10 + i] = luma_size * 1.5;
-	len += sizeof(vce_aux_buffer) / 4;
-	memcpy((ib_cpu + len), vce_feedback, sizeof(vce_feedback));
-	ib_cpu[len + 2] = enc->fb[0].addr >> 32;
-	ib_cpu[len + 3] = enc->fb[0].addr;
-	len += sizeof(vce_feedback) / 4;
-	memcpy((ib_cpu + len), vce_encode, sizeof(vce_encode));
-	ib_cpu[len + 9] = luma_offset >> 32;
-	ib_cpu[len + 10] = luma_offset;
-	ib_cpu[len + 11] = chroma_offset >> 32;
-	ib_cpu[len + 12] = chroma_offset;
-	ib_cpu[len + 14] = ALIGN(enc->width, align);
-	ib_cpu[len + 15] = ALIGN(enc->width, align);
-	ib_cpu[len + 73] = luma_size * 1.5;
-	ib_cpu[len + 74] = luma_size * 2.5;
-	len += sizeof(vce_encode) / 4;
-	enc->ib_len = len;
-	if (!enc->two_instance) {
-		r = submit(len, AMDGPU_HW_IP_VCE);
-		CU_ASSERT_EQUAL(r, 0);
-	}
-}
-
-static void amdgpu_cs_vce_encode_p(struct amdgpu_vce_encode *enc)
-{
-	uint64_t luma_offset, chroma_offset;
-	int len, i, r;
-	unsigned align = (family_id >= AMDGPU_FAMILY_AI) ? 256 : 16;
-	unsigned luma_size = ALIGN(enc->width, align) * ALIGN(enc->height, 16);
-
-	len = (enc->two_instance) ? enc->ib_len : 0;
-	luma_offset = enc->vbuf.addr;
-	chroma_offset = luma_offset + luma_size;
-
-	if (!enc->two_instance) {
-		memcpy((ib_cpu + len), vce_session, sizeof(vce_session));
-		len += sizeof(vce_session) / 4;
-	}
-	memcpy((ib_cpu + len), vce_taskinfo, sizeof(vce_taskinfo));
-	len += sizeof(vce_taskinfo) / 4;
-	memcpy((ib_cpu + len), vce_bs_buffer, sizeof(vce_bs_buffer));
-	ib_cpu[len + 2] = enc->bs[1].addr >> 32;
-	ib_cpu[len + 3] = enc->bs[1].addr;
-	len += sizeof(vce_bs_buffer) / 4;
-	memcpy((ib_cpu + len), vce_context_buffer, sizeof(vce_context_buffer));
-	ib_cpu[len + 2] = enc->cpb.addr >> 32;
-	ib_cpu[len + 3] = enc->cpb.addr;
-	len += sizeof(vce_context_buffer) / 4;
-	memcpy((ib_cpu + len), vce_aux_buffer, sizeof(vce_aux_buffer));
-	for (i = 0; i <  8; ++i)
-		ib_cpu[len + 2 + i] = luma_size * 1.5 * (i + 2);
-	for (i = 0; i <  8; ++i)
-		ib_cpu[len + 10 + i] = luma_size * 1.5;
-	len += sizeof(vce_aux_buffer) / 4;
-	memcpy((ib_cpu + len), vce_feedback, sizeof(vce_feedback));
-	ib_cpu[len + 2] = enc->fb[1].addr >> 32;
-	ib_cpu[len + 3] = enc->fb[1].addr;
-	len += sizeof(vce_feedback) / 4;
-	memcpy((ib_cpu + len), vce_encode, sizeof(vce_encode));
-	ib_cpu[len + 2] = 0;
-	ib_cpu[len + 9] = luma_offset >> 32;
-	ib_cpu[len + 10] = luma_offset;
-	ib_cpu[len + 11] = chroma_offset >> 32;
-	ib_cpu[len + 12] = chroma_offset;
-	ib_cpu[len + 14] = ALIGN(enc->width, align);
-	ib_cpu[len + 15] = ALIGN(enc->width, align);
-	ib_cpu[len + 18] = 0;
-	ib_cpu[len + 19] = 0;
-	ib_cpu[len + 56] = 3;
-	ib_cpu[len + 57] = 0;
-	ib_cpu[len + 58] = 0;
-	ib_cpu[len + 59] = luma_size * 1.5;
-	ib_cpu[len + 60] = luma_size * 2.5;
-	ib_cpu[len + 73] = 0;
-	ib_cpu[len + 74] = luma_size;
-	ib_cpu[len + 81] = 1;
-	ib_cpu[len + 82] = 1;
-	len += sizeof(vce_encode) / 4;
-
-	r = submit(len, AMDGPU_HW_IP_VCE);
-	CU_ASSERT_EQUAL(r, 0);
-}
-
-static void check_result(struct amdgpu_vce_encode *enc)
-{
-	uint64_t sum;
-	uint32_t s[2] = {180325, 15946};
-	uint32_t *ptr, size;
-	int i, j, r;
-
-	for (i = 0; i < 2; ++i) {
-		r = amdgpu_bo_cpu_map(enc->fb[i].handle, (void **)&enc->fb[i].ptr);
-		CU_ASSERT_EQUAL(r, 0);
-		ptr = (uint32_t *)enc->fb[i].ptr;
-		size = ptr[4] - ptr[9];
-		r = amdgpu_bo_cpu_unmap(enc->fb[i].handle);
-		CU_ASSERT_EQUAL(r, 0);
-		r = amdgpu_bo_cpu_map(enc->bs[i].handle, (void **)&enc->bs[i].ptr);
-		CU_ASSERT_EQUAL(r, 0);
-		for (j = 0, sum = 0; j < size; ++j)
-			sum += enc->bs[i].ptr[j];
-		CU_ASSERT_EQUAL(sum, s[i]);
-		r = amdgpu_bo_cpu_unmap(enc->bs[i].handle);
-		CU_ASSERT_EQUAL(r, 0);
-	}
-}
-
-static void amdgpu_cs_vce_encode(void)
-{
-	uint32_t vbuf_size, bs_size = 0x154000, cpb_size;
-	unsigned align = (family_id >= AMDGPU_FAMILY_AI) ? 256 : 16;
-	int i, r;
-
-	vbuf_size = ALIGN(enc.width, align) * ALIGN(enc.height, 16) * 1.5;
-	cpb_size = vbuf_size * 10;
-	num_resources = 0;
-	alloc_resource(&enc.fb[0], 4096, AMDGPU_GEM_DOMAIN_GTT);
-	resources[num_resources++] = enc.fb[0].handle;
-	alloc_resource(&enc.fb[1], 4096, AMDGPU_GEM_DOMAIN_GTT);
-	resources[num_resources++] = enc.fb[1].handle;
-	alloc_resource(&enc.bs[0], bs_size, AMDGPU_GEM_DOMAIN_GTT);
-	resources[num_resources++] = enc.bs[0].handle;
-	alloc_resource(&enc.bs[1], bs_size, AMDGPU_GEM_DOMAIN_GTT);
-	resources[num_resources++] = enc.bs[1].handle;
-	alloc_resource(&enc.vbuf, vbuf_size, AMDGPU_GEM_DOMAIN_VRAM);
-	resources[num_resources++] = enc.vbuf.handle;
-	alloc_resource(&enc.cpb, cpb_size, AMDGPU_GEM_DOMAIN_VRAM);
-	resources[num_resources++] = enc.cpb.handle;
-	resources[num_resources++] = ib_handle;
-
-	r = amdgpu_bo_cpu_map(enc.vbuf.handle, (void **)&enc.vbuf.ptr);
-	CU_ASSERT_EQUAL(r, 0);
-
-	memset(enc.vbuf.ptr, 0, vbuf_size);
-	for (i = 0; i < enc.height; ++i) {
-		memcpy(enc.vbuf.ptr, (frame + i * enc.width), enc.width);
-		enc.vbuf.ptr += ALIGN(enc.width, align);
-	}
-	for (i = 0; i < enc.height / 2; ++i) {
-		memcpy(enc.vbuf.ptr, ((frame + enc.height * enc.width) + i * enc.width), enc.width);
-		enc.vbuf.ptr += ALIGN(enc.width, align);
-	}
-
-	r = amdgpu_bo_cpu_unmap(enc.vbuf.handle);
-	CU_ASSERT_EQUAL(r, 0);
-
-	amdgpu_cs_vce_config();
-
-	if (family_id >= AMDGPU_FAMILY_VI) {
-		vce_taskinfo[3] = 3;
-		amdgpu_cs_vce_encode_idr(&enc);
-		amdgpu_cs_vce_encode_p(&enc);
-		check_result(&enc);
-
-		/* two pipes */
-		vce_encode[16] = 0;
-		amdgpu_cs_vce_encode_idr(&enc);
-		amdgpu_cs_vce_encode_p(&enc);
-		check_result(&enc);
-
-		/* two instances */
-		if (vce_harvest_config == 0) {
-			enc.two_instance = true;
-			vce_taskinfo[2] = 0x83;
-			vce_taskinfo[4] = 1;
-			amdgpu_cs_vce_encode_idr(&enc);
-			vce_taskinfo[2] = 0xffffffff;
-			vce_taskinfo[4] = 2;
-			amdgpu_cs_vce_encode_p(&enc);
-			check_result(&enc);
-		}
-	} else {
-		vce_taskinfo[3] = 3;
-		vce_encode[16] = 0;
-		amdgpu_cs_vce_encode_idr(&enc);
-		amdgpu_cs_vce_encode_p(&enc);
-		check_result(&enc);
-	}
-
-	free_resource(&enc.fb[0]);
-	free_resource(&enc.fb[1]);
-	free_resource(&enc.bs[0]);
-	free_resource(&enc.bs[1]);
-	free_resource(&enc.vbuf);
-	free_resource(&enc.cpb);
-}
-
-static void amdgpu_cs_vce_mv(struct amdgpu_vce_encode *enc)
-{
-	uint64_t luma_offset, chroma_offset;
-	uint64_t mv_ref_luma_offset;
-	unsigned align = (family_id >= AMDGPU_FAMILY_AI) ? 256 : 16;
-	unsigned luma_size = ALIGN(enc->width, align) * ALIGN(enc->height, 16);
-	int len = 0, i, r;
-
-	luma_offset = enc->vbuf.addr;
-	chroma_offset = luma_offset + luma_size;
-	mv_ref_luma_offset = enc->mvrefbuf.addr;
-
-	memcpy((ib_cpu + len), vce_session, sizeof(vce_session));
-	len += sizeof(vce_session) / 4;
-	memcpy((ib_cpu + len), vce_taskinfo, sizeof(vce_taskinfo));
-	len += sizeof(vce_taskinfo) / 4;
-	memcpy((ib_cpu + len), vce_bs_buffer, sizeof(vce_bs_buffer));
-	ib_cpu[len + 2] = enc->bs[0].addr >> 32;
-	ib_cpu[len + 3] = enc->bs[0].addr;
-	len += sizeof(vce_bs_buffer) / 4;
-	memcpy((ib_cpu + len), vce_context_buffer, sizeof(vce_context_buffer));
-	ib_cpu[len + 2] = enc->cpb.addr >> 32;
-	ib_cpu[len + 3] = enc->cpb.addr;
-	len += sizeof(vce_context_buffer) / 4;
-	memcpy((ib_cpu + len), vce_aux_buffer, sizeof(vce_aux_buffer));
-	for (i = 0; i <  8; ++i)
-		ib_cpu[len + 2 + i] = luma_size * 1.5 * (i + 2);
-	for (i = 0; i <  8; ++i)
-		ib_cpu[len + 10 + i] = luma_size * 1.5;
-	len += sizeof(vce_aux_buffer) / 4;
-	memcpy((ib_cpu + len), vce_feedback, sizeof(vce_feedback));
-	ib_cpu[len + 2] = enc->fb[0].addr >> 32;
-	ib_cpu[len + 3] = enc->fb[0].addr;
-	len += sizeof(vce_feedback) / 4;
-	memcpy((ib_cpu + len), vce_mv_buffer, sizeof(vce_mv_buffer));
-	ib_cpu[len + 2] = mv_ref_luma_offset >> 32;
-	ib_cpu[len + 3] = mv_ref_luma_offset;
-	ib_cpu[len + 4] = ALIGN(enc->width, align);
-	ib_cpu[len + 5] = ALIGN(enc->width, align);
-	ib_cpu[len + 6] = luma_size;
-	ib_cpu[len + 7] = enc->mvb.addr >> 32;
-	ib_cpu[len + 8] = enc->mvb.addr;
-	len += sizeof(vce_mv_buffer) / 4;
-	memcpy((ib_cpu + len), vce_encode, sizeof(vce_encode));
-	ib_cpu[len + 2] = 0;
-	ib_cpu[len + 3] = 0;
-	ib_cpu[len + 4] = 0x154000;
-	ib_cpu[len + 9] = luma_offset >> 32;
-	ib_cpu[len + 10] = luma_offset;
-	ib_cpu[len + 11] = chroma_offset >> 32;
-	ib_cpu[len + 12] = chroma_offset;
-	ib_cpu[len + 13] = ALIGN(enc->height, 16);;
-	ib_cpu[len + 14] = ALIGN(enc->width, align);
-	ib_cpu[len + 15] = ALIGN(enc->width, align);
-	/* encDisableMBOffloading-encDisableTwoPipeMode-encInputPicArrayMode-encInputPicAddrMode */
-	ib_cpu[len + 16] = 0x01010000;
-	ib_cpu[len + 18] = 0; /* encPicType */
-	ib_cpu[len + 19] = 0; /* encIdrFlag */
-	ib_cpu[len + 20] = 0; /* encIdrPicId */
-	ib_cpu[len + 21] = 0; /* encMGSKeyPic */
-	ib_cpu[len + 22] = 0; /* encReferenceFlag */
-	ib_cpu[len + 23] = 0; /* encTemporalLayerIndex */
-	ib_cpu[len + 55] = 0; /* pictureStructure */
-	ib_cpu[len + 56] = 0; /* encPicType -ref[0] */
-	ib_cpu[len + 61] = 0; /* pictureStructure */
-	ib_cpu[len + 62] = 0; /* encPicType -ref[1] */
-	ib_cpu[len + 67] = 0; /* pictureStructure */
-	ib_cpu[len + 68] = 0; /* encPicType -ref1 */
-	ib_cpu[len + 81] = 1; /* frameNumber */
-	ib_cpu[len + 82] = 2; /* pictureOrderCount */
-	ib_cpu[len + 83] = 0xffffffff; /* numIPicRemainInRCGOP */
-	ib_cpu[len + 84] = 0xffffffff; /* numPPicRemainInRCGOP */
-	ib_cpu[len + 85] = 0xffffffff; /* numBPicRemainInRCGOP */
-	ib_cpu[len + 86] = 0xffffffff; /* numIRPicRemainInRCGOP */
-	ib_cpu[len + 87] = 0; /* remainedIntraRefreshPictures */
-	len += sizeof(vce_encode) / 4;
-
-	enc->ib_len = len;
-	r = submit(len, AMDGPU_HW_IP_VCE);
-	CU_ASSERT_EQUAL(r, 0);
-}
-
-static void check_mv_result(struct amdgpu_vce_encode *enc)
-{
-	uint64_t sum;
-	uint32_t s = 140790;
-	int j, r;
-
-	r = amdgpu_bo_cpu_map(enc->fb[0].handle, (void **)&enc->fb[0].ptr);
-	CU_ASSERT_EQUAL(r, 0);
-	r = amdgpu_bo_cpu_unmap(enc->fb[0].handle);
-	CU_ASSERT_EQUAL(r, 0);
-	r = amdgpu_bo_cpu_map(enc->mvb.handle, (void **)&enc->mvb.ptr);
-	CU_ASSERT_EQUAL(r, 0);
-	for (j = 0, sum = 0; j < enc->mvbuf_size; ++j)
-		sum += enc->mvb.ptr[j];
-	CU_ASSERT_EQUAL(sum, s);
-	r = amdgpu_bo_cpu_unmap(enc->mvb.handle);
-	CU_ASSERT_EQUAL(r, 0);
-}
-
-static void amdgpu_cs_vce_encode_mv(void)
-{
-	uint32_t vbuf_size, bs_size = 0x154000, cpb_size;
-	unsigned align = (family_id >= AMDGPU_FAMILY_AI) ? 256 : 16;
-	int i, r;
-
-	vbuf_size = ALIGN(enc.width, align) * ALIGN(enc.height, 16) * 1.5;
-	enc.mvbuf_size = ALIGN(enc.width, 16) * ALIGN(enc.height, 16) / 8;
-	cpb_size = vbuf_size * 10;
-	num_resources = 0;
-	alloc_resource(&enc.fb[0], 4096, AMDGPU_GEM_DOMAIN_GTT);
-	resources[num_resources++] = enc.fb[0].handle;
-	alloc_resource(&enc.bs[0], bs_size, AMDGPU_GEM_DOMAIN_GTT);
-	resources[num_resources++] = enc.bs[0].handle;
-	alloc_resource(&enc.mvb, enc.mvbuf_size, AMDGPU_GEM_DOMAIN_GTT);
-	resources[num_resources++] = enc.mvb.handle;
-	alloc_resource(&enc.vbuf, vbuf_size, AMDGPU_GEM_DOMAIN_VRAM);
-	resources[num_resources++] = enc.vbuf.handle;
-	alloc_resource(&enc.mvrefbuf, vbuf_size, AMDGPU_GEM_DOMAIN_VRAM);
-	resources[num_resources++] = enc.mvrefbuf.handle;
-	alloc_resource(&enc.cpb, cpb_size, AMDGPU_GEM_DOMAIN_VRAM);
-	resources[num_resources++] = enc.cpb.handle;
-	resources[num_resources++] = ib_handle;
-
-	r = amdgpu_bo_cpu_map(enc.vbuf.handle, (void **)&enc.vbuf.ptr);
-	CU_ASSERT_EQUAL(r, 0);
-
-	memset(enc.vbuf.ptr, 0, vbuf_size);
-	for (i = 0; i < enc.height; ++i) {
-		memcpy(enc.vbuf.ptr, (frame + i * enc.width), enc.width);
-		enc.vbuf.ptr += ALIGN(enc.width, align);
-	}
-	for (i = 0; i < enc.height / 2; ++i) {
-		memcpy(enc.vbuf.ptr, ((frame + enc.height * enc.width) + i * enc.width), enc.width);
-		enc.vbuf.ptr += ALIGN(enc.width, align);
-	}
-
-	r = amdgpu_bo_cpu_unmap(enc.vbuf.handle);
-	CU_ASSERT_EQUAL(r, 0);
-
-	r = amdgpu_bo_cpu_map(enc.mvrefbuf.handle, (void **)&enc.mvrefbuf.ptr);
-	CU_ASSERT_EQUAL(r, 0);
-
-	memset(enc.mvrefbuf.ptr, 0, vbuf_size);
-	for (i = 0; i < enc.height; ++i) {
-		memcpy(enc.mvrefbuf.ptr, (frame + (enc.height - i -1) * enc.width), enc.width);
-		enc.mvrefbuf.ptr += ALIGN(enc.width, align);
-	}
-	for (i = 0; i < enc.height / 2; ++i) {
-		memcpy(enc.mvrefbuf.ptr,
-		((frame + enc.height * enc.width) + (enc.height / 2 - i -1) * enc.width), enc.width);
-		enc.mvrefbuf.ptr += ALIGN(enc.width, align);
-	}
-
-	r = amdgpu_bo_cpu_unmap(enc.mvrefbuf.handle);
-	CU_ASSERT_EQUAL(r, 0);
-
-	amdgpu_cs_vce_config();
-
-	vce_taskinfo[3] = 3;
-	amdgpu_cs_vce_mv(&enc);
-	check_mv_result(&enc);
-
-	free_resource(&enc.fb[0]);
-	free_resource(&enc.bs[0]);
-	free_resource(&enc.vbuf);
-	free_resource(&enc.cpb);
-	free_resource(&enc.mvrefbuf);
-	free_resource(&enc.mvb);
-}
-
-static void amdgpu_cs_vce_destroy(void)
-{
-	int len, r;
-
-	num_resources  = 0;
-	alloc_resource(&enc.fb[0], 4096, AMDGPU_GEM_DOMAIN_GTT);
-	resources[num_resources++] = enc.fb[0].handle;
-	resources[num_resources++] = ib_handle;
-
-	len = 0;
-	memcpy(ib_cpu, vce_session, sizeof(vce_session));
-	len += sizeof(vce_session) / 4;
-	memcpy((ib_cpu + len), vce_taskinfo, sizeof(vce_taskinfo));
-	ib_cpu[len + 3] = 1;
-	len += sizeof(vce_taskinfo) / 4;
-	memcpy((ib_cpu + len), vce_feedback, sizeof(vce_feedback));
-	ib_cpu[len + 2] = enc.fb[0].addr >> 32;
-	ib_cpu[len + 3] = enc.fb[0].addr;
-	len += sizeof(vce_feedback) / 4;
-	memcpy((ib_cpu + len), vce_destroy, sizeof(vce_destroy));
-	len += sizeof(vce_destroy) / 4;
-
-	r = submit(len, AMDGPU_HW_IP_VCE);
-	CU_ASSERT_EQUAL(r, 0);
-
-	free_resource(&enc.fb[0]);
-}

tests/amdgpu/vm_tests.c

@@ -1,270 +0,0 @@
-/*
- * Copyright 2017 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
-*/
-
-#include "CUnit/Basic.h"
-
-#include "amdgpu_test.h"
-#include "amdgpu_drm.h"
-#include "amdgpu_internal.h"
-
-static  amdgpu_device_handle device_handle;
-static  uint32_t  major_version;
-static  uint32_t  minor_version;
-static  uint32_t  family_id;
-static  uint32_t  chip_id;
-static  uint32_t  chip_rev;
-
-static void amdgpu_vmid_reserve_test(void);
-static void amdgpu_vm_unaligned_map(void);
-static void amdgpu_vm_mapping_test(void);
-
-CU_BOOL suite_vm_tests_enable(void)
-{
-    CU_BOOL enable = CU_TRUE;
-
-	if (amdgpu_device_initialize(drm_amdgpu[0], &major_version,
-				     &minor_version, &device_handle))
-		return CU_FALSE;
-
-	if (device_handle->info.family_id == AMDGPU_FAMILY_SI) {
-		printf("\n\nCurrently hangs the CP on this ASIC, VM suite disabled\n");
-		enable = CU_FALSE;
-	}
-
-	if (amdgpu_device_deinitialize(device_handle))
-		return CU_FALSE;
-
-	return enable;
-}
-
-int suite_vm_tests_init(void)
-{
-	int r;
-
-	r = amdgpu_device_initialize(drm_amdgpu[0], &major_version,
-				   &minor_version, &device_handle);
-
-	if (r) {
-		if ((r == -EACCES) && (errno == EACCES))
-			printf("\n\nError:%s. "
-				"Hint:Try to run this test program as root.",
-				strerror(errno));
-		return CUE_SINIT_FAILED;
-	}
-
-	return CUE_SUCCESS;
-}
-
-int suite_vm_tests_clean(void)
-{
-	int r = amdgpu_device_deinitialize(device_handle);
-
-	if (r == 0)
-		return CUE_SUCCESS;
-	else
-		return CUE_SCLEAN_FAILED;
-}
-
-
-CU_TestInfo vm_tests[] = {
-	{ "resere vmid test",  amdgpu_vmid_reserve_test },
-	{ "unaligned map",  amdgpu_vm_unaligned_map },
-	{ "vm mapping test",  amdgpu_vm_mapping_test },
-	CU_TEST_INFO_NULL,
-};
-
-static void amdgpu_vmid_reserve_test(void)
-{
-	amdgpu_context_handle context_handle;
-	amdgpu_bo_handle ib_result_handle;
-	void *ib_result_cpu;
-	uint64_t ib_result_mc_address;
-	struct amdgpu_cs_request ibs_request;
-	struct amdgpu_cs_ib_info ib_info;
-	struct amdgpu_cs_fence fence_status;
-	uint32_t expired, flags;
-	int i, r;
-	amdgpu_bo_list_handle bo_list;
-	amdgpu_va_handle va_handle;
-	static uint32_t *ptr;
-	struct amdgpu_gpu_info gpu_info = {0};
-	unsigned gc_ip_type;
-
-	r = amdgpu_query_gpu_info(device_handle, &gpu_info);
-	CU_ASSERT_EQUAL(r, 0);
-
-	family_id = device_handle->info.family_id;
-	chip_id = device_handle->info.chip_external_rev;
-	chip_rev = device_handle->info.chip_rev;
-
-	gc_ip_type = (asic_is_gfx_pipe_removed(family_id, chip_id, chip_rev)) ?
-			AMDGPU_HW_IP_COMPUTE : AMDGPU_HW_IP_GFX;
-
-	r = amdgpu_cs_ctx_create(device_handle, &context_handle);
-	CU_ASSERT_EQUAL(r, 0);
-
-	flags = 0;
-	r = amdgpu_vm_reserve_vmid(device_handle, flags);
-	CU_ASSERT_EQUAL(r, 0);
-
-
-	r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096,
-			AMDGPU_GEM_DOMAIN_GTT, 0,
-						    &ib_result_handle, &ib_result_cpu,
-						    &ib_result_mc_address, &va_handle);
-	CU_ASSERT_EQUAL(r, 0);
-
-	r = amdgpu_get_bo_list(device_handle, ib_result_handle, NULL,
-			       &bo_list);
-	CU_ASSERT_EQUAL(r, 0);
-
-	ptr = ib_result_cpu;
-
-	for (i = 0; i < 16; ++i)
-		ptr[i] = 0xffff1000;
-
-	memset(&ib_info, 0, sizeof(struct amdgpu_cs_ib_info));
-	ib_info.ib_mc_address = ib_result_mc_address;
-	ib_info.size = 16;
-
-	memset(&ibs_request, 0, sizeof(struct amdgpu_cs_request));
-	ibs_request.ip_type = gc_ip_type;
-	ibs_request.ring = 0;
-	ibs_request.number_of_ibs = 1;
-	ibs_request.ibs = &ib_info;
-	ibs_request.resources = bo_list;
-	ibs_request.fence_info.handle = NULL;
-
-	r = amdgpu_cs_submit(context_handle, 0,&ibs_request, 1);
-	CU_ASSERT_EQUAL(r, 0);
-
-
-	memset(&fence_status, 0, sizeof(struct amdgpu_cs_fence));
-	fence_status.context = context_handle;
-	fence_status.ip_type = gc_ip_type;
-	fence_status.ip_instance = 0;
-	fence_status.ring = 0;
-	fence_status.fence = ibs_request.seq_no;
-
-	r = amdgpu_cs_query_fence_status(&fence_status,
-			AMDGPU_TIMEOUT_INFINITE,0, &expired);
-	CU_ASSERT_EQUAL(r, 0);
-
-	r = amdgpu_bo_list_destroy(bo_list);
-	CU_ASSERT_EQUAL(r, 0);
-
-	r = amdgpu_bo_unmap_and_free(ib_result_handle, va_handle,
-				     ib_result_mc_address, 4096);
-	CU_ASSERT_EQUAL(r, 0);
-
-	flags = 0;
-	r = amdgpu_vm_unreserve_vmid(device_handle, flags);
-	CU_ASSERT_EQUAL(r, 0);
-
-
-	r = amdgpu_cs_ctx_free(context_handle);
-	CU_ASSERT_EQUAL(r, 0);
-}
-
-static void amdgpu_vm_unaligned_map(void)
-{
-	const uint64_t map_size = (4ULL << 30) - (2 << 12);
-	struct amdgpu_bo_alloc_request request = {};
-	amdgpu_bo_handle buf_handle;
-	amdgpu_va_handle handle;
-	uint64_t vmc_addr;
-	int r;
-
-	request.alloc_size = 4ULL << 30;
-	request.phys_alignment = 4096;
-	request.preferred_heap = AMDGPU_GEM_DOMAIN_VRAM;
-	request.flags = AMDGPU_GEM_CREATE_NO_CPU_ACCESS;
-
-	r = amdgpu_bo_alloc(device_handle, &request, &buf_handle);
-	/* Don't let the test fail if the device doesn't have enough VRAM */
-	if (r)
-		return;
-
-	r = amdgpu_va_range_alloc(device_handle, amdgpu_gpu_va_range_general,
-				  4ULL << 30, 1ULL << 30, 0, &vmc_addr,
-				  &handle, 0);
-	CU_ASSERT_EQUAL(r, 0);
-	if (r)
-		goto error_va_alloc;
-
-	vmc_addr += 1 << 12;
-
-	r = amdgpu_bo_va_op(buf_handle, 0, map_size, vmc_addr, 0,
-			    AMDGPU_VA_OP_MAP);
-	CU_ASSERT_EQUAL(r, 0);
-	if (r)
-		goto error_va_alloc;
-
-	amdgpu_bo_va_op(buf_handle, 0, map_size, vmc_addr, 0,
-			AMDGPU_VA_OP_UNMAP);
-
-error_va_alloc:
-	amdgpu_bo_free(buf_handle);
-}
-
-static void amdgpu_vm_mapping_test(void)
-{
-	struct amdgpu_bo_alloc_request req = {0};
-	struct drm_amdgpu_info_device dev_info;
-	const uint64_t size = 4096;
-	amdgpu_bo_handle buf;
-	uint64_t addr;
-	int r;
-
-	req.alloc_size = size;
-	req.phys_alignment = 0;
-	req.preferred_heap = AMDGPU_GEM_DOMAIN_GTT;
-	req.flags = 0;
-
-	r = amdgpu_bo_alloc(device_handle, &req, &buf);
-	CU_ASSERT_EQUAL(r, 0);
-
-	r = amdgpu_query_info(device_handle, AMDGPU_INFO_DEV_INFO,
-			      sizeof(dev_info), &dev_info);
-	CU_ASSERT_EQUAL(r, 0);
-
-	addr = dev_info.virtual_address_offset;
-	r = amdgpu_bo_va_op(buf, 0, size, addr, 0, AMDGPU_VA_OP_MAP);
-	CU_ASSERT_EQUAL(r, 0);
-
-	addr = dev_info.virtual_address_max - size;
-	r = amdgpu_bo_va_op(buf, 0, size, addr, 0, AMDGPU_VA_OP_MAP);
-	CU_ASSERT_EQUAL(r, 0);
-
-	if (dev_info.high_va_offset) {
-		addr = dev_info.high_va_offset;
-		r = amdgpu_bo_va_op(buf, 0, size, addr, 0, AMDGPU_VA_OP_MAP);
-		CU_ASSERT_EQUAL(r, 0);
-
-		addr = dev_info.high_va_max - size;
-		r = amdgpu_bo_va_op(buf, 0, size, addr, 0, AMDGPU_VA_OP_MAP);
-		CU_ASSERT_EQUAL(r, 0);
-	}
-
-	amdgpu_bo_free(buf);
-}