Eric Anholt
ef9a9d3cd1
Define __iomem for systems without it.
2007-02-07 21:26:01 -08:00
Eric Anholt
8918748058
Add chip family flags to i915 driver, and fix a missing '"' in mach64 ID list.
2007-02-07 21:26:01 -08:00
Thomas Hellstrom
c1fbd8a566
Checkpoint commit.
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Flag handling and memory type selection cleanup.
glxgears won't start.
2007-02-07 17:25:13 +01:00
Thomas Hellstrom
609e3b0375
Implement a policy for selecting memory types.
2007-02-06 14:20:33 +01:00
Stephane Marchesin
17985f07d6
nouveau: more work on the nv04 context switch code.
2007-02-06 01:17:32 +01:00
Stephane Marchesin
8c663b4e56
nouveau: and of course, I was missing the last nv04 piece.
2007-02-03 06:13:27 +01:00
Stephane Marchesin
0c13657c33
nouveau: plugin the nv04 graph init function.
2007-02-03 06:00:29 +01:00
Stephane Marchesin
7ab9e7f36f
nouveau: cleanup the nv04 pgraph save/restore mechanism.
2007-02-03 05:56:42 +01:00
Stephane Marchesin
d69902db3b
nouveau: fix nv04 graph routines for new register names.
2007-02-03 05:25:36 +01:00
Stephane Marchesin
5a072f32c8
nouveau: rename registers to their proper names.
2007-02-03 04:57:06 +01:00
Stephane Marchesin
e64dbef911
nouveau: add NV04 registers required for PGRAPH context switching.
2007-02-03 04:23:09 +01:00
Matthieu Castet
55f7859a25
nouveau: nv ctx switch opps the size of array was wrong
2007-02-02 23:01:03 +01:00
Matthieu Castet
63cf3b3da7
nouveau: nv10 ctx switch, some regs are nv17+ only
2007-02-02 20:08:33 +01:00
Thomas Hellstrom
6c04185857
via: Try to improve command-buffer chaining.
...
Bump driver date and patchlevel.
2007-02-02 09:22:30 +01:00
Thomas Hellstrom
70bba11bc7
Disable AGP DMA for chips with the new 3D engine.
2007-02-02 09:22:15 +01:00
Thomas Hellstrom
3024f23c65
memory manager: Make device driver aware of different memory types.
...
Memory types are either fixed (on-card or pre-bound AGP) or not fixed
(dynamically bound) to an aperture. They also carry information about:
1) Whether they can be mapped cached.
2) Whether they are at all mappable.
3) Whether they need an ioremap to be accessible from kernel space.
In this way VRAM memory and, for example, pre-bound AGP appear
identical to the memory manager.
This also makes support for unmappable VRAM simple to implement.
2007-01-31 14:50:57 +01:00
Ben Skeggs
ee4ac5c897
nouveau: determine chipset type at startup, instead of every time we use it.
2007-01-28 23:48:33 +11:00
Matthieu Castet
c744bfde2d
make works ctx switch on nv10.
2007-01-26 21:57:44 +01:00
Patrice Mandin
9c03ca81e7
nouveau: oops, wrong indexing in nv17 regs
2007-01-26 21:05:59 +01:00
Patrice Mandin
5534c90ff3
nouveau: read gpu type once
2007-01-26 19:54:35 +01:00
Patrice Mandin
05d3ed472e
nouveau: only save/restore nv17 regs on nv17,18 hw
2007-01-26 19:25:49 +01:00
Patrice Mandin
e7ba15a003
nouveau: add extra pgraph registers
2007-01-26 19:24:34 +01:00
Patrice Mandin
d4c9f135b5
nouveau: add some nv10 pgraph defines
2007-01-26 18:10:31 +01:00
Patrice Mandin
6d9ef1a960
nouveau: simplify and fix BIG_ENDIAN flags
2007-01-25 23:06:48 +01:00
Ben Skeggs
90ae39d2f0
nouveau: nv4c default context
2007-01-25 11:11:01 +11:00
Ben Skeggs
aa7266385e
nouveau: always print nsource/nstatus regs on PGRAPH errors
2007-01-25 08:16:23 +11:00
Zou Nan hai
7d4e6b1445
vblank interrupt fix
2007-01-24 16:33:21 +08:00
Ben Skeggs
19ba074938
nouveau: fix getparam from 32-bit client on 64-bit kernel
2007-01-19 15:41:51 +11:00
Ben Skeggs
4291df69bd
nouveau: re-add 6150 Go pciid (0x0244)
2007-01-19 15:16:18 +11:00
Jeremy Kolb
a40de938fa
nouveau: cleanup nv30_graph.c
2007-01-18 21:40:21 -05:00
Jeremy Kolb
ab72a7714e
nouveau: Remove write to CTX_SIZE. This gives us proper nv3x PGRAPH switching.
2007-01-18 21:40:21 -05:00
Dave Jones
bd0418cb01
add missing quadro id
2007-01-18 17:35:28 +11:00
Jeremy Kolb
78a4f5c1bc
nouveau: Try to get nv35 pgraph switching working. Doesn't quite yet.
...
Hook into nv20 pgraph switching functions (they're identical for nv3x).
Actually call nv30_pgraph_context_init so the ctx_table is allocated.
Thanks to Carlos Martin for the help.
2007-01-17 08:46:59 -05:00
Matthieu Castet
fdbc34fab0
nouveau: opps nv20 ctx ramin size was wrong
2007-01-14 20:04:20 +01:00
Matthieu Castet
06cd155595
nouveau: opps restored the wrong channel
2007-01-13 23:30:43 +01:00
Matthieu Castet
f04347f371
nouveau: nv20 graph ctx switch.
...
Untested...
2007-01-13 23:19:41 +01:00
Matthieu Castet
cd5f543b2f
nouveau: first step to make graph ctx works
...
It is still not working, but now we could use some 3D commands
without needed to run nvidia blob before.
2007-01-13 21:44:50 +01:00
Matthieu Castet
4ae64a1b58
nouveau: add and indent pgraph regs
2007-01-13 21:44:50 +01:00
Stephane Marchesin
1967aa82cf
nouveau: Oops, fix the nv04 RAMFC_DMA_FETCH value.
2007-01-13 12:32:50 +01:00
Matthieu Castet
1bad7e0d02
nouveau : remove useless init : we clear RAMIN before
2007-01-12 20:31:18 +01:00
Haihao Xiang
9d3deddc4a
Delay for a usec while spinning waiting for ring buffer space.
...
This means the loop will wait up to ~10ms for ring buffer space to become
available, rather than just however long it takes to check the space 10000
times. This matches other drivers' behavior when waiting for ring buffer/fifo
space.
2007-01-12 11:24:50 -08:00
Jeremy Kolb
4297a83b48
nouveau: get nv30 context switching to work.
...
* Pulled in some registers from nv10reg.h. Needed for context switching.
* Filled in nv30 graphics context (based on nv40_graph.c).
* Figure out nv30 context table, set up on context creation. Allows the cards automatic switching to work.
2007-01-12 00:14:54 -05:00
Michel Dänzer
8ff026723c
radeon: Fix u32 overflows when determining AGP base address in card space.
...
The overflows could lead to the AGP aperture overlapping the framebuffer area
in the card's address space when the latter is located at the very end of the
32 bit address space, which would result in a freeze on X server startup,
probably because the card read commands from the framebuffer instead of from
AGP.
See http://bugs.debian.org/cgi-bin/bugreport.cgi?bug=392915 .
2007-01-11 09:02:07 +01:00
Dave Airlie
a70aedd5fc
novueau: try resource 3 if resource 2 is 0 length
...
This happens on my NV43 PPC
2007-01-09 13:48:38 +11:00
Stephane Marchesin
deba42ef32
nouveau: fix nv4a context size.
2007-01-08 20:55:57 +01:00
Stephane Marchesin
d0080d71b9
nouveau: nv4a context support.
2007-01-08 05:02:40 +01:00
Stephane Marchesin
6eaa1272b4
Merge branch 'master' of git+ssh://marcheu@git.freedesktop.org/git/mesa/drm
2007-01-08 03:50:34 +01:00
Ben Skeggs
26bf6d9b5b
nouveau: oops
2007-01-08 12:50:44 +11:00
Ben Skeggs
128d87a3dd
nouveau: nv43 context stuff
2007-01-08 12:47:51 +11:00
Stephane Marchesin
1f0f7d7a18
nouveau: fix a stupid bug from me.
2007-01-08 00:11:39 +01:00
