Commit graph

14 commits

Author SHA1 Message Date
Kenneth Graunke
ca678bc073 intel: Fix Haswell CRW PCI IDs.
The second digit was off by one, which meant we accidentally treated
GT(n) as GT(n-1).  This also meant no support for GT1 at all.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2013-03-28 13:24:15 -07:00
Ville Syrjälä
93d12593e5 intel_chipset: Fix up VLV confusion
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
2013-03-27 11:13:44 +02:00
Ville Syrjälä
6e55fd7dee intel_chipset: Use parens around macro arguments
Protect the macro argument evaluations with parens.

This is already touching most lines, so while at it, fix up all white
space to uniform style throughout the file.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
2013-03-27 11:13:44 +02:00
Ben Widawsky
36d18211b1 intel_chipset: Merge intel-gpu-tools chipsets
Intel GPU Tools is newer and arguably better. This change doesn't
completely merge the files because it's a bit simpler if we move the
I9XX macro over to Intel GPU Tools, and don't move over a few macros
from IGT that libdrm doesn't care about.

It has been discussed, and would seem even easier if Intel GPU Tools
simply used the libdrm header files. Whether or not we move to that,
this should help that effort.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Acked-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2013-02-11 15:25:48 -08:00
Jesse Barnes
ef866c7293 intel: add more VLV PCI IDs 2013-02-02 11:10:24 +01:00
Jesse Barnes
9d9cb8553c intel: add support for ValleyView
Just some PCI ID stuff to enable the right features.
2012-09-13 11:50:59 -07:00
Paulo Zanoni
93fef04b1e intel: add more Haswell PCI IDs
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
2012-08-08 15:38:12 -03:00
Eugeni Dodonov
e057a56448 intel: add Ivy Bridge GT2 server variant
We were missing this one and it is being used by Bromolow.

Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
2012-04-01 11:03:36 -03:00
Kenneth Graunke
617213357e intel: Add some PCI IDs for Haswell.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
2012-03-22 13:52:29 -07:00
Eric Anholt
1d318e2a79 intel: intel: Add IS_GEN[567] macros.
These will be used by intel_decode.c, and were taken from intel-gpu-tools.

Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Acked-by: Eugeni Dodonov <eugeni@dodonov.net>
2011-12-29 16:43:29 -08:00
Eric Anholt
078bc5b6ee intel: Make intel_chipset handle devid directly.
This will make these macros reusable from intel_decode.c, which
doesn't have a bufmgr_gem context, without faking the struct.  We
should generally only be using these macros from bufmgr_gem context
setup anyway.

Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Acked-by: Eugeni Dodonov <eugeni@dodonov.net>
2011-12-29 16:43:27 -08:00
Jesse Barnes
b50964027b libdrm/intel: execbuf2 support
This patch to libdrm adds support for the new execbuf2 ioctl.  If
detected, it will be used instead of the old ioctl.  By using the new
drm_intel_bufmgr_gem_enable_fenced_relocs(), you can indicate that any
time a fence register is actually required for a relocation target you
will call drm_intel_bo_emit_reloc_fence instead of
drm_intel_bo_emit_reloc, which will reduce fence register pressure.

Signed-off-by: Eric Anholt <eric@anholt.net>
2010-03-02 10:10:50 -08:00
Eric Anholt
f6dc964e1d intel: Add initial support for Sandybridge, and clean up the #defines. 2010-02-25 10:41:03 -08:00
Kristian Høgsberg
4f57abfe66 Move libdrm/ up one level 2009-11-17 11:15:06 -05:00
Renamed from libdrm/intel/intel_chipset.h (Browse further)