Commit graph

1449 commits

Author SHA1 Message Date
Kristian Høgsberg
373dbcf8b2 i915: Add a dri2 init path that gets the lock from the dri2 sarea. 2008-02-13 13:34:02 -05:00
Kristian Høgsberg
db3f03ae35 i915: Only look up dev_priv->mmio_map if it's not already set up 2008-02-13 13:34:02 -05:00
Kristian Høgsberg
ee15459483 i915: Add I915_PARAM_CHIPSET_ID param to get chipset ID. 2008-02-13 13:34:02 -05:00
Kristian Høgsberg
4feb0638f1 i915: Make sarea_priv setup optional. 2008-02-13 13:34:02 -05:00
Jesse Barnes
6f19473191 Fix saveGR array size
Make sure we have enough room for all the GR registers or we'll end up
clobbering the AR index register (which should actually be harmless
unless the BIOS is making an assumption about it).
2008-02-07 11:21:09 -08:00
Jesse Barnes
8b6c96dedd i915: save/restore interrupt state
On resume, if the interrupt state isn't restored correctly, we may end
up with a flood of unexpected or ill-timed interrupts, which could cause
the kernel to disable the interrupt or vblank events to happen at the
wrong time.  So save/restore them properly.
2008-02-07 10:48:08 -08:00
Thomas Hellstrom
76748efae2 i915: Re-report breadcrumbs on poll to the fence manager,
since a breadcrumb may actually turn up before a corresponding fence object
has been placed on the fence ring.
2008-02-05 10:36:49 +01:00
Stuart Bennett
a0781e7622 nouveau: make nv34 work every time, not just every 2nd time
And make nv30_graph_init a bit more like mmio-traces
2008-02-04 16:38:31 +00:00
Maarten Maathuis
733e07663e nouveau: NV40 can/should now be able to run after the blob.
- Moved the fix from the ddx to drm, because it seemed more appropriate.
- Don't be shy, report if it works for you or not.
2008-02-02 12:46:47 +01:00
Thomas Hellstrom
47ee6237fe i915: Avoid calling drm_fence_flush_old excessively. 2008-01-30 22:14:02 +01:00
Thomas Hellstrom
f1edb7ad91 Simplify the fencing code and differentiate between flushes and
waiting types.
Add a "command_stream_barrier" method to the bo driver.
2008-01-30 22:06:02 +01:00
Ben Skeggs
9a7e45858d nv40: some more nv67 changes
With some luck the drm-side will be OK now for this chipset.
2008-01-30 11:50:17 +11:00
Mirko
0744cb153a Add new RV380 pci id
bug 14289
2008-01-29 10:11:27 -05:00
Maciej Cencora
b8755ff7c3 drm: add initial rs690 support for drm.
This adds support for configuring the RS690 GART.
2008-01-27 12:50:31 +10:00
George Sapountzis
6bfb9b639a mach64: fix after vblank-rework
don't disable vblank interrupts (similar to r128)
2008-01-25 16:54:29 +02:00
Jesse Barnes
bfdddd218e Fixup modeset ioctl number & typedef usage
Should be 0x08 rather than 0xa0, and shouldn't use typedefs.
2008-01-24 21:13:33 -08:00
Eric Anholt
e3c42f0004 Merge commit 'airlied/i915-ttm-cfu'
This requires updated Mesa to handle the new relocation format.
2008-01-24 12:44:19 -08:00
Jesse Barnes
c7ee6cc269 Remove broken 'in vblank' accounting
We need to return an accurate vblank count to the callers of
->get_vblank_counter, and in the Intel case the actual frame count
register isn't udpated until the next active line is displayed, so we
need to return one more than the frame count register if we're currently
in a vblank period.

However, none of the various ways of doing this is working yet, so
disable the logic for now.  This may result in a few missed events, but
should fix the hangs some people have seen due to the current code
tripping the wraparound logic in drm_update_vblank_count.
2008-01-24 08:57:04 -08:00
Dave Airlie
5b99306452 i915: fix missing header when copying data from userspace 2008-01-24 15:18:09 +10:00
Dave Airlie
34b71eb451 i915 make relocs use copy from user
Switch relocs to using copy from user and remove index and pass buffer
handles in instead.
2008-01-24 14:37:40 +10:00
Jesse Barnes
b5a34f5da5 Fix thinko in get_vblank_counter
Should use vtotal not htotal to figure out if we're in a vblank period.
2008-01-23 08:39:57 -08:00
Jesse Barnes
cb91784371 Fix IS_I915G macro
One to many parantheses...
2008-01-23 08:38:01 -08:00
Maarten Maathuis
7c726086dd nouveau: Fix warning in nouveau_mem.c 2008-01-23 16:40:19 +01:00
Dave Airlie
2f19fe4498 drm/i915: add support for E7221 2008-01-23 16:44:51 +10:00
Jesse Barnes
531f25cfe9 Correct vblank count value
The frame count registers don't increment until the start of the next
frame, so make sure we return an incremented count if called during the
actual vblank period.
2008-01-22 15:16:01 -08:00
Jesse Barnes
893e311999 i915 irq fixes
Ack the IRQs correctly (PIPExSTAT first followed by IIR).  Don't read
vblank counter registers on disabled pipes (might hang otherwise).  And
deal with flipped pipe/plane mappings if present.
2008-01-22 13:11:29 -08:00
Jesse Barnes
0cd4cbc9a6 Merge branch 'master' into vblank-rework, including mach64 support
Conflicts:

	linux-core/drmP.h
	linux-core/drm_drv.c
	shared-core/i915_drv.h
	shared-core/i915_irq.c
	shared-core/mga_irq.c
	shared-core/radeon_irq.c
	shared-core/via_irq.c

Mostly trivial conflicts.

mach64 support from Mathieu Bérard.
2008-01-22 09:42:37 -08:00
Dave Airlie
5231a524f5 Revert "Fix pipe<->plane mapping vs. vblank handling (again)"
This reverts commit bfc29606e4.

This regresses i915 here for me I can't get greater than 0.333 fps with gears
2008-01-22 14:42:48 +11:00
Stephane Marchesin
616cef5ec8 nouveau: don't forget NV80. 2008-01-21 21:11:47 +01:00
Stephane Marchesin
641c9a2ecc nouveau: new card family for old card designs. 2008-01-21 21:01:28 +01:00
Eric Anholt
44a9fa8cc6 Add additional explanation of DRM_BO_FLAG_CACHED_MAPPED before I forget again. 2008-01-17 16:55:43 -08:00
Zhenyu Wang
ac6b3780c8 i915: Add chipset id for Intel Integrated Graphics Device
This adds new chipset id in drm.

Signed-off-by: Zhenyu Wang <zhenyu.z.wang@intel.com>
2008-01-15 13:06:09 -05:00
Thomas Hellstrom
88c511e49d Properly propagate the user-space fence flags.
This avoids a sync flush when user-space has already programmed
and MI_FLUSH in the batchbuffer.
2008-01-15 10:03:41 +01:00
Stephane Marchesin
269d518008 nouveau: make mem alloc debug a little more verbose. 2008-01-14 03:16:42 +01:00
Ben Skeggs
f0b7c45653 nv05: enable ctx/op methods, and ignore patch valid failures.
Yes, I'm quite aware "real" nv04 doesn't support this, hopefully the GPU
will just ignore those PGRAPH_DEBUG_3 bits on that hw.
2008-01-11 12:51:08 +11:00
Stuart Bennett
5f15f317fb nouveau: AGP reset correction - don't touch FW bit 2008-01-08 20:30:21 +00:00
Ben Skeggs
0bfd09f719 nv50: more small changes 2008-01-07 18:56:44 +11:00
Ben Skeggs
942b500e24 nv50: oops, lost some state saving along the way somewhere.
xf86-video-nv will now work again after nouveau.
2008-01-07 18:19:16 +11:00
Ben Skeggs
3d248cd7e4 nv50: hook up timer funcs... 2008-01-07 17:23:31 +11:00
Ben Skeggs
7a4ba7273c nv50: abort on chips without ctx ucode 2008-01-07 17:13:22 +11:00
Ben Skeggs
15f8fd34df nv50: some needed ctx vals 2008-01-07 17:09:00 +11:00
Ben Skeggs
3d3d509dca nv50: some cleanups + small changes 2008-01-07 17:08:59 +11:00
Stephane Marchesin
cd19dcef4f Nouveau: ppc oops. 2008-01-07 06:11:33 +01:00
Stephane Marchesin
de522ae742 Nouveau: move PPC bios copy to firstopen. 2008-01-07 05:54:37 +01:00
Jeremy Kolb
bd5d760a10 nouveau: Add ctx_voodoo for NV86 2008-01-06 10:09:47 -05:00
Xavier Bachelot
30fba69a68 via: add P4M900 pci id.
bug 12108
2008-01-04 16:29:04 +10:00
Stuart Bennett
71adbfc874 [PATCH] nouveau: reset AGP on init for < nv40
This is necessary for AGP to work after running bios init scripts on nv3x, and
is seen in mmio traces of all cards (nv04-nv4x)

I'm not making the equivalent change to nv40_mc.c, as early cards (6200, 6800gt)
use the 0x000018XX PBUS and later cards use the 0x000880XX PBUS and I don't know
the effects of using the wrong one
2008-01-04 05:08:15 +01:00
Stuart Bennett
381724a35b [PATCH] nouveau: Fix nv20/30 context loading
Don't set the context as valid until it has been loaded
2008-01-04 05:07:35 +01:00
Dave Airlie
78d6649069 mach64: some more minor cleanups 2008-01-03 17:44:04 +10:00
Dave Airlie
97b8c9591c mach64: cleanup some of the macro formatting 2008-01-03 17:10:30 +10:00