the ring as they are sent by the client (enabled with
MACH64_NO_BATCH_DISPATCH). For the "no batch dispatch" path:
- The DMA end of list flag is moved in the COMMIT_RING macro.
- The flush function only starts a new pass if the card has gone idle and
there are descriptors on the ring still unprocessed. This could be
better optimized to flush only when there is a large enough queue on
the card, but we'll always need to flush if we run out of freeable
buffers.
- This path is working up to a point, but lockups still occur. There is a
small performance improvement.
done with the pattern registers which is not ideal, but works. There
are still lots of places where optimizing is needed. We need to do the
minimum required to sync with the X server on context switches, since
right now things slow down whenever the mouse is moved.
mach64-0-0-3-dma-branch)
- I've partly filled in the dma_dispatch implementation from the vertex
dispatch code. We still need to deal with adding a register reset
buffer to the end of the dma pass. The freelist and blits are also
still to be filled in.
- I've added XF86Config options for the driver: ForcePCIMode - Don't use
AGP for buffers/textures, even if agpgart is present PseudoDMAMode -
Dispatch DMA buffers with MMIO, one register at a time. AgpMode - 1 or
2 AgpSize - Size of AGP aperture to use for allocations BufferSize -
Size of vertex buffers in MB (1 or 2)
