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i915: register definition & header file cleanup

Browse source 
It would be nice if one day the DRM driver was the canonical source for
register definitions and core macros.  To that end, this patch cleans
things up quite a bit, removing redundant definitions (some with
different names referring to the same register) and generally tidying up
the header file.
This commit is contained in:
Jesse Barnes 2008-05-13 14:44:17 -07:00
parent d32ce7f621
commit ee631e1b86
9 changed files with 775 additions and 1084 deletions
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59
linux-core/i915_drv.c
View file

@ -67,11 +67,6 @@ static struct drm_bo_driver i915_bo_driver = {
};
#endif
enum pipe {
PIPE_A = 0,
PIPE_B,
};
static bool i915_pipe_enabled(struct drm_device *dev, enum pipe pipe)
{
struct drm_i915_private *dev_priv = dev->dev_private;
@ -308,13 +303,13 @@ static int i915_suspend(struct drm_device *dev, pm_message_t state)
dev_priv->saveDSPASTRIDE = I915_READ(DSPASTRIDE);
dev_priv->saveDSPASIZE = I915_READ(DSPASIZE);
dev_priv->saveDSPAPOS = I915_READ(DSPAPOS);
dev_priv->saveDSPABASE = I915_READ(DSPABASE);
dev_priv->saveDSPAADDR = I915_READ(DSPAADDR);
if (IS_I965G(dev)) {
dev_priv->saveDSPASURF = I915_READ(DSPASURF);
dev_priv->saveDSPATILEOFF = I915_READ(DSPATILEOFF);
}
i915_save_palette(dev, PIPE_A);
dev_priv->savePIPEASTAT = I915_READ(I915REG_PIPEASTAT);
dev_priv->savePIPEASTAT = I915_READ(PIPEASTAT);
/* Pipe & plane B info */
dev_priv->savePIPEBCONF = I915_READ(PIPEBCONF);
@ -336,13 +331,13 @@ static int i915_suspend(struct drm_device *dev, pm_message_t state)
dev_priv->saveDSPBSTRIDE = I915_READ(DSPBSTRIDE);
dev_priv->saveDSPBSIZE = I915_READ(DSPBSIZE);
dev_priv->saveDSPBPOS = I915_READ(DSPBPOS);
dev_priv->saveDSPBBASE = I915_READ(DSPBBASE);
dev_priv->saveDSPBADDR = I915_READ(DSPBADDR);
if (IS_I965GM(dev) || IS_IGD_GM(dev)) {
dev_priv->saveDSPBSURF = I915_READ(DSPBSURF);
dev_priv->saveDSPBTILEOFF = I915_READ(DSPBTILEOFF);
}
i915_save_palette(dev, PIPE_B);
dev_priv->savePIPEBSTAT = I915_READ(I915REG_PIPEBSTAT);
dev_priv->savePIPEBSTAT = I915_READ(PIPEBSTAT);
/* CRT state */
dev_priv->saveADPA = I915_READ(ADPA);
@ -357,9 +352,9 @@ static int i915_suspend(struct drm_device *dev, pm_message_t state)
dev_priv->saveLVDS = I915_READ(LVDS);
if (!IS_I830(dev) && !IS_845G(dev))
dev_priv->savePFIT_CONTROL = I915_READ(PFIT_CONTROL);
dev_priv->saveLVDSPP_ON = I915_READ(LVDSPP_ON);
dev_priv->saveLVDSPP_OFF = I915_READ(LVDSPP_OFF);
dev_priv->savePP_CYCLE = I915_READ(PP_CYCLE);
dev_priv->savePP_ON_DELAYS = I915_READ(PP_ON_DELAYS);
dev_priv->savePP_OFF_DELAYS = I915_READ(PP_OFF_DELAYS);
dev_priv->savePP_DIVISOR = I915_READ(PP_DIVISOR);
/* FIXME: save TV & SDVO state */
@ -370,19 +365,19 @@ static int i915_suspend(struct drm_device *dev, pm_message_t state)
dev_priv->saveFBC_CONTROL = I915_READ(FBC_CONTROL);
/* Interrupt state */
dev_priv->saveIIR = I915_READ(I915REG_INT_IDENTITY_R);
dev_priv->saveIER = I915_READ(I915REG_INT_ENABLE_R);
dev_priv->saveIMR = I915_READ(I915REG_INT_MASK_R);
dev_priv->saveIIR = I915_READ(IIR);
dev_priv->saveIER = I915_READ(IER);
dev_priv->saveIMR = I915_READ(IMR);
/* VGA state */
dev_priv->saveVCLK_DIVISOR_VGA0 = I915_READ(VCLK_DIVISOR_VGA0);
dev_priv->saveVCLK_DIVISOR_VGA1 = I915_READ(VCLK_DIVISOR_VGA1);
dev_priv->saveVCLK_POST_DIV = I915_READ(VCLK_POST_DIV);
dev_priv->saveVGA0 = I915_READ(VGA0);
dev_priv->saveVGA1 = I915_READ(VGA1);
dev_priv->saveVGA_PD = I915_READ(VGA_PD);
dev_priv->saveVGACNTRL = I915_READ(VGACNTRL);
/* Clock gating state */
dev_priv->saveD_STATE = I915_READ(D_STATE);
dev_priv->saveDSPCLK_GATE_D = I915_READ(DSPCLK_GATE_D);
dev_priv->saveCG_2D_DIS = I915_READ(CG_2D_DIS);
/* Cache mode state */
dev_priv->saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0);
@ -419,6 +414,8 @@ static int i915_resume(struct drm_device *dev)
if (pci_enable_device(dev->pdev))
return -1;
DRM_INFO("resuming i915\n");
pci_write_config_byte(dev->pdev, LBB, dev_priv->saveLBB);
I915_WRITE(DSPARB, dev_priv->saveDSPARB);
@ -452,7 +449,7 @@ static int i915_resume(struct drm_device *dev)
I915_WRITE(DSPASIZE, dev_priv->saveDSPASIZE);
I915_WRITE(DSPAPOS, dev_priv->saveDSPAPOS);
I915_WRITE(PIPEASRC, dev_priv->savePIPEASRC);
I915_WRITE(DSPABASE, dev_priv->saveDSPABASE);
I915_WRITE(DSPAADDR, dev_priv->saveDSPAADDR);
I915_WRITE(DSPASTRIDE, dev_priv->saveDSPASTRIDE);
if (IS_I965G(dev)) {
I915_WRITE(DSPASURF, dev_priv->saveDSPASURF);
@ -464,10 +461,11 @@ static int i915_resume(struct drm_device *dev)
i915_restore_palette(dev, PIPE_A);
/* Enable the plane */
I915_WRITE(DSPACNTR, dev_priv->saveDSPACNTR);
I915_WRITE(DSPABASE, I915_READ(DSPABASE));
I915_WRITE(DSPAADDR, I915_READ(DSPAADDR));
/* Pipe & plane B info */
if (dev_priv->saveDPLL_B & DPLL_VCO_ENABLE) {
DRM_INFO("restoring DPLL_B: 0x%08x\n", dev_priv->saveDPLL_B);
I915_WRITE(DPLL_B, dev_priv->saveDPLL_B &
~DPLL_VCO_ENABLE);
udelay(150);
@ -476,6 +474,7 @@ static int i915_resume(struct drm_device *dev)
I915_WRITE(FPB1, dev_priv->saveFPB1);
/* Actually enable it */
I915_WRITE(DPLL_B, dev_priv->saveDPLL_B);
DRM_INFO("restoring DPLL_B: 0x%08x\n", dev_priv->saveDPLL_B);
udelay(150);
if (IS_I965G(dev))
I915_WRITE(DPLL_B_MD, dev_priv->saveDPLL_B_MD);
@ -494,7 +493,7 @@ static int i915_resume(struct drm_device *dev)
I915_WRITE(DSPBSIZE, dev_priv->saveDSPBSIZE);
I915_WRITE(DSPBPOS, dev_priv->saveDSPBPOS);
I915_WRITE(PIPEBSRC, dev_priv->savePIPEBSRC);
I915_WRITE(DSPBBASE, dev_priv->saveDSPBBASE);
I915_WRITE(DSPBADDR, dev_priv->saveDSPBADDR);
I915_WRITE(DSPBSTRIDE, dev_priv->saveDSPBSTRIDE);
if (IS_I965G(dev)) {
I915_WRITE(DSPBSURF, dev_priv->saveDSPBSURF);
@ -506,7 +505,7 @@ static int i915_resume(struct drm_device *dev)
i915_restore_palette(dev, PIPE_B);
/* Enable the plane */
I915_WRITE(DSPBCNTR, dev_priv->saveDSPBCNTR);
I915_WRITE(DSPBBASE, I915_READ(DSPBBASE));
I915_WRITE(DSPBADDR, I915_READ(DSPBADDR));
/* CRT state */
I915_WRITE(ADPA, dev_priv->saveADPA);
@ -521,9 +520,9 @@ static int i915_resume(struct drm_device *dev)
I915_WRITE(PFIT_PGM_RATIOS, dev_priv->savePFIT_PGM_RATIOS);
I915_WRITE(BLC_PWM_CTL, dev_priv->saveBLC_PWM_CTL);
I915_WRITE(LVDSPP_ON, dev_priv->saveLVDSPP_ON);
I915_WRITE(LVDSPP_OFF, dev_priv->saveLVDSPP_OFF);
I915_WRITE(PP_CYCLE, dev_priv->savePP_CYCLE);
I915_WRITE(PP_ON_DELAYS, dev_priv->savePP_ON_DELAYS);
I915_WRITE(PP_OFF_DELAYS, dev_priv->savePP_OFF_DELAYS);
I915_WRITE(PP_DIVISOR, dev_priv->savePP_DIVISOR);
I915_WRITE(PP_CONTROL, dev_priv->savePP_CONTROL);
/* FIXME: restore TV & SDVO state */
@ -536,14 +535,14 @@ static int i915_resume(struct drm_device *dev)
/* VGA state */
I915_WRITE(VGACNTRL, dev_priv->saveVGACNTRL);
I915_WRITE(VCLK_DIVISOR_VGA0, dev_priv->saveVCLK_DIVISOR_VGA0);
I915_WRITE(VCLK_DIVISOR_VGA1, dev_priv->saveVCLK_DIVISOR_VGA1);
I915_WRITE(VCLK_POST_DIV, dev_priv->saveVCLK_POST_DIV);
I915_WRITE(VGA0, dev_priv->saveVGA0);
I915_WRITE(VGA1, dev_priv->saveVGA1);
I915_WRITE(VGA_PD, dev_priv->saveVGA_PD);
udelay(150);
/* Clock gating state */
I915_WRITE (D_STATE, dev_priv->saveD_STATE);
I915_WRITE (DSPCLK_GATE_D, dev_priv->saveDSPCLK_GATE_D);
I915_WRITE (CG_2D_DIS, dev_priv->saveCG_2D_DIS);
/* Cache mode state */
I915_WRITE (CACHE_MODE_0, dev_priv->saveCACHE_MODE_0 | 0xffff0000);

2
linux-core/i915_fence.c
View file

@ -46,7 +46,7 @@ static inline void i915_initiate_rwflush(struct drm_i915_private *dev_priv,
dev_priv->flush_sequence = (uint32_t) READ_BREADCRUMB(dev_priv);
dev_priv->flush_flags = fc->pending_flush;
dev_priv->saved_flush_status = READ_HWSP(dev_priv, 0);
I915_WRITE(I915REG_INSTPM, (1 << 5) | (1 << 21));
I915_WRITE(INSTPM, (1 << 5) | (1 << 21));
dev_priv->flush_pending = 1;
fc->pending_flush &= ~DRM_I915_FENCE_TYPE_RW;
}

52
linux-core/intel_display.c
View file

@ -367,7 +367,7 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y)
struct intel_crtc *intel_crtc = crtc->driver_private;
int pipe = intel_crtc->pipe;
unsigned long Start, Offset;
int dspbase = (pipe == 0 ? DSPABASE : DSPBBASE);
int dspbase = (pipe == 0 ? DSPAADDR : DSPBADDR);
int dspsurf = (pipe == 0 ? DSPASURF : DSPBSURF);
int dspstride = (pipe == 0) ? DSPASTRIDE : DSPBSTRIDE;
int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR;
@ -456,7 +456,7 @@ static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
int pipe = intel_crtc->pipe;
int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR;
int dspbase_reg = (pipe == 0) ? DSPABASE : DSPBBASE;
int dspbase_reg = (pipe == 0) ? DSPAADDR : DSPBADDR;
int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
u32 temp;
bool enabled;
@ -617,16 +617,16 @@ static int intel_get_core_clock_speed(struct drm_device *dev)
else if (IS_I915GM(dev)) {
u16 gcfgc = 0;
pci_read_config_word(dev->pdev, I915_GCFGC, &gcfgc);
pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
if (gcfgc & I915_LOW_FREQUENCY_ENABLE)
if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
return 133000;
else {
switch (gcfgc & I915_DISPLAY_CLOCK_MASK) {
case I915_DISPLAY_CLOCK_333_MHZ:
switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
case GC_DISPLAY_CLOCK_333_MHZ:
return 333000;
default:
case I915_DISPLAY_CLOCK_190_200_MHZ:
case GC_DISPLAY_CLOCK_190_200_MHZ:
return 190000;
}
}
@ -635,20 +635,20 @@ static int intel_get_core_clock_speed(struct drm_device *dev)
else if (IS_I855(dev)) {
#if 0
PCITAG bridge = pciTag(0, 0, 0); /* This is always the host bridge */
u16 hpllcc = pciReadWord(bridge, I855_HPLLCC);
u16 hpllcc = pciReadWord(bridge, HPLLCC);
#endif
u16 hpllcc = 0;
/* Assume that the hardware is in the high speed state. This
* should be the default.
*/
switch (hpllcc & I855_CLOCK_CONTROL_MASK) {
case I855_CLOCK_133_200:
case I855_CLOCK_100_200:
switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
case GC_CLOCK_133_200:
case GC_CLOCK_100_200:
return 200000;
case I855_CLOCK_166_250:
case GC_CLOCK_166_250:
return 250000;
case I855_CLOCK_100_133:
case GC_CLOCK_100_133:
return 133000;
}
} else /* 852, 830 */
@ -961,24 +961,6 @@ void intel_crtc_load_lut(struct drm_crtc *crtc)
}
}
#define CURSOR_A_CONTROL 0x70080
#define CURSOR_A_BASE 0x70084
#define CURSOR_A_POSITION 0x70088
#define CURSOR_B_CONTROL 0x700C0
#define CURSOR_B_BASE 0x700C4
#define CURSOR_B_POSITION 0x700C8
#define CURSOR_MODE_DISABLE 0x00
#define CURSOR_MODE_64_32B_AX 0x07
#define CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX)
#define MCURSOR_GAMMA_ENABLE (1 << 26)
#define CURSOR_POS_MASK 0x007FF
#define CURSOR_POS_SIGN 0x8000
#define CURSOR_X_SHIFT 0
#define CURSOR_Y_SHIFT 16
static int intel_crtc_cursor_set(struct drm_crtc *crtc,
struct drm_buffer_object *bo,
uint32_t width, uint32_t height)
@ -987,8 +969,8 @@ static int intel_crtc_cursor_set(struct drm_crtc *crtc,
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_crtc *intel_crtc = crtc->driver_private;
int pipe = intel_crtc->pipe;
uint32_t control = (pipe == 0) ? CURSOR_A_CONTROL : CURSOR_B_CONTROL;
uint32_t base = (pipe == 0) ? CURSOR_A_BASE : CURSOR_B_BASE;
uint32_t control = (pipe == 0) ? CURACNTR : CURBCNTR;
uint32_t base = (pipe == 0) ? CURABASE : CURBBASE;
uint32_t temp;
size_t addr;
@ -1063,8 +1045,8 @@ static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
temp |= ((y & CURSOR_POS_MASK) << CURSOR_Y_SHIFT);
adder = intel_crtc->cursor_addr;
I915_WRITE((pipe == 0) ? CURSOR_A_POSITION : CURSOR_B_POSITION, temp);
I915_WRITE((pipe == 0) ? CURSOR_A_BASE : CURSOR_B_BASE, adder);
I915_WRITE((pipe == 0) ? CURAPOS : CURBPOS, temp);
I915_WRITE((pipe == 0) ? CURABASE : CURBBASE, adder);
return 0;
}

12
linux-core/intel_lvds.c
View file

@ -106,10 +106,10 @@ static void intel_lvds_save(struct drm_output *output)
struct drm_device *dev = output->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
dev_priv->savePP_ON = I915_READ(LVDSPP_ON);
dev_priv->savePP_OFF = I915_READ(LVDSPP_OFF);
dev_priv->savePP_ON = I915_READ(PP_ON_DELAYS);
dev_priv->savePP_OFF = I915_READ(PP_OFF_DELAYS);
dev_priv->savePP_CONTROL = I915_READ(PP_CONTROL);
dev_priv->savePP_CYCLE = I915_READ(PP_CYCLE);
dev_priv->savePP_DIVISOR = I915_READ(PP_DIVISOR);
dev_priv->saveBLC_PWM_CTL = I915_READ(BLC_PWM_CTL);
dev_priv->backlight_duty_cycle = (dev_priv->saveBLC_PWM_CTL &
BACKLIGHT_DUTY_CYCLE_MASK);
@ -128,9 +128,9 @@ static void intel_lvds_restore(struct drm_output *output)
struct drm_i915_private *dev_priv = dev->dev_private;
I915_WRITE(BLC_PWM_CTL, dev_priv->saveBLC_PWM_CTL);
I915_WRITE(LVDSPP_ON, dev_priv->savePP_ON);
I915_WRITE(LVDSPP_OFF, dev_priv->savePP_OFF);
I915_WRITE(PP_CYCLE, dev_priv->savePP_CYCLE);
I915_WRITE(PP_ON_DELAYS, dev_priv->savePP_ON);
I915_WRITE(PP_OFF_DELAYS, dev_priv->savePP_OFF);
I915_WRITE(PP_DIVISOR, dev_priv->savePP_DIVISOR);
I915_WRITE(PP_CONTROL, dev_priv->savePP_CONTROL);
if (dev_priv->savePP_CONTROL & POWER_TARGET_ON)
intel_lvds_set_power(dev, true);

18
linux-core/intel_tv.c
View file

@ -1012,7 +1012,7 @@ intel_tv_restore(struct drm_output *output)
int pipeconf = I915_READ(pipeconf_reg);
int dspcntr = I915_READ(dspcntr_reg);
int dspbase_reg = (intel_crtc->plane == 0) ?
DSPABASE : DSPBBASE;
DSPAADDR : DSPBADDR;
/* Pipe must be off here */
I915_WRITE(dspcntr_reg, dspcntr & ~DISPLAY_PLANE_ENABLE);
/* Flush the plane changes */
@ -1277,7 +1277,7 @@ intel_tv_mode_set(struct drm_output *output, struct drm_display_mode *mode,
int pipeconf = I915_READ(pipeconf_reg);
int dspcntr = I915_READ(dspcntr_reg);
int dspbase_reg = (intel_crtc->plane == 0) ?
DSPABASE : DSPBBASE;
DSPAADDR : DSPBADDR;
int xpos = 0x0, ypos = 0x0;
unsigned int xsize, ysize;
/* Pipe must be off here */
@ -1368,12 +1368,12 @@ intel_tv_detect_type (struct drm_crtc *crtc, struct drm_output *output)
tv_dac = I915_READ(TV_DAC);
/* Disable TV interrupts around load detect or we'll recurse */
pipeastat = I915_READ(I915REG_PIPEASTAT);
pipeastat = I915_READ(PIPEASTAT);
pipeastat_save = pipeastat;
pipeastat &= ~I915_HOTPLUG_INTERRUPT_ENABLE;
pipeastat &= ~I915_HOTPLUG_TV_INTERRUPT_ENABLE;
I915_WRITE(I915REG_PIPEASTAT, pipeastat | I915_HOTPLUG_TV_CLEAR |
I915_HOTPLUG_CLEAR);
pipeastat &= ~PIPE_HOTPLUG_INTERRUPT_ENABLE;
pipeastat &= ~PIPE_HOTPLUG_TV_INTERRUPT_ENABLE;
I915_WRITE(PIPEASTAT, pipeastat | PIPE_HOTPLUG_TV_INTERRUPT_STATUS |
PIPE_HOTPLUG_INTERRUPT_STATUS);
/*
* Detect TV by polling)
@ -1423,8 +1423,8 @@ intel_tv_detect_type (struct drm_crtc *crtc, struct drm_output *output)
}
/* Restore interrupt config */
I915_WRITE(I915REG_PIPEASTAT, pipeastat_save | I915_HOTPLUG_TV_CLEAR |
I915_HOTPLUG_CLEAR);
I915_WRITE(PIPEASTAT, pipeastat_save | PIPE_HOTPLUG_TV_INTERRUPT_STATUS |
PIPE_HOTPLUG_INTERRUPT_STATUS);
return type;
}

14
shared-core/i915_dma.c
View file

@ -40,11 +40,11 @@ int i915_wait_ring(struct drm_device * dev, int n, const char *caller)
{
struct drm_i915_private *dev_priv = dev->dev_private;
struct drm_i915_ring_buffer *ring = &(dev_priv->ring);
u32 last_head = I915_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
u32 last_head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
int i;
for (i = 0; i < 10000; i++) {
ring->head = I915_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
ring->space = ring->head - (ring->tail + 8);
if (ring->space < 0)
ring->space += ring->Size;
@ -71,8 +71,8 @@ void i915_kernel_lost_context(struct drm_device * dev)
if (drm_core_check_feature(dev, DRIVER_MODESET))
return;
ring->head = I915_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
ring->tail = I915_READ(LP_RING + RING_TAIL) & TAIL_ADDR;
ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR;
ring->space = ring->head - (ring->tail + 8);
if (ring->space < 0)
ring->space += ring->Size;
@ -510,7 +510,7 @@ void i915_emit_breadcrumb(struct drm_device *dev)
master_priv->sarea_priv->last_enqueue = dev_priv->counter;
BEGIN_LP_RING(4);
OUT_RING(CMD_STORE_DWORD_IDX);
OUT_RING(MI_STORE_DWORD_INDEX);
OUT_RING(20);
OUT_RING(dev_priv->counter);
OUT_RING(0);
@ -521,7 +521,7 @@ void i915_emit_breadcrumb(struct drm_device *dev)
int i915_emit_mi_flush(struct drm_device *dev, uint32_t flush)
{
struct drm_i915_private *dev_priv = dev->dev_private;
uint32_t flush_cmd = CMD_MI_FLUSH;
uint32_t flush_cmd = MI_FLUSH;
RING_LOCALS;
flush_cmd |= flush;
@ -1022,7 +1022,7 @@ static int i915_set_status_page(struct drm_device *dev, void *data,
dev_priv->hw_status_page = dev_priv->hws_map.handle;
memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
I915_WRITE(I915REG_HWS_PGA, dev_priv->status_gfx_addr);
I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
DRM_DEBUG("load hws 0x2080 with gfx mem 0x%x\n",
dev_priv->status_gfx_addr);
DRM_DEBUG("load hws at %p\n", dev_priv->hw_status_page);

1517
shared-core/i915_drv.h
View file

File diff suppressed because it is too large Load diff

25
shared-core/i915_init.c
View file

@ -112,9 +112,9 @@ int i915_load_modeset_init(struct drm_device *dev)
drm_bo_init_mm(dev, DRM_BO_MEM_VRAM, 0, prealloc_size >> PAGE_SHIFT, 1);
drm_bo_init_mm(dev, DRM_BO_MEM_TT, prealloc_size >> PAGE_SHIFT,
(agp_size - prealloc_size) >> PAGE_SHIFT, 1);
I915_WRITE(LP_RING + RING_LEN, 0);
I915_WRITE(LP_RING + RING_HEAD, 0);
I915_WRITE(LP_RING + RING_TAIL, 0);
I915_WRITE(PRB0_CTL, 0);
I915_WRITE(PRB0_HEAD, 0);
I915_WRITE(PRB0_TAIL, 0);
size = PRIMARY_RINGBUFFER_SIZE;
ret = drm_buffer_object_create(dev, size, drm_bo_type_kernel,
@ -146,10 +146,9 @@ int i915_load_modeset_init(struct drm_device *dev)
dev_priv->ring.virtual_start, dev_priv->ring.Size);
memset((void *)(dev_priv->ring.virtual_start), 0, dev_priv->ring.Size);
I915_WRITE(LP_RING + RING_START, dev_priv->ring.Start);
I915_WRITE(LP_RING + RING_LEN,
((dev_priv->ring.Size - 4096) & RING_NR_PAGES) |
(RING_NO_REPORT | RING_VALID));
I915_WRITE(PRB0_START, dev_priv->ring.Start);
I915_WRITE(PRB0_CTL, ((dev_priv->ring.Size - 4096) & RING_NR_PAGES) |
(RING_NO_REPORT | RING_VALID));
/* We are using separate values as placeholders for mechanisms for
* private backbuffer/depthbuffer usage.
@ -175,7 +174,7 @@ int i915_load_modeset_init(struct drm_device *dev)
memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
I915_WRITE(I915REG_HWS_PGA, dev_priv->dma_status_page);
I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
} else {
size = 4 * 1024;
ret = drm_buffer_object_create(dev, size,
@ -210,7 +209,7 @@ int i915_load_modeset_init(struct drm_device *dev)
}
dev_priv->hw_status_page = dev_priv->hws_map.handle;
memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
I915_WRITE(I915REG_HWS_PGA, dev_priv->status_gfx_addr);
I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
}
DRM_DEBUG("Enabled hardware status page\n");
@ -261,7 +260,7 @@ destroy_hws:
if (dev_priv->hws_bo)
drm_bo_usage_deref_unlocked(&dev_priv->hws_bo);
}
I915_WRITE(I915REG_HWS_PGA, 0x1ffff000);
I915_WRITE(HWS_PGA, 0x1ffff000);
destroy_ringbuffer:
if (dev_priv->ring.virtual_start)
drm_mem_reg_iounmap(dev, &dev_priv->ring_buffer->mem,
@ -381,7 +380,7 @@ int i915_driver_unload(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
I915_WRITE(LP_RING + RING_LEN, 0);
I915_WRITE(PRB0_CTL, 0);
if (drm_core_check_feature(dev, DRIVER_MODESET)) {
drm_irq_uninstall(dev);
@ -413,14 +412,14 @@ int i915_driver_unload(struct drm_device *dev)
dev_priv->hw_status_page = NULL;
dev_priv->dma_status_page = 0;
/* Need to rewrite hardware status page */
I915_WRITE(I915REG_HWS_PGA, 0x1ffff000);
I915_WRITE(HWS_PGA, 0x1ffff000);
}
if (dev_priv->status_gfx_addr) {
dev_priv->status_gfx_addr = 0;
drm_core_ioremapfree(&dev_priv->hws_map, dev);
drm_bo_usage_deref_unlocked(&dev_priv->hws_bo);
I915_WRITE(I915REG_HWS_PGA, 0x1ffff000);
I915_WRITE(HWS_PGA, 0x1ffff000);
}
if (drm_core_check_feature(dev, DRIVER_MODESET)) {

160
shared-core/i915_irq.c
View file

@ -636,9 +636,9 @@ irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
/* On i8xx/i915 hw the IIR and IER are 16bit on i9xx its 32bit */
if (IS_I9XX(dev) && !IS_I915G(dev) && !IS_I915GM(dev))
iir = I915_READ(I915REG_INT_IDENTITY_R);
iir = I915_READ(IIR);
else
iir = I915_READ16(I915REG_INT_IDENTITY_R);
iir = I915_READ16(IIR);
iir &= (dev_priv->irq_enable_reg | I915_USER_INTERRUPT);
@ -649,10 +649,10 @@ irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
#if 0
DRM_DEBUG ("iir 0x%08x im 0x%08x ie 0x%08x pipea 0x%08x pipeb 0x%08x\n",
iir,
I915_READ(I915REG_INT_MASK_R),
I915_READ(I915REG_INT_ENABLE_R),
I915_READ(I915REG_PIPEASTAT),
I915_READ(I915REG_PIPEBSTAT));
I915_READ(IMR),
I915_READ(IER),
I915_READ(PIPEASTAT),
I915_READ(PIPEBSTAT));
#endif
return IRQ_NONE;
}
@ -662,19 +662,19 @@ irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
* we may get extra interrupts.
*/
if (iir & I915_DISPLAY_PIPE_A_EVENT_INTERRUPT) {
pipea_stats = I915_READ(I915REG_PIPEASTAT);
if (pipea_stats & (I915_START_VBLANK_INTERRUPT_STATUS|
I915_VBLANK_INTERRUPT_STATUS))
pipea_stats = I915_READ(PIPEASTAT);
if (pipea_stats & (PIPE_START_VBLANK_INTERRUPT_STATUS|
PIPE_VBLANK_INTERRUPT_STATUS))
{
vblank++;
drm_handle_vblank(dev, i915_get_plane(dev, 0));
}
/* This is a global event, and not a pipe A event */
if (pipea_stats & I915_HOTPLUG_INTERRUPT_STATUS)
if (pipea_stats & PIPE_HOTPLUG_INTERRUPT_STATUS)
hotplug = 1;
if (pipea_stats & I915_HOTPLUG_TV_INTERRUPT_STATUS) {
if (pipea_stats & PIPE_HOTPLUG_TV_INTERRUPT_STATUS) {
hotplug = 1;
/* Toggle hotplug detection to clear hotplug status */
tvdac = I915_READ(TV_DAC);
@ -682,27 +682,27 @@ irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
I915_WRITE(TV_DAC, tvdac | TVDAC_STATE_CHG_EN);
}
I915_WRITE(I915REG_PIPEASTAT, pipea_stats);
I915_WRITE(PIPEASTAT, pipea_stats);
}
if (iir & I915_DISPLAY_PIPE_B_EVENT_INTERRUPT) {
pipeb_stats = I915_READ(I915REG_PIPEBSTAT);
if (pipeb_stats & (I915_START_VBLANK_INTERRUPT_STATUS|
I915_VBLANK_INTERRUPT_STATUS))
pipeb_stats = I915_READ(PIPEBSTAT);
if (pipeb_stats & (PIPE_START_VBLANK_INTERRUPT_STATUS|
PIPE_VBLANK_INTERRUPT_STATUS))
{
vblank++;
drm_handle_vblank(dev, i915_get_plane(dev, 1));
}
I915_WRITE(I915REG_PIPEBSTAT, pipeb_stats);
I915_WRITE(PIPEBSTAT, pipeb_stats);
}
/* Clear the generated interrupt */
if (IS_I9XX(dev) && !IS_I915G(dev) && !IS_I915GM(dev)) {
I915_WRITE(I915REG_INT_IDENTITY_R, iir);
(void) I915_READ(I915REG_INT_IDENTITY_R);
I915_WRITE(IIR, iir);
(void) I915_READ(IIR);
} else {
I915_WRITE16(I915REG_INT_IDENTITY_R, iir);
(void) I915_READ16(I915REG_INT_IDENTITY_R);
I915_WRITE16(IIR, iir);
(void) I915_READ16(IIR);
}
if (dev->primary->master) {
@ -728,10 +728,10 @@ irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
DRM_INFO("Hotplug event received\n");
if (!IS_I9XX(dev) || IS_I915G(dev) || IS_I915GM(dev)) {
if (pipea_stats & I915_HOTPLUG_INTERRUPT_STATUS)
if (pipea_stats & PIPE_HOTPLUG_INTERRUPT_STATUS)
temp2 |= SDVOB_HOTPLUG_INT_STATUS |
SDVOC_HOTPLUG_INT_STATUS;
if (pipea_stats & I915_HOTPLUG_TV_INTERRUPT_STATUS)
if (pipea_stats & PIPE_HOTPLUG_TV_INTERRUPT_STATUS)
temp2 |= TV_HOTPLUG_INT_STATUS;
} else {
temp2 = I915_READ(PORT_HOTPLUG_STAT);
@ -757,7 +757,7 @@ int i915_emit_irq(struct drm_device *dev)
BEGIN_LP_RING(2);
OUT_RING(0);
OUT_RING(GFX_OP_USER_INTERRUPT);
OUT_RING(MI_USER_INTERRUPT);
ADVANCE_LP_RING();
return dev_priv->counter;
@ -771,9 +771,9 @@ void i915_user_irq_on(struct drm_device *dev)
if (dev_priv->irq_enabled && (++dev_priv->user_irq_refcount == 1)){
dev_priv->irq_enable_reg |= I915_USER_INTERRUPT;
if (IS_I9XX(dev) && !IS_I915G(dev) && !IS_I915GM(dev))
I915_WRITE(I915REG_INT_ENABLE_R, dev_priv->irq_enable_reg);
I915_WRITE(IER, dev_priv->irq_enable_reg);
else
I915_WRITE16(I915REG_INT_ENABLE_R, dev_priv->irq_enable_reg);
I915_WRITE16(IER, dev_priv->irq_enable_reg);
}
DRM_SPINUNLOCK(&dev_priv->user_irq_lock);
@ -787,9 +787,9 @@ void i915_user_irq_off(struct drm_device *dev)
if (dev_priv->irq_enabled && (--dev_priv->user_irq_refcount == 0)) {
// dev_priv->irq_enable_reg &= ~I915_USER_INTERRUPT;
// if (IS_I9XX(dev) && !IS_I915G(dev) && !IS_I915GM(dev))
// I915_WRITE(I915REG_INT_ENABLE_R, dev_priv->irq_enable_reg);
// I915_WRITE(IER, dev_priv->irq_enable_reg);
// else
// I915_WRITE16(I915REG_INT_ENABLE_R, dev_priv->irq_enable_reg);
// I915_WRITE16(IER, dev_priv->irq_enable_reg);
}
DRM_SPINUNLOCK(&dev_priv->user_irq_lock);
}
@ -876,11 +876,11 @@ int i915_enable_vblank(struct drm_device *dev, int plane)
switch (pipe) {
case 0:
pipestat_reg = I915REG_PIPEASTAT;
pipestat_reg = PIPEASTAT;
dev_priv->irq_enable_reg |= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
break;
case 1:
pipestat_reg = I915REG_PIPEBSTAT;
pipestat_reg = PIPEBSTAT;
dev_priv->irq_enable_reg |= I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
break;
default:
@ -897,21 +897,21 @@ int i915_enable_vblank(struct drm_device *dev, int plane)
* but
*/
if (IS_I965G (dev))
pipestat |= I915_START_VBLANK_INTERRUPT_ENABLE;
pipestat |= PIPE_START_VBLANK_INTERRUPT_ENABLE;
else
pipestat |= I915_VBLANK_INTERRUPT_ENABLE;
pipestat |= PIPE_VBLANK_INTERRUPT_ENABLE;
/*
* Clear any pending status
*/
pipestat |= (I915_START_VBLANK_INTERRUPT_STATUS |
I915_VBLANK_INTERRUPT_STATUS);
pipestat |= (PIPE_START_VBLANK_INTERRUPT_STATUS |
PIPE_VBLANK_INTERRUPT_STATUS);
I915_WRITE(pipestat_reg, pipestat);
}
if (IS_I9XX(dev) && !IS_I915G(dev) && !IS_I915GM(dev))
I915_WRITE(I915REG_INT_ENABLE_R, dev_priv->irq_enable_reg);
I915_WRITE(IER, dev_priv->irq_enable_reg);
else
I915_WRITE16(I915REG_INT_ENABLE_R, dev_priv->irq_enable_reg);
I915_WRITE16(IER, dev_priv->irq_enable_reg);
return 0;
@ -926,11 +926,11 @@ void i915_disable_vblank(struct drm_device *dev, int plane)
switch (pipe) {
case 0:
pipestat_reg = I915REG_PIPEASTAT;
pipestat_reg = PIPEASTAT;
dev_priv->irq_enable_reg &= ~I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
break;
case 1:
pipestat_reg = I915REG_PIPEBSTAT;
pipestat_reg = PIPEBSTAT;
dev_priv->irq_enable_reg &= ~I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
break;
default:
@ -940,20 +940,20 @@ void i915_disable_vblank(struct drm_device *dev, int plane)
}
if (IS_I9XX(dev) && !IS_I915G(dev) && !IS_I915GM(dev))
I915_WRITE(I915REG_INT_ENABLE_R, dev_priv->irq_enable_reg);
I915_WRITE(IER, dev_priv->irq_enable_reg);
else
I915_WRITE16(I915REG_INT_ENABLE_R, dev_priv->irq_enable_reg);
I915_WRITE16(IER, dev_priv->irq_enable_reg);
if (pipestat_reg)
{
pipestat = I915_READ (pipestat_reg);
pipestat &= ~(I915_START_VBLANK_INTERRUPT_ENABLE |
I915_VBLANK_INTERRUPT_ENABLE);
pipestat &= ~(PIPE_START_VBLANK_INTERRUPT_ENABLE |
PIPE_VBLANK_INTERRUPT_ENABLE);
/*
* Clear any pending status
*/
pipestat |= (I915_START_VBLANK_INTERRUPT_STATUS |
I915_VBLANK_INTERRUPT_STATUS);
pipestat |= (PIPE_START_VBLANK_INTERRUPT_STATUS |
PIPE_VBLANK_INTERRUPT_STATUS);
I915_WRITE(pipestat_reg, pipestat);
}
}
@ -973,11 +973,11 @@ void i915_enable_interrupt (struct drm_device *dev)
dev_priv->irq_enable_reg |= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
/* Enable global interrupts for hotplug - not a pipeA event */
I915_WRITE(I915REG_PIPEASTAT, I915_READ(I915REG_PIPEASTAT) |
I915_HOTPLUG_INTERRUPT_ENABLE |
I915_HOTPLUG_TV_INTERRUPT_ENABLE |
I915_HOTPLUG_TV_CLEAR |
I915_HOTPLUG_CLEAR);
I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) |
PIPE_HOTPLUG_INTERRUPT_ENABLE |
PIPE_HOTPLUG_TV_INTERRUPT_ENABLE |
PIPE_HOTPLUG_TV_INTERRUPT_STATUS |
PIPE_HOTPLUG_INTERRUPT_STATUS);
}
if (dev_priv->irq_enable_reg & (I915_DISPLAY_PORT_INTERRUPT | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT)) {
@ -1025,9 +1025,9 @@ void i915_enable_interrupt (struct drm_device *dev)
}
if (IS_I9XX(dev) && !IS_I915G(dev) && !IS_I915GM(dev))
I915_WRITE(I915REG_INT_ENABLE_R, dev_priv->irq_enable_reg);
I915_WRITE(IER, dev_priv->irq_enable_reg);
else
I915_WRITE16(I915REG_INT_ENABLE_R, dev_priv->irq_enable_reg);
I915_WRITE16(IER, dev_priv->irq_enable_reg);
dev_priv->irq_enabled = 1;
}
@ -1068,9 +1068,9 @@ int i915_vblank_pipe_get(struct drm_device *dev, void *data,
}
if (IS_I9XX(dev) && !IS_I915G(dev) && !IS_I915GM(dev))
flag = I915_READ(I915REG_INT_ENABLE_R);
flag = I915_READ(IER);
else
flag = I915_READ16(I915REG_INT_ENABLE_R);
flag = I915_READ16(IER);
pipe->pipe = 0;
if (flag & I915_DISPLAY_PIPE_A_EVENT_INTERRUPT)
@ -1249,23 +1249,23 @@ void i915_driver_irq_preinstall(struct drm_device * dev)
struct drm_i915_private *dev_priv = (struct drm_i915_private *) dev->dev_private;
u32 tmp;
tmp = I915_READ(I915REG_PIPEASTAT);
I915_WRITE(I915REG_PIPEASTAT, tmp);
tmp = I915_READ(I915REG_PIPEBSTAT);
I915_WRITE(I915REG_PIPEBSTAT, tmp);
tmp = I915_READ(PIPEASTAT);
I915_WRITE(PIPEASTAT, tmp);
tmp = I915_READ(PIPEBSTAT);
I915_WRITE(PIPEBSTAT, tmp);
I915_WRITE16(I915REG_HWSTAM, 0xeffe);
I915_WRITE16(HWSTAM, 0xeffe);
if (IS_I9XX(dev) && !IS_I915G(dev) && !IS_I915GM(dev)) {
I915_WRITE(I915REG_INT_MASK_R, 0x0);
I915_WRITE(I915REG_INT_ENABLE_R, 0x0);
tmp = I915_READ(I915REG_INT_IDENTITY_R);
I915_WRITE(I915REG_INT_IDENTITY_R, tmp);
I915_WRITE(IMR, 0x0);
I915_WRITE(IER, 0x0);
tmp = I915_READ(IIR);
I915_WRITE(IIR, tmp);
} else {
I915_WRITE16(I915REG_INT_MASK_R, 0x0);
I915_WRITE16(I915REG_INT_ENABLE_R, 0x0);
tmp = I915_READ16(I915REG_INT_IDENTITY_R);
I915_WRITE16(I915REG_INT_IDENTITY_R, tmp);
I915_WRITE16(IMR, 0x0);
I915_WRITE16(IER, 0x0);
tmp = I915_READ16(IIR);
I915_WRITE16(IIR, tmp);
}
}
@ -1300,7 +1300,7 @@ int i915_driver_irq_postinstall(struct drm_device * dev)
* Initialize the hardware status page IRQ location.
*/
I915_WRITE(I915REG_INSTPM, (1 << 5) | (1 << 21));
I915_WRITE(INSTPM, (1 << 5) | (1 << 21));
return 0;
}
@ -1314,23 +1314,23 @@ void i915_driver_irq_uninstall(struct drm_device * dev)
dev_priv->irq_enabled = 0;
temp = I915_READ(I915REG_PIPEASTAT);
I915_WRITE(I915REG_PIPEASTAT, temp);
temp = I915_READ(I915REG_PIPEBSTAT);
I915_WRITE(I915REG_PIPEBSTAT, temp);
temp = I915_READ(PIPEASTAT);
I915_WRITE(PIPEASTAT, temp);
temp = I915_READ(PIPEBSTAT);
I915_WRITE(PIPEBSTAT, temp);
if (IS_I9XX(dev) && !IS_I915G(dev) && !IS_I915GM(dev)) {
I915_WRITE(I915REG_HWSTAM, 0xffffffff);
I915_WRITE(I915REG_INT_MASK_R, 0xffffffff);
I915_WRITE(I915REG_INT_ENABLE_R, 0x0);
I915_WRITE(HWSTAM, 0xffffffff);
I915_WRITE(IMR, 0xffffffff);
I915_WRITE(IER, 0x0);
temp = I915_READ(I915REG_INT_IDENTITY_R);
I915_WRITE(I915REG_INT_IDENTITY_R, temp);
temp = I915_READ(IIR);
I915_WRITE(IIR, temp);
} else {
I915_WRITE16(I915REG_HWSTAM, 0xffff);
I915_WRITE16(I915REG_INT_MASK_R, 0xffff);
I915_WRITE16(I915REG_INT_ENABLE_R, 0x0);
I915_WRITE16(HWSTAM, 0xffff);
I915_WRITE16(IMR, 0xffff);
I915_WRITE16(IER, 0x0);
temp = I915_READ16(I915REG_INT_IDENTITY_R);
I915_WRITE16(I915REG_INT_IDENTITY_R, temp);
temp = I915_READ16(IIR);
I915_WRITE16(IIR, temp);
}
}