mirror of
https://gitlab.freedesktop.org/mesa/drm.git
synced 2025-12-24 23:00:11 +01:00
i915: This was part of a sync to the intel driver at some point
-Remove the old TTM interface -Move register definitions to i915_reg.h -Rework the irq handler
This commit is contained in:
Robert Noland
parent
c3c21303e3
commit
d45bc6667c
7 changed files with 1925 additions and 2294 deletions
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@ -658,6 +658,7 @@ struct drm_device {
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/* Context support */
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int irq; /* Interrupt used by board */
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int irq_enabled; /* True if the irq handler is enabled */
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int msi_enabled; /* MSI enabled */
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int irqrid; /* Interrupt used by board */
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struct resource *irqr; /* Resource for interrupt used by board */
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void *irqh; /* Handle from bus_setup_intr */
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@ -75,7 +75,6 @@ static void i915_configure(struct drm_device *dev)
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dev->driver->buf_priv_size = sizeof(drm_i915_private_t);
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dev->driver->load = i915_driver_load;
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dev->driver->unload = i915_driver_unload;
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dev->driver->firstopen = i915_driver_firstopen;
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dev->driver->preclose = i915_driver_preclose;
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dev->driver->lastclose = i915_driver_lastclose;
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dev->driver->device_is_agp = i915_driver_device_is_agp;
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1
bsd-core/i915_reg.h
Symbolic link
1
bsd-core/i915_reg.h
Symbolic link
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@ -0,0 +1 @@
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../shared-core/i915_reg.h
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File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
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@ -33,16 +33,29 @@
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#define MAX_NOPID ((u32)~0)
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/*
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* These are the interrupts used by the driver
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/**
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* Interrupts that are always left unmasked.
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*
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* Since pipe events are edge-triggered from the PIPESTAT register to IIR,
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* we leave them always unmasked in IMR and then control enabling them through
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* PIPESTAT alone.
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*/
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#define I915_INTERRUPT_ENABLE_MASK (I915_USER_INTERRUPT | \
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I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | \
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I915_DISPLAY_PIPE_B_EVENT_INTERRUPT)
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#define I915_INTERRUPT_ENABLE_FIX (I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | \
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I915_DISPLAY_PIPE_B_EVENT_INTERRUPT)
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/** Interrupts that we mask and unmask at runtime. */
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#define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT)
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/** These are all of the interrupts used by the driver */
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#define I915_INTERRUPT_ENABLE_MASK (I915_INTERRUPT_ENABLE_FIX | \
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I915_INTERRUPT_ENABLE_VAR)
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static inline void
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i915_enable_irq(drm_i915_private_t *dev_priv, uint32_t mask)
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i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask)
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{
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DRM_DEBUG("irq_enable_reg = 0x%08x, mask = 0x%08x\n",
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dev_priv->irq_mask_reg, mask);
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mask &= I915_INTERRUPT_ENABLE_VAR;
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if ((dev_priv->irq_mask_reg & mask) != 0) {
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dev_priv->irq_mask_reg &= ~mask;
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I915_WRITE(IMR, dev_priv->irq_mask_reg);
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@ -51,8 +64,9 @@ i915_enable_irq(drm_i915_private_t *dev_priv, uint32_t mask)
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}
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static inline void
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i915_disable_irq(drm_i915_private_t *dev_priv, uint32_t mask)
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i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask)
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{
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mask &= I915_INTERRUPT_ENABLE_VAR;
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if ((dev_priv->irq_mask_reg & mask) != mask) {
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dev_priv->irq_mask_reg |= mask;
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I915_WRITE(IMR, dev_priv->irq_mask_reg);
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@ -60,43 +74,41 @@ i915_disable_irq(drm_i915_private_t *dev_priv, uint32_t mask)
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}
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}
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/**
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* i915_get_pipe - return the the pipe associated with a given plane
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* @dev: DRM device
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* @plane: plane to look for
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*
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* The Intel Mesa & 2D drivers call the vblank routines with a plane number
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* rather than a pipe number, since they may not always be equal. This routine
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* maps the given @plane back to a pipe number.
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*/
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static int
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i915_get_pipe(struct drm_device *dev, int plane)
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static inline u32
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i915_pipestat(int pipe)
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{
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drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
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u32 dspcntr;
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dspcntr = plane ? I915_READ(DSPBCNTR) : I915_READ(DSPACNTR);
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return dspcntr & DISPPLANE_SEL_PIPE_MASK ? 1 : 0;
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if (pipe == 0)
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return PIPEASTAT;
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if (pipe == 1)
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return PIPEBSTAT;
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return -EINVAL;
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}
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/**
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* i915_get_plane - return the the plane associated with a given pipe
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* @dev: DRM device
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* @pipe: pipe to look for
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*
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* The Intel Mesa & 2D drivers call the vblank routines with a plane number
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* rather than a plane number, since they may not always be equal. This routine
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* maps the given @pipe back to a plane number.
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*/
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static int
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i915_get_plane(struct drm_device *dev, int pipe)
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void
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i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
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{
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if (i915_get_pipe(dev, 0) == pipe)
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return 0;
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return 1;
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if ((dev_priv->pipestat[pipe] & mask) != mask) {
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u32 reg = i915_pipestat(pipe);
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dev_priv->pipestat[pipe] |= mask;
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/* Enable the interrupt, clear any pending status */
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I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
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(void) I915_READ(reg);
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}
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}
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void
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i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
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{
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if ((dev_priv->pipestat[pipe] & mask) != 0) {
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u32 reg = i915_pipestat(pipe);
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dev_priv->pipestat[pipe] &= ~mask;
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I915_WRITE(reg, dev_priv->pipestat[pipe]);
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(void) I915_READ(reg);
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}
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}
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/**
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* i915_pipe_enabled - check if a pipe is enabled
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* @dev: DRM device
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@ -118,21 +130,22 @@ i915_pipe_enabled(struct drm_device *dev, int pipe)
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return 0;
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}
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u32 i915_get_vblank_counter(struct drm_device *dev, int plane)
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/* Called from drm generic code, passed a 'crtc', which
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* we use as a pipe index
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*/
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u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
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{
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drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
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unsigned long high_frame;
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unsigned long low_frame;
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u32 high1, high2, low, count;
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int pipe;
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pipe = i915_get_pipe(dev, plane);
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high_frame = pipe ? PIPEBFRAMEHIGH : PIPEAFRAMEHIGH;
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low_frame = pipe ? PIPEBFRAMEPIXEL : PIPEAFRAMEPIXEL;
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if (!i915_pipe_enabled(dev, pipe)) {
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DRM_DEBUG("trying to get vblank count for disabled pipe %d\n", pipe);
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return 0;
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DRM_ERROR("trying to get vblank count for disabled pipe %d\n", pipe);
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return 0;
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}
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/*
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@ -158,104 +171,65 @@ irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
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{
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struct drm_device *dev = (struct drm_device *) arg;
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drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
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u32 iir;
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u32 pipea_stats = 0, pipeb_stats = 0;
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int vblank = 0;
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#ifdef __linux__
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if (dev->pdev->msi_enabled)
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I915_WRITE(IMR, ~0);
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#endif
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iir = I915_READ(IIR);
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#if 0
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DRM_DEBUG("flag=%08x\n", iir);
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#endif
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u32 iir, new_iir;
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u32 pipea_stats, pipeb_stats;
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atomic_inc(&dev_priv->irq_received);
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if (iir == 0) {
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#ifdef __linux__
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if (dev->pdev->msi_enabled) {
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I915_WRITE(IMR, dev_priv->irq_mask_reg);
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(void) I915_READ(IMR);
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for (iir = I915_READ(IIR) ; iir != 0 ; iir = new_iir) {
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pipea_stats = pipeb_stats = 0;
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/*
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* Clear the PIPE(A|B)STAT regs before the IIR
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*/
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if (iir & I915_DISPLAY_PIPE_A_EVENT_INTERRUPT) {
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DRM_SPINLOCK(&dev_priv->user_irq_lock);
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pipea_stats = I915_READ(PIPEASTAT);
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I915_WRITE(PIPEASTAT, pipea_stats);
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DRM_SPINUNLOCK(&dev_priv->user_irq_lock);
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}
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if (iir & I915_DISPLAY_PIPE_B_EVENT_INTERRUPT) {
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DRM_SPINLOCK(&dev_priv->user_irq_lock);
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pipeb_stats = I915_READ(PIPEBSTAT);
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I915_WRITE(PIPEBSTAT, pipeb_stats);
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DRM_SPINUNLOCK(&dev_priv->user_irq_lock);
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}
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I915_WRITE(IIR, iir);
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new_iir = I915_READ(IIR);
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DRM_DEBUG("iir = 0x%08x, pipestats a = 0x%08x, b = 0x%08x\n",
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iir, pipea_stats, pipeb_stats);
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if (dev_priv->sarea_priv)
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dev_priv->sarea_priv->last_dispatch =
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READ_BREADCRUMB(dev_priv);
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if (iir & I915_USER_INTERRUPT) {
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#ifdef I915_HAVE_GEM
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dev_priv->mm.irq_gem_seqno = i915_get_gem_seqno(dev);
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#endif
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return IRQ_NONE;
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}
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/*
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* Clear the PIPE(A|B)STAT regs before the IIR otherwise
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* we may get extra interrupts.
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*/
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if (iir & I915_DISPLAY_PIPE_A_EVENT_INTERRUPT) {
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pipea_stats = I915_READ(PIPEASTAT);
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/* The vblank interrupt gets enabled even if we didn't ask for
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it, so make sure it's shut down again */
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if (!(dev_priv->vblank_pipe & DRM_I915_VBLANK_PIPE_A))
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pipea_stats &= ~(PIPE_START_VBLANK_INTERRUPT_ENABLE |
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PIPE_VBLANK_INTERRUPT_ENABLE);
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else if (pipea_stats & (PIPE_START_VBLANK_INTERRUPT_STATUS|
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PIPE_VBLANK_INTERRUPT_STATUS))
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{
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vblank++;
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drm_handle_vblank(dev, i915_get_plane(dev, 0));
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DRM_WAKEUP(&dev_priv->irq_queue);
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}
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I915_WRITE(PIPEASTAT, pipea_stats);
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}
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if (iir & I915_DISPLAY_PIPE_B_EVENT_INTERRUPT) {
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pipeb_stats = I915_READ(PIPEBSTAT);
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/* The vblank interrupt gets enabled even if we didn't ask for
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it, so make sure it's shut down again */
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if (!(dev_priv->vblank_pipe & DRM_I915_VBLANK_PIPE_B))
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pipeb_stats &= ~(PIPE_START_VBLANK_INTERRUPT_ENABLE |
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PIPE_VBLANK_INTERRUPT_ENABLE);
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else if (pipeb_stats & (PIPE_START_VBLANK_INTERRUPT_STATUS|
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PIPE_VBLANK_INTERRUPT_STATUS))
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{
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vblank++;
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drm_handle_vblank(dev, i915_get_plane(dev, 1));
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}
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if (pipea_stats & (PIPE_START_VBLANK_INTERRUPT_STATUS |
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PIPE_VBLANK_INTERRUPT_STATUS))
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drm_handle_vblank(dev, 0);
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if (pipeb_stats & (PIPE_START_VBLANK_INTERRUPT_STATUS |
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PIPE_VBLANK_INTERRUPT_STATUS))
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drm_handle_vblank(dev, 1);
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#ifdef __linux__
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#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,25)
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if (pipeb_stats & I915_LEGACY_BLC_EVENT_ENABLE)
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if ((pipeb_stats & I915_LEGACY_BLC_EVENT_STATUS) ||
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(iir & I915_ASLE_INTERRUPT))
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opregion_asle_intr(dev);
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#endif
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#endif
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I915_WRITE(PIPEBSTAT, pipeb_stats);
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}
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#ifdef __linux__
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#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,25)
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if (iir & I915_ASLE_INTERRUPT)
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opregion_asle_intr(dev);
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#endif
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#endif
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if (dev_priv->sarea_priv)
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dev_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
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I915_WRITE(IIR, iir);
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#ifdef __linux__
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if (dev->pdev->msi_enabled)
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I915_WRITE(IMR, dev_priv->irq_mask_reg);
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#endif
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(void) I915_READ(IIR); /* Flush posted writes */
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if (iir & I915_USER_INTERRUPT) {
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#ifdef I915_HAVE_GEM
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dev_priv->mm.irq_gem_seqno = i915_get_gem_seqno(dev);
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#endif
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DRM_WAKEUP(&dev_priv->irq_queue);
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#ifdef I915_HAVE_FENCE
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i915_fence_handler(dev);
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#endif
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}
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return IRQ_HANDLED;
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}
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int i915_emit_irq(struct drm_device *dev)
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static int i915_emit_irq(struct drm_device * dev)
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{
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drm_i915_private_t *dev_priv = dev->dev_private;
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RING_LOCALS;
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@ -264,60 +238,71 @@ int i915_emit_irq(struct drm_device *dev)
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DRM_DEBUG("\n");
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i915_emit_breadcrumb(dev);
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dev_priv->counter++;
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if (dev_priv->counter > 0x7FFFFFFFUL)
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dev_priv->counter = 1;
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if (dev_priv->sarea_priv)
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dev_priv->sarea_priv->last_enqueue = dev_priv->counter;
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BEGIN_LP_RING(2);
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OUT_RING(0);
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BEGIN_LP_RING(4);
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OUT_RING(MI_STORE_DWORD_INDEX);
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OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
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OUT_RING(dev_priv->counter);
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OUT_RING(MI_USER_INTERRUPT);
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ADVANCE_LP_RING();
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return dev_priv->counter;
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}
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void i915_user_irq_on(drm_i915_private_t *dev_priv)
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void i915_user_irq_get(struct drm_device *dev)
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{
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DRM_SPINLOCK(&dev_priv->user_irq_lock);
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if (dev_priv->irq_enabled && (++dev_priv->user_irq_refcount == 1))
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drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
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unsigned long irqflags;
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DRM_DEBUG("\n");
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DRM_SPINLOCK_IRQSAVE(&dev_priv->user_irq_lock, irqflags);
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if (dev->irq_enabled && (++dev_priv->user_irq_refcount == 1))
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i915_enable_irq(dev_priv, I915_USER_INTERRUPT);
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DRM_SPINUNLOCK(&dev_priv->user_irq_lock);
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DRM_SPINUNLOCK_IRQRESTORE(&dev_priv->user_irq_lock, irqflags);
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}
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void i915_user_irq_off(drm_i915_private_t *dev_priv)
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void i915_user_irq_put(struct drm_device *dev)
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{
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DRM_SPINLOCK(&dev_priv->user_irq_lock);
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drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
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unsigned long irqflags;
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DRM_SPINLOCK_IRQSAVE(&dev_priv->user_irq_lock, irqflags);
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#ifdef __linux__
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BUG_ON(dev_priv->irq_enabled && dev_priv->user_irq_refcount <= 0);
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BUG_ON(dev->irq_enabled && dev_priv->user_irq_refcount <= 0);
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#endif
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if (dev_priv->irq_enabled && (--dev_priv->user_irq_refcount == 0))
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if (dev->irq_enabled && (--dev_priv->user_irq_refcount == 0))
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i915_disable_irq(dev_priv, I915_USER_INTERRUPT);
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DRM_SPINUNLOCK(&dev_priv->user_irq_lock);
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DRM_SPINUNLOCK_IRQRESTORE(&dev_priv->user_irq_lock, irqflags);
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}
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int i915_wait_irq(struct drm_device * dev, int irq_nr)
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static int i915_wait_irq(struct drm_device * dev, int irq_nr)
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{
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drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
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int ret = 0;
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if (!dev_priv) {
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DRM_ERROR("called with no initialization\n");
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return -EINVAL;
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}
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DRM_DEBUG("irq_nr=%d breadcrumb=%d\n", irq_nr,
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READ_BREADCRUMB(dev_priv));
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if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
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if (dev_priv->sarea_priv)
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if (dev_priv->sarea_priv) {
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dev_priv->sarea_priv->last_dispatch =
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READ_BREADCRUMB(dev_priv);
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}
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return 0;
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}
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i915_user_irq_on(dev_priv);
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if (dev_priv->sarea_priv)
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dev_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
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i915_user_irq_get(dev);
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DRM_WAIT_ON(ret, dev_priv->irq_queue, 3 * DRM_HZ,
|
||||
READ_BREADCRUMB(dev_priv) >= irq_nr);
|
||||
i915_user_irq_off(dev_priv);
|
||||
i915_user_irq_put(dev);
|
||||
|
||||
if (ret == -EBUSY) {
|
||||
DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
|
||||
|
|
@ -327,6 +312,7 @@ int i915_wait_irq(struct drm_device * dev, int irq_nr)
|
|||
if (dev_priv->sarea_priv)
|
||||
dev_priv->sarea_priv->last_dispatch =
|
||||
READ_BREADCRUMB(dev_priv);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
|
@ -339,7 +325,7 @@ int i915_irq_emit(struct drm_device *dev, void *data,
|
|||
drm_i915_irq_emit_t *emit = data;
|
||||
int result;
|
||||
|
||||
LOCK_TEST_WITH_RETURN(dev, file_priv);
|
||||
RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
|
||||
|
||||
if (!dev_priv) {
|
||||
DRM_ERROR("called with no initialization\n");
|
||||
|
|
@ -359,7 +345,7 @@ int i915_irq_emit(struct drm_device *dev, void *data,
|
|||
/* Doesn't need the hardware lock.
|
||||
*/
|
||||
int i915_irq_wait(struct drm_device *dev, void *data,
|
||||
struct drm_file *file_priv)
|
||||
struct drm_file *file_priv)
|
||||
{
|
||||
drm_i915_private_t *dev_priv = dev->dev_private;
|
||||
drm_i915_irq_wait_t *irqwait = data;
|
||||
|
|
@ -372,112 +358,42 @@ int i915_irq_wait(struct drm_device *dev, void *data,
|
|||
return i915_wait_irq(dev, irqwait->irq_seq);
|
||||
}
|
||||
|
||||
int i915_enable_vblank(struct drm_device *dev, int plane)
|
||||
/* Called from drm generic code, passed 'crtc' which
|
||||
* we use as a pipe index
|
||||
*/
|
||||
int i915_enable_vblank(struct drm_device *dev, int pipe)
|
||||
{
|
||||
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
|
||||
int pipe = i915_get_pipe(dev, plane);
|
||||
u32 pipestat_reg = 0;
|
||||
u32 mask_reg = 0;
|
||||
u32 pipestat;
|
||||
unsigned long irqflags;
|
||||
u32 pipestat;
|
||||
|
||||
switch (pipe) {
|
||||
case 0:
|
||||
pipestat_reg = PIPEASTAT;
|
||||
mask_reg |= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
|
||||
break;
|
||||
case 1:
|
||||
pipestat_reg = PIPEBSTAT;
|
||||
mask_reg |= I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
|
||||
break;
|
||||
default:
|
||||
DRM_ERROR("tried to enable vblank on non-existent pipe %d\n",
|
||||
pipe);
|
||||
break;
|
||||
}
|
||||
|
||||
if (pipestat_reg)
|
||||
{
|
||||
pipestat = I915_READ (pipestat_reg);
|
||||
/*
|
||||
* Older chips didn't have the start vblank interrupt,
|
||||
* but
|
||||
*/
|
||||
if (IS_I965G (dev))
|
||||
pipestat |= PIPE_START_VBLANK_INTERRUPT_ENABLE;
|
||||
else
|
||||
pipestat |= PIPE_VBLANK_INTERRUPT_ENABLE;
|
||||
/*
|
||||
* Clear any pending status
|
||||
*/
|
||||
pipestat |= (PIPE_START_VBLANK_INTERRUPT_STATUS |
|
||||
PIPE_VBLANK_INTERRUPT_STATUS);
|
||||
I915_WRITE(pipestat_reg, pipestat);
|
||||
}
|
||||
DRM_SPINLOCK(&dev_priv->user_irq_lock);
|
||||
i915_enable_irq(dev_priv, mask_reg);
|
||||
DRM_SPINUNLOCK(&dev_priv->user_irq_lock);
|
||||
/*
|
||||
* Older chips didn't have the start vblank interrupt,
|
||||
* but
|
||||
*/
|
||||
if (IS_I965G (dev))
|
||||
pipestat = PIPE_START_VBLANK_INTERRUPT_ENABLE;
|
||||
else
|
||||
pipestat = PIPE_VBLANK_INTERRUPT_ENABLE;
|
||||
|
||||
DRM_SPINLOCK_IRQSAVE(&dev_priv->user_irq_lock, irqflags);
|
||||
i915_enable_pipestat(dev_priv, pipe, pipestat);
|
||||
DRM_SPINUNLOCK_IRQRESTORE(&dev_priv->user_irq_lock, irqflags);
|
||||
return 0;
|
||||
}
|
||||
|
||||
void i915_disable_vblank(struct drm_device *dev, int plane)
|
||||
/* Called from drm generic code, passed 'crtc' which
|
||||
* we use as a pipe index
|
||||
*/
|
||||
void i915_disable_vblank(struct drm_device *dev, int pipe)
|
||||
{
|
||||
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
|
||||
int pipe = i915_get_pipe(dev, plane);
|
||||
u32 pipestat_reg = 0;
|
||||
u32 mask_reg = 0;
|
||||
u32 pipestat;
|
||||
unsigned long irqflags;
|
||||
|
||||
switch (pipe) {
|
||||
case 0:
|
||||
pipestat_reg = PIPEASTAT;
|
||||
mask_reg |= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
|
||||
break;
|
||||
case 1:
|
||||
pipestat_reg = PIPEBSTAT;
|
||||
mask_reg |= I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
|
||||
break;
|
||||
default:
|
||||
DRM_ERROR("tried to disable vblank on non-existent pipe %d\n",
|
||||
pipe);
|
||||
break;
|
||||
}
|
||||
|
||||
DRM_SPINLOCK(&dev_priv->user_irq_lock);
|
||||
i915_disable_irq(dev_priv, mask_reg);
|
||||
DRM_SPINUNLOCK(&dev_priv->user_irq_lock);
|
||||
|
||||
if (pipestat_reg)
|
||||
{
|
||||
pipestat = I915_READ (pipestat_reg);
|
||||
pipestat &= ~(PIPE_START_VBLANK_INTERRUPT_ENABLE |
|
||||
PIPE_VBLANK_INTERRUPT_ENABLE);
|
||||
/*
|
||||
* Clear any pending status
|
||||
*/
|
||||
pipestat |= (PIPE_START_VBLANK_INTERRUPT_STATUS |
|
||||
PIPE_VBLANK_INTERRUPT_STATUS);
|
||||
I915_WRITE(pipestat_reg, pipestat);
|
||||
(void) I915_READ(pipestat_reg);
|
||||
}
|
||||
}
|
||||
|
||||
static void i915_enable_interrupt (struct drm_device *dev)
|
||||
{
|
||||
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
|
||||
|
||||
dev_priv->irq_mask_reg = ~0;
|
||||
I915_WRITE(IMR, dev_priv->irq_mask_reg);
|
||||
I915_WRITE(IER, I915_INTERRUPT_ENABLE_MASK);
|
||||
(void) I915_READ (IER);
|
||||
|
||||
#ifdef __linux__
|
||||
#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,25)
|
||||
opregion_enable_asle(dev);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
dev_priv->irq_enabled = 1;
|
||||
DRM_SPINLOCK_IRQSAVE(&dev_priv->user_irq_lock, irqflags);
|
||||
i915_disable_pipestat(dev_priv, pipe,
|
||||
PIPE_START_VBLANK_INTERRUPT_ENABLE | PIPE_VBLANK_INTERRUPT_ENABLE);
|
||||
DRM_SPINUNLOCK_IRQRESTORE(&dev_priv->user_irq_lock, irqflags);
|
||||
}
|
||||
|
||||
/* Set the vblank monitor pipe
|
||||
|
|
@ -542,55 +458,69 @@ void i915_driver_irq_preinstall(struct drm_device * dev)
|
|||
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
|
||||
|
||||
I915_WRITE(HWSTAM, 0xeffe);
|
||||
I915_WRITE(PIPEASTAT, 0);
|
||||
I915_WRITE(PIPEBSTAT, 0);
|
||||
I915_WRITE(IMR, 0xffffffff);
|
||||
I915_WRITE(IER, 0x0);
|
||||
(void) I915_READ(IER);
|
||||
}
|
||||
|
||||
int i915_driver_irq_postinstall(struct drm_device * dev)
|
||||
int i915_driver_irq_postinstall(struct drm_device *dev)
|
||||
{
|
||||
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
|
||||
int ret, num_pipes = 2;
|
||||
|
||||
dev_priv->user_irq_refcount = 0;
|
||||
dev_priv->irq_mask_reg = ~0;
|
||||
|
||||
ret = drm_vblank_init(dev, num_pipes);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
|
||||
|
||||
dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
|
||||
|
||||
i915_enable_interrupt(dev);
|
||||
/* Unmask the interrupts that we always want on. */
|
||||
dev_priv->irq_mask_reg = ~I915_INTERRUPT_ENABLE_FIX;
|
||||
|
||||
dev_priv->pipestat[0] = 0;
|
||||
dev_priv->pipestat[1] = 0;
|
||||
|
||||
/* Disable pipe interrupt enables, clear pending pipe status */
|
||||
I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff);
|
||||
I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff);
|
||||
|
||||
/* Clear pending interrupt status */
|
||||
I915_WRITE(IIR, I915_READ(IIR));
|
||||
|
||||
I915_WRITE(IER, I915_INTERRUPT_ENABLE_MASK);
|
||||
I915_WRITE(IMR, dev_priv->irq_mask_reg);
|
||||
(void) I915_READ(IER);
|
||||
#ifdef __linux__
|
||||
opregion_enable_asle(dev);
|
||||
#endif
|
||||
DRM_INIT_WAITQUEUE(&dev_priv->irq_queue);
|
||||
|
||||
/*
|
||||
* Initialize the hardware status page IRQ location.
|
||||
*/
|
||||
i915_enable_vblank(dev, 0);
|
||||
i915_enable_vblank(dev, 1);
|
||||
|
||||
I915_WRITE(INSTPM, (1 << 5) | (1 << 21));
|
||||
return 0;
|
||||
}
|
||||
|
||||
void i915_driver_irq_uninstall(struct drm_device * dev)
|
||||
{
|
||||
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
|
||||
u32 temp;
|
||||
|
||||
if (!dev_priv)
|
||||
return;
|
||||
|
||||
dev_priv->vblank_pipe = 0;
|
||||
|
||||
dev_priv->irq_enabled = 0;
|
||||
I915_WRITE(HWSTAM, 0xffffffff);
|
||||
I915_WRITE(PIPEASTAT, 0);
|
||||
I915_WRITE(PIPEBSTAT, 0);
|
||||
I915_WRITE(IMR, 0xffffffff);
|
||||
I915_WRITE(IER, 0x0);
|
||||
|
||||
temp = I915_READ(PIPEASTAT);
|
||||
I915_WRITE(PIPEASTAT, temp);
|
||||
temp = I915_READ(PIPEBSTAT);
|
||||
I915_WRITE(PIPEBSTAT, temp);
|
||||
temp = I915_READ(IIR);
|
||||
I915_WRITE(IIR, temp);
|
||||
I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff);
|
||||
I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff);
|
||||
I915_WRITE(IIR, I915_READ(IIR));
|
||||
}
|
||||
|
|
|
|||
1417
shared-core/i915_reg.h
Normal file
1417
shared-core/i915_reg.h
Normal file
File diff suppressed because it is too large
Load diff
Loading…
Add table
Reference in a new issue