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https://gitlab.freedesktop.org/mesa/drm.git
synced 2025-12-27 10:30:17 +01:00
Added the state hardware programming functions to here
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7aea29f4bc
commit
d04ebd5463
2 changed files with 88 additions and 1 deletions
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@ -253,6 +253,7 @@ extern int mach64_dma_vertex( struct inode *inode, struct file *filp,
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#define MACH64_SCALE_3D_CNTL 0x05fc
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#define MACH64_SCRATCH_REG0 0x0480
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#define MACH64_SCRATCH_REG1 0x0484
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#define MACH64_SECONDARY_TEX_OFF 0x0778
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#define MACH64_SETUP_CNTL 0x0304
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#define MACH64_SRC_CNTL 0x05b4
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# define MACH64_SRC_BM_ENABLE (1 << 8)
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@ -269,6 +270,7 @@ extern int mach64_dma_vertex( struct inode *inode, struct file *filp,
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#define MACH64_SRC_WIDTH1 0x0590
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#define MACH64_SRC_Y_X 0x058c
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#define MACH64_TEX_0_OFF 0x05c0
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#define MACH64_TEX_CNTL 0x0774
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#define MACH64_TEX_SIZE_PITCH 0x0770
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#define MACH64_TIMER_CONFIG 0x0428
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@ -33,6 +33,89 @@
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#include "drm.h"
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/* ================================================================
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* DMA hardware state programming functions
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*/
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static inline void mach64_emit_texture( drm_mach64_private_t *dev_priv )
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{
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drm_mach64_sarea_t *sarea_priv = dev_priv->sarea_priv;
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drm_mach64_context_regs_t *regs = &sarea_priv->context_state;
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u32 offset = ((regs->tex_size_pitch & 0xf0) >> 2);
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MACH64_WRITE( MACH64_TEX_SIZE_PITCH, regs->tex_size_pitch );
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MACH64_WRITE( MACH64_TEX_CNTL, regs->tex_cntl );
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MACH64_WRITE( MACH64_SECONDARY_TEX_OFF, regs->secondary_tex_off );
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MACH64_WRITE( MACH64_TEX_0_OFF + offset, regs->tex_offset );
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}
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static inline void mach64_emit_state( drm_mach64_private_t *dev_priv )
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{
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drm_mach64_sarea_t *sarea_priv = dev_priv->sarea_priv;
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drm_mach64_context_regs_t *regs = &sarea_priv->context_state;
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unsigned int dirty = sarea_priv->dirty;
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DRM_DEBUG( "%s: dirty=0x%08x\n", __FUNCTION__, dirty );
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if ( dirty & MACH64_UPLOAD_MISC ) {
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MACH64_WRITE( MACH64_DP_MIX, regs->dp_mix );
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MACH64_WRITE( MACH64_DP_SRC, regs->dp_src );
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MACH64_WRITE( MACH64_CLR_CMP_CNTL, regs->clr_cmp_cntl );
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MACH64_WRITE( MACH64_GUI_TRAJ_CNTL, regs->gui_traj_cntl );
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sarea_priv->dirty &= ~MACH64_UPLOAD_MISC;
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}
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if ( dirty & MACH64_UPLOAD_DST_OFF_PITCH ) {
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MACH64_WRITE( MACH64_DST_OFF_PITCH, regs->dst_off_pitch );
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sarea_priv->dirty &= ~MACH64_UPLOAD_DST_OFF_PITCH;
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}
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if ( dirty & MACH64_UPLOAD_Z_OFF_PITCH ) {
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MACH64_WRITE( MACH64_Z_OFF_PITCH, regs->z_off_pitch );
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sarea_priv->dirty &= ~MACH64_UPLOAD_Z_OFF_PITCH;
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}
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if ( dirty & MACH64_UPLOAD_Z_ALPHA_CNTL ) {
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MACH64_WRITE( MACH64_Z_CNTL, regs->z_cntl );
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MACH64_WRITE( MACH64_ALPHA_TST_CNTL, regs->alpha_tst_cntl );
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sarea_priv->dirty &= ~MACH64_UPLOAD_Z_ALPHA_CNTL;
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}
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if ( dirty & MACH64_UPLOAD_SCALE_3D_CNTL ) {
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MACH64_WRITE( MACH64_SCALE_3D_CNTL, regs->scale_3d_cntl );
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sarea_priv->dirty &= ~MACH64_UPLOAD_SCALE_3D_CNTL;
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}
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if ( dirty & MACH64_UPLOAD_DP_FOG_CLR ) {
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MACH64_WRITE( MACH64_DP_FOG_CLR, regs->dp_fog_clr );
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sarea_priv->dirty &= ~MACH64_UPLOAD_DP_FOG_CLR;
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}
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if ( dirty & MACH64_UPLOAD_DP_WRITE_MASK ) {
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MACH64_WRITE( MACH64_DP_WRITE_MASK, regs->dp_write_mask );
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sarea_priv->dirty &= ~MACH64_UPLOAD_DP_WRITE_MASK;
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}
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if ( dirty & MACH64_UPLOAD_DP_PIX_WIDTH ) {
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MACH64_WRITE( MACH64_DP_PIX_WIDTH, regs->dp_pix_width );
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sarea_priv->dirty &= ~MACH64_UPLOAD_DP_PIX_WIDTH;
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}
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if ( dirty & MACH64_UPLOAD_SETUP_CNTL ) {
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MACH64_WRITE( MACH64_SETUP_CNTL, regs->setup_cntl );
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sarea_priv->dirty &= ~MACH64_UPLOAD_SETUP_CNTL;
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}
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if ( dirty & MACH64_UPLOAD_TEXTURE ) {
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mach64_emit_texture( dev_priv );
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sarea_priv->dirty &= ~MACH64_UPLOAD_TEXTURE;
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}
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if ( dirty & MACH64_UPLOAD_CLIPRECTS ) {
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MACH64_WRITE( MACH64_SC_LEFT_RIGHT, regs->sc_left_right );
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MACH64_WRITE( MACH64_SC_TOP_BOTTOM, regs->sc_top_bottom );
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sarea_priv->dirty &= ~MACH64_UPLOAD_CLIPRECTS;
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}
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/* FIXME: Is this really necessary? */
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sarea_priv->dirty = 0;
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}
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/* ================================================================
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* DMA command dispatch functions
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*/
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@ -316,9 +399,11 @@ static void mach64_dma_dispatch_vertex( drm_device_t *dev,
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buf_priv->dispatched = 1;
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if ( sarea_priv->dirty & ~MACH64_UPLOAD_CLIPRECTS ) {
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#else
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if ( sarea_priv->dirty ) {
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#endif
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mach64_emit_state( dev_priv );
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}
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#endif
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do {
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#if 0
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