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intel: Fix Haswell CRW PCI IDs.

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The second digit was off by one, which meant we accidentally treated
GT(n) as GT(n-1).  This also meant no support for GT1 at all.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
This commit is contained in:
Kenneth Graunke 2013-03-01 15:37:01 -08:00
parent 1eb2860b4b
commit ca678bc073
1 changed files with 9 additions and 9 deletions
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18
intel/intel_chipset.h
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@ -115,15 +115,15 @@
#define PCI_CHIP_HASWELL_ULT_S_GT1 0x0A0A /* Server */ #define PCI_CHIP_HASWELL_ULT_S_GT1 0x0A0A /* Server */
#define PCI_CHIP_HASWELL_ULT_S_GT2 0x0A1A #define PCI_CHIP_HASWELL_ULT_S_GT2 0x0A1A
#define PCI_CHIP_HASWELL_ULT_S_GT2_PLUS 0x0A2A #define PCI_CHIP_HASWELL_ULT_S_GT2_PLUS 0x0A2A
#define PCI_CHIP_HASWELL_CRW_GT1 0x0D12 /* Desktop */ #define PCI_CHIP_HASWELL_CRW_GT1 0x0D02 /* Desktop */
#define PCI_CHIP_HASWELL_CRW_GT2 0x0D22 #define PCI_CHIP_HASWELL_CRW_GT2 0x0D12
#define PCI_CHIP_HASWELL_CRW_GT2_PLUS 0x0D32 #define PCI_CHIP_HASWELL_CRW_GT2_PLUS 0x0D22
#define PCI_CHIP_HASWELL_CRW_M_GT1 0x0D16 /* Mobile */ #define PCI_CHIP_HASWELL_CRW_M_GT1 0x0D06 /* Mobile */
#define PCI_CHIP_HASWELL_CRW_M_GT2 0x0D26 #define PCI_CHIP_HASWELL_CRW_M_GT2 0x0D16
#define PCI_CHIP_HASWELL_CRW_M_GT2_PLUS 0x0D36 #define PCI_CHIP_HASWELL_CRW_M_GT2_PLUS 0x0D26
#define PCI_CHIP_HASWELL_CRW_S_GT1 0x0D1A /* Server */ #define PCI_CHIP_HASWELL_CRW_S_GT1 0x0D0A /* Server */
#define PCI_CHIP_HASWELL_CRW_S_GT2 0x0D2A #define PCI_CHIP_HASWELL_CRW_S_GT2 0x0D1A
#define PCI_CHIP_HASWELL_CRW_S_GT2_PLUS 0x0D3A #define PCI_CHIP_HASWELL_CRW_S_GT2_PLUS 0x0D2A
#define PCI_CHIP_VALLEYVIEW_PO 0x0f30 /* VLV PO board */ #define PCI_CHIP_VALLEYVIEW_PO 0x0f30 /* VLV PO board */
#define PCI_CHIP_VALLEYVIEW_1 0x0f31 #define PCI_CHIP_VALLEYVIEW_1 0x0f31