mirror of
https://gitlab.freedesktop.org/mesa/drm.git
synced 2026-05-05 12:28:03 +02:00
libdrm: make a branch for libdrm which drops all the TTM apis.
This will be the next release of libdrm as 2.3.1, Mesa needs to deal with this for 7.1.
This commit is contained in:
Dave Airlie
parent
5b86823fa3
commit
c28c1cf756
5 changed files with 4 additions and 988 deletions
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@ -20,12 +20,13 @@
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libdrm_la_LTLIBRARIES = libdrm.la
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libdrm_ladir = $(libdir)
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libdrm_la_LDFLAGS = -version-number 2:3:0 -no-undefined
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libdrm_la_LDFLAGS = -version-number 2:3:1 -no-undefined
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AM_CFLAGS = -I$(top_srcdir)/shared-core
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libdrm_la_SOURCES = xf86drm.c xf86drmHash.c xf86drmRandom.c xf86drmSL.c
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libdrmincludedir = ${includedir}
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libdrminclude_HEADERS = xf86drm.h xf86mm.h
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libdrminclude_HEADERS = xf86drm.h
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EXTRA_DIST = ChangeLog TODO
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573
libdrm/xf86drm.c
573
libdrm/xf86drm.c
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@ -2337,579 +2337,6 @@ int drmCommandWriteRead(int fd, unsigned long drmCommandIndex, void *data,
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return 0;
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}
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/*
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* Valid flags are
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* DRM_FENCE_FLAG_EMIT
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* DRM_FENCE_FLAG_SHAREABLE
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* DRM_FENCE_MASK_DRIVER
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*/
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int drmFenceCreate(int fd, unsigned flags, int fence_class, unsigned type,
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drmFence *fence)
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{
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drm_fence_arg_t arg;
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memset(&arg, 0, sizeof(arg));
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arg.flags = flags;
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arg.type = type;
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arg.fence_class = fence_class;
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if (ioctl(fd, DRM_IOCTL_FENCE_CREATE, &arg))
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return -errno;
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fence->handle = arg.handle;
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fence->fence_class = arg.fence_class;
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fence->type = arg.type;
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fence->flags = arg.flags;
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fence->signaled = 0;
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return 0;
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}
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/*
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* Valid flags are
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* DRM_FENCE_FLAG_SHAREABLE
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* DRM_FENCE_MASK_DRIVER
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*/
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int drmFenceBuffers(int fd, unsigned flags, uint32_t fence_class, drmFence *fence)
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{
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drm_fence_arg_t arg;
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memset(&arg, 0, sizeof(arg));
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arg.flags = flags;
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arg.fence_class = fence_class;
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if (ioctl(fd, DRM_IOCTL_FENCE_BUFFERS, &arg))
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return -errno;
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fence->handle = arg.handle;
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fence->fence_class = arg.fence_class;
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fence->type = arg.type;
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fence->flags = arg.flags;
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fence->sequence = arg.sequence;
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fence->signaled = 0;
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return 0;
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}
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int drmFenceReference(int fd, unsigned handle, drmFence *fence)
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{
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drm_fence_arg_t arg;
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memset(&arg, 0, sizeof(arg));
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arg.handle = handle;
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if (ioctl(fd, DRM_IOCTL_FENCE_REFERENCE, &arg))
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return -errno;
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fence->handle = arg.handle;
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fence->fence_class = arg.fence_class;
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fence->type = arg.type;
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fence->flags = arg.flags;
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fence->signaled = arg.signaled;
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return 0;
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}
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int drmFenceUnreference(int fd, const drmFence *fence)
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{
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drm_fence_arg_t arg;
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memset(&arg, 0, sizeof(arg));
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arg.handle = fence->handle;
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if (ioctl(fd, DRM_IOCTL_FENCE_UNREFERENCE, &arg))
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return -errno;
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return 0;
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}
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int drmFenceFlush(int fd, drmFence *fence, unsigned flush_type)
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{
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drm_fence_arg_t arg;
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memset(&arg, 0, sizeof(arg));
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arg.handle = fence->handle;
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arg.type = flush_type;
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if (ioctl(fd, DRM_IOCTL_FENCE_FLUSH, &arg))
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return -errno;
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fence->fence_class = arg.fence_class;
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fence->type = arg.type;
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fence->signaled = arg.signaled;
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return arg.error;
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}
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int drmFenceUpdate(int fd, drmFence *fence)
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{
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drm_fence_arg_t arg;
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memset(&arg, 0, sizeof(arg));
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arg.handle = fence->handle;
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if (ioctl(fd, DRM_IOCTL_FENCE_SIGNALED, &arg))
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return -errno;
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fence->fence_class = arg.fence_class;
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fence->type = arg.type;
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fence->signaled = arg.signaled;
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return 0;
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}
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int drmFenceSignaled(int fd, drmFence *fence, unsigned fenceType,
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int *signaled)
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{
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if ((fence->flags & DRM_FENCE_FLAG_SHAREABLE) ||
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((fenceType & fence->signaled) != fenceType)) {
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int ret = drmFenceFlush(fd, fence, fenceType);
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if (ret)
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return ret;
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}
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*signaled = ((fenceType & fence->signaled) == fenceType);
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return 0;
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}
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/*
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* Valid flags are
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* DRM_FENCE_FLAG_SHAREABLE
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* DRM_FENCE_MASK_DRIVER
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*/
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int drmFenceEmit(int fd, unsigned flags, drmFence *fence, unsigned emit_type)
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{
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drm_fence_arg_t arg;
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memset(&arg, 0, sizeof(arg));
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arg.fence_class = fence->fence_class;
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arg.flags = flags;
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arg.handle = fence->handle;
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arg.type = emit_type;
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if (ioctl(fd, DRM_IOCTL_FENCE_EMIT, &arg))
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return -errno;
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fence->fence_class = arg.fence_class;
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fence->type = arg.type;
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fence->signaled = arg.signaled;
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fence->sequence = arg.sequence;
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return 0;
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}
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/*
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* Valid flags are
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* DRM_FENCE_FLAG_WAIT_LAZY
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* DRM_FENCE_FLAG_WAIT_IGNORE_SIGNALS
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*/
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#define DRM_IOCTL_TIMEOUT_USEC 3000000UL
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static unsigned long
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drmTimeDiff(struct timeval *now, struct timeval *then)
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{
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uint64_t val;
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val = now->tv_sec - then->tv_sec;
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val *= 1000000LL;
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val += now->tv_usec;
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val -= then->tv_usec;
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return (unsigned long) val;
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}
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static int
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drmIoctlTimeout(int fd, unsigned long request, void *argp)
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{
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int haveThen = 0;
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struct timeval then, now;
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int ret;
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do {
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ret = ioctl(fd, request, argp);
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if (ret != 0 && errno == EAGAIN) {
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if (!haveThen) {
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gettimeofday(&then, NULL);
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haveThen = 1;
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}
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gettimeofday(&now, NULL);
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}
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} while (ret != 0 && errno == EAGAIN &&
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drmTimeDiff(&now, &then) < DRM_IOCTL_TIMEOUT_USEC);
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if (ret != 0)
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return ((errno == EAGAIN) ? -EBUSY : -errno);
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return 0;
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}
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int drmFenceWait(int fd, unsigned flags, drmFence *fence, unsigned flush_type)
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{
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drm_fence_arg_t arg;
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int ret;
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if (flush_type == 0) {
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flush_type = fence->type;
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}
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if (!(fence->flags & DRM_FENCE_FLAG_SHAREABLE)) {
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if ((flush_type & fence->signaled) == flush_type) {
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return 0;
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}
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}
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memset(&arg, 0, sizeof(arg));
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arg.handle = fence->handle;
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arg.type = flush_type;
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arg.flags = flags;
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ret = drmIoctlTimeout(fd, DRM_IOCTL_FENCE_WAIT, &arg);
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if (ret)
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return ret;
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fence->fence_class = arg.fence_class;
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fence->type = arg.type;
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fence->signaled = arg.signaled;
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return arg.error;
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}
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static void drmBOCopyReply(const struct drm_bo_info_rep *rep, drmBO *buf)
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{
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buf->handle = rep->handle;
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buf->flags = rep->flags;
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buf->size = rep->size;
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buf->offset = rep->offset;
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buf->mapHandle = rep->arg_handle;
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buf->proposedFlags = rep->proposed_flags;
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buf->start = rep->buffer_start;
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buf->fenceFlags = rep->fence_flags;
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buf->replyFlags = rep->rep_flags;
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buf->pageAlignment = rep->page_alignment;
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buf->tileInfo = rep->tile_info;
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buf->hwTileStride = rep->hw_tile_stride;
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buf->desiredTileStride = rep->desired_tile_stride;
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}
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int drmBOCreate(int fd, unsigned long size,
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unsigned pageAlignment, void *user_buffer,
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uint64_t flags,
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unsigned hint, drmBO *buf)
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{
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struct drm_bo_create_arg arg;
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struct drm_bo_create_req *req = &arg.d.req;
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struct drm_bo_info_rep *rep = &arg.d.rep;
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int ret;
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memset(buf, 0, sizeof(*buf));
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memset(&arg, 0, sizeof(arg));
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req->flags = flags;
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req->hint = hint;
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req->size = size;
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req->page_alignment = pageAlignment;
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req->buffer_start = (unsigned long) user_buffer;
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buf->virtual = NULL;
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ret = drmIoctlTimeout(fd, DRM_IOCTL_BO_CREATE, &arg);
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if (ret)
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return ret;
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drmBOCopyReply(rep, buf);
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buf->virtual = user_buffer;
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buf->mapCount = 0;
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return 0;
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}
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int drmBOReference(int fd, unsigned handle, drmBO *buf)
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{
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struct drm_bo_reference_info_arg arg;
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struct drm_bo_handle_arg *req = &arg.d.req;
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struct drm_bo_info_rep *rep = &arg.d.rep;
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memset(&arg, 0, sizeof(arg));
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req->handle = handle;
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if (ioctl(fd, DRM_IOCTL_BO_REFERENCE, &arg))
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return -errno;
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drmBOCopyReply(rep, buf);
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buf->mapVirtual = NULL;
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buf->mapCount = 0;
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buf->virtual = NULL;
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return 0;
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}
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int drmBOUnreference(int fd, drmBO *buf)
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{
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struct drm_bo_handle_arg arg;
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if (buf->mapVirtual && buf->mapHandle) {
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(void) munmap(buf->mapVirtual, buf->start + buf->size);
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buf->mapVirtual = NULL;
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buf->virtual = NULL;
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}
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memset(&arg, 0, sizeof(arg));
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arg.handle = buf->handle;
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if (ioctl(fd, DRM_IOCTL_BO_UNREFERENCE, &arg))
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return -errno;
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buf->handle = 0;
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return 0;
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}
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/*
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* Flags can be DRM_BO_FLAG_READ, DRM_BO_FLAG_WRITE or'ed together
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* Hint currently be DRM_BO_HINT_DONT_BLOCK, which makes the
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* call return an -EBUSY if it can' immediately honor the mapping request.
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*/
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int drmBOMap(int fd, drmBO *buf, unsigned mapFlags, unsigned mapHint,
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void **address)
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{
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struct drm_bo_map_wait_idle_arg arg;
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struct drm_bo_info_req *req = &arg.d.req;
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struct drm_bo_info_rep *rep = &arg.d.rep;
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int ret = 0;
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/*
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* Make sure we have a virtual address of the buffer.
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*/
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if (!buf->virtual) {
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drmAddress virtual;
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virtual = mmap(0, buf->size + buf->start,
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PROT_READ | PROT_WRITE, MAP_SHARED,
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fd, buf->mapHandle);
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if (virtual == MAP_FAILED) {
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ret = -errno;
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}
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if (ret)
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return ret;
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buf->mapVirtual = virtual;
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buf->virtual = ((char *) virtual) + buf->start;
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}
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memset(&arg, 0, sizeof(arg));
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req->handle = buf->handle;
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req->mask = mapFlags;
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req->hint = mapHint;
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/*
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* May hang if the buffer object is busy.
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* This IOCTL synchronizes the buffer.
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*/
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ret = drmIoctlTimeout(fd, DRM_IOCTL_BO_MAP, &arg);
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if (ret)
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return ret;
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drmBOCopyReply(rep, buf);
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buf->mapFlags = mapFlags;
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++buf->mapCount;
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*address = buf->virtual;
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return 0;
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}
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int drmBOUnmap(int fd, drmBO *buf)
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{
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struct drm_bo_handle_arg arg;
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memset(&arg, 0, sizeof(arg));
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arg.handle = buf->handle;
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if (ioctl(fd, DRM_IOCTL_BO_UNMAP, &arg)) {
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return -errno;
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}
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buf->mapCount--;
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return 0;
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}
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int drmBOSetStatus(int fd, drmBO *buf,
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uint64_t flags, uint64_t mask,
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unsigned int hint,
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unsigned int desired_tile_stride,
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unsigned int tile_info)
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{
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struct drm_bo_map_wait_idle_arg arg;
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struct drm_bo_info_req *req = &arg.d.req;
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struct drm_bo_info_rep *rep = &arg.d.rep;
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int ret = 0;
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memset(&arg, 0, sizeof(arg));
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req->mask = mask;
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req->flags = flags;
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req->handle = buf->handle;
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req->hint = hint;
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req->desired_tile_stride = desired_tile_stride;
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req->tile_info = tile_info;
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ret = drmIoctlTimeout(fd, DRM_IOCTL_BO_SETSTATUS, &arg);
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if (ret)
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return ret;
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drmBOCopyReply(rep, buf);
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return 0;
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}
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int drmBOInfo(int fd, drmBO *buf)
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{
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struct drm_bo_reference_info_arg arg;
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struct drm_bo_handle_arg *req = &arg.d.req;
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struct drm_bo_info_rep *rep = &arg.d.rep;
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int ret = 0;
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memset(&arg, 0, sizeof(arg));
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req->handle = buf->handle;
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ret = ioctl(fd, DRM_IOCTL_BO_INFO, &arg);
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if (ret)
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return -errno;
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drmBOCopyReply(rep, buf);
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return 0;
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}
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int drmBOWaitIdle(int fd, drmBO *buf, unsigned hint)
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{
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struct drm_bo_map_wait_idle_arg arg;
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struct drm_bo_info_req *req = &arg.d.req;
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struct drm_bo_info_rep *rep = &arg.d.rep;
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int ret = 0;
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if ((buf->flags & DRM_BO_FLAG_SHAREABLE) ||
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(buf->replyFlags & DRM_BO_REP_BUSY)) {
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memset(&arg, 0, sizeof(arg));
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req->handle = buf->handle;
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req->hint = hint;
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ret = drmIoctlTimeout(fd, DRM_IOCTL_BO_WAIT_IDLE, &arg);
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if (ret)
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return ret;
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drmBOCopyReply(rep, buf);
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}
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return 0;
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}
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int drmBOBusy(int fd, drmBO *buf, int *busy)
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{
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int ret = drmBOInfo(fd, buf);
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if (ret)
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return ret;
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*busy = (buf->replyFlags & DRM_BO_REP_BUSY);
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return 0;
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}
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int drmMMInit(int fd, unsigned long pOffset, unsigned long pSize,
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unsigned memType)
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{
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struct drm_mm_init_arg arg;
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memset(&arg, 0, sizeof(arg));
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arg.magic = DRM_BO_INIT_MAGIC;
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arg.major = DRM_BO_INIT_MAJOR;
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arg.minor = DRM_BO_INIT_MINOR;
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arg.p_offset = pOffset;
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arg.p_size = pSize;
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arg.mem_type = memType;
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if (ioctl(fd, DRM_IOCTL_MM_INIT, &arg))
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return -errno;
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return 0;
|
||||
}
|
||||
|
||||
int drmMMTakedown(int fd, unsigned memType)
|
||||
{
|
||||
struct drm_mm_type_arg arg;
|
||||
|
||||
memset(&arg, 0, sizeof(arg));
|
||||
arg.mem_type = memType;
|
||||
|
||||
if (ioctl(fd, DRM_IOCTL_MM_TAKEDOWN, &arg))
|
||||
return -errno;
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* If this function returns an error, and lockBM was set to 1,
|
||||
* the buffer manager is NOT locked.
|
||||
*/
|
||||
|
||||
int drmMMLock(int fd, unsigned memType, int lockBM, int ignoreNoEvict)
|
||||
{
|
||||
struct drm_mm_type_arg arg;
|
||||
|
||||
memset(&arg, 0, sizeof(arg));
|
||||
arg.mem_type = memType;
|
||||
arg.lock_flags |= (lockBM) ? DRM_BO_LOCK_UNLOCK_BM : 0;
|
||||
arg.lock_flags |= (ignoreNoEvict) ? DRM_BO_LOCK_IGNORE_NO_EVICT : 0;
|
||||
|
||||
return drmIoctlTimeout(fd, DRM_IOCTL_MM_LOCK, &arg);
|
||||
}
|
||||
|
||||
int drmMMUnlock(int fd, unsigned memType, int unlockBM)
|
||||
{
|
||||
struct drm_mm_type_arg arg;
|
||||
|
||||
memset(&arg, 0, sizeof(arg));
|
||||
|
||||
arg.mem_type = memType;
|
||||
arg.lock_flags |= (unlockBM) ? DRM_BO_LOCK_UNLOCK_BM : 0;
|
||||
|
||||
return drmIoctlTimeout(fd, DRM_IOCTL_MM_UNLOCK, &arg);
|
||||
}
|
||||
|
||||
int drmMMInfo(int fd, unsigned memType, uint64_t *size)
|
||||
{
|
||||
struct drm_mm_info_arg arg;
|
||||
|
||||
memset(&arg, 0, sizeof(arg));
|
||||
|
||||
arg.mem_type = memType;
|
||||
|
||||
if (ioctl(fd, DRM_IOCTL_MM_INFO, &arg))
|
||||
return -errno;
|
||||
|
||||
*size = arg.p_size;
|
||||
return 0;
|
||||
}
|
||||
|
||||
int drmBOVersion(int fd, unsigned int *major,
|
||||
unsigned int *minor,
|
||||
unsigned int *patchlevel)
|
||||
{
|
||||
struct drm_bo_version_arg arg;
|
||||
int ret;
|
||||
|
||||
memset(&arg, 0, sizeof(arg));
|
||||
ret = ioctl(fd, DRM_IOCTL_BO_VERSION, &arg);
|
||||
if (ret)
|
||||
return -errno;
|
||||
|
||||
if (major)
|
||||
*major = arg.major;
|
||||
if (minor)
|
||||
*minor = arg.minor;
|
||||
if (patchlevel)
|
||||
*patchlevel = arg.patchlevel;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
|
||||
#define DRM_MAX_FDS 16
|
||||
static struct {
|
||||
char *BusID;
|
||||
|
|
|
|||
|
|
@ -29,12 +29,10 @@ klibdrminclude_HEADERS = \
|
|||
i915_drm.h \
|
||||
mach64_drm.h \
|
||||
mga_drm.h \
|
||||
nouveau_drm.h \
|
||||
r128_drm.h \
|
||||
radeon_drm.h \
|
||||
savage_drm.h \
|
||||
sis_drm.h \
|
||||
via_drm.h \
|
||||
r300_reg.h \
|
||||
via_3d_reg.h \
|
||||
xgi_drm.h
|
||||
via_3d_reg.h
|
||||
|
|
|
|||
|
|
@ -236,7 +236,6 @@ enum drm_map_type {
|
|||
_DRM_AGP = 3, /**< AGP/GART */
|
||||
_DRM_SCATTER_GATHER = 4, /**< Scatter/gather memory for PCI DMA */
|
||||
_DRM_CONSISTENT = 5, /**< Consistent memory for PCI DMA */
|
||||
_DRM_TTM = 6
|
||||
};
|
||||
|
||||
/**
|
||||
|
|
@ -641,324 +640,6 @@ struct drm_set_version {
|
|||
int drm_dd_minor;
|
||||
};
|
||||
|
||||
|
||||
#define DRM_FENCE_FLAG_EMIT 0x00000001
|
||||
#define DRM_FENCE_FLAG_SHAREABLE 0x00000002
|
||||
/**
|
||||
* On hardware with no interrupt events for operation completion,
|
||||
* indicates that the kernel should sleep while waiting for any blocking
|
||||
* operation to complete rather than spinning.
|
||||
*
|
||||
* Has no effect otherwise.
|
||||
*/
|
||||
#define DRM_FENCE_FLAG_WAIT_LAZY 0x00000004
|
||||
#define DRM_FENCE_FLAG_NO_USER 0x00000010
|
||||
|
||||
/* Reserved for driver use */
|
||||
#define DRM_FENCE_MASK_DRIVER 0xFF000000
|
||||
|
||||
#define DRM_FENCE_TYPE_EXE 0x00000001
|
||||
|
||||
struct drm_fence_arg {
|
||||
unsigned int handle;
|
||||
unsigned int fence_class;
|
||||
unsigned int type;
|
||||
unsigned int flags;
|
||||
unsigned int signaled;
|
||||
unsigned int error;
|
||||
unsigned int sequence;
|
||||
unsigned int pad64;
|
||||
uint64_t expand_pad[2]; /*Future expansion */
|
||||
};
|
||||
|
||||
/* Buffer permissions, referring to how the GPU uses the buffers.
|
||||
* these translate to fence types used for the buffers.
|
||||
* Typically a texture buffer is read, A destination buffer is write and
|
||||
* a command (batch-) buffer is exe. Can be or-ed together.
|
||||
*/
|
||||
|
||||
#define DRM_BO_FLAG_READ (1ULL << 0)
|
||||
#define DRM_BO_FLAG_WRITE (1ULL << 1)
|
||||
#define DRM_BO_FLAG_EXE (1ULL << 2)
|
||||
|
||||
/*
|
||||
* All of the bits related to access mode
|
||||
*/
|
||||
#define DRM_BO_MASK_ACCESS (DRM_BO_FLAG_READ | DRM_BO_FLAG_WRITE | DRM_BO_FLAG_EXE)
|
||||
/*
|
||||
* Status flags. Can be read to determine the actual state of a buffer.
|
||||
* Can also be set in the buffer mask before validation.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Mask: Never evict this buffer. Not even with force. This type of buffer is only
|
||||
* available to root and must be manually removed before buffer manager shutdown
|
||||
* or lock.
|
||||
* Flags: Acknowledge
|
||||
*/
|
||||
#define DRM_BO_FLAG_NO_EVICT (1ULL << 4)
|
||||
|
||||
/*
|
||||
* Mask: Require that the buffer is placed in mappable memory when validated.
|
||||
* If not set the buffer may or may not be in mappable memory when validated.
|
||||
* Flags: If set, the buffer is in mappable memory.
|
||||
*/
|
||||
#define DRM_BO_FLAG_MAPPABLE (1ULL << 5)
|
||||
|
||||
/* Mask: The buffer should be shareable with other processes.
|
||||
* Flags: The buffer is shareable with other processes.
|
||||
*/
|
||||
#define DRM_BO_FLAG_SHAREABLE (1ULL << 6)
|
||||
|
||||
/* Mask: If set, place the buffer in cache-coherent memory if available.
|
||||
* If clear, never place the buffer in cache coherent memory if validated.
|
||||
* Flags: The buffer is currently in cache-coherent memory.
|
||||
*/
|
||||
#define DRM_BO_FLAG_CACHED (1ULL << 7)
|
||||
|
||||
/* Mask: Make sure that every time this buffer is validated,
|
||||
* it ends up on the same location provided that the memory mask is the same.
|
||||
* The buffer will also not be evicted when claiming space for
|
||||
* other buffers. Basically a pinned buffer but it may be thrown out as
|
||||
* part of buffer manager shutdown or locking.
|
||||
* Flags: Acknowledge.
|
||||
*/
|
||||
#define DRM_BO_FLAG_NO_MOVE (1ULL << 8)
|
||||
|
||||
/* Mask: Make sure the buffer is in cached memory when mapped. In conjunction
|
||||
* with DRM_BO_FLAG_CACHED it also allows the buffer to be bound into the GART
|
||||
* with unsnooped PTEs instead of snooped, by using chipset-specific cache
|
||||
* flushing at bind time. A better name might be DRM_BO_FLAG_TT_UNSNOOPED,
|
||||
* as the eviction to local memory (TTM unbind) on map is just a side effect
|
||||
* to prevent aggressive cache prefetch from the GPU disturbing the cache
|
||||
* management that the DRM is doing.
|
||||
*
|
||||
* Flags: Acknowledge.
|
||||
* Buffers allocated with this flag should not be used for suballocators
|
||||
* This type may have issues on CPUs with over-aggressive caching
|
||||
* http://marc.info/?l=linux-kernel&m=102376926732464&w=2
|
||||
*/
|
||||
#define DRM_BO_FLAG_CACHED_MAPPED (1ULL << 19)
|
||||
|
||||
|
||||
/* Mask: Force DRM_BO_FLAG_CACHED flag strictly also if it is set.
|
||||
* Flags: Acknowledge.
|
||||
*/
|
||||
#define DRM_BO_FLAG_FORCE_CACHING (1ULL << 13)
|
||||
|
||||
/*
|
||||
* Mask: Force DRM_BO_FLAG_MAPPABLE flag strictly also if it is clear.
|
||||
* Flags: Acknowledge.
|
||||
*/
|
||||
#define DRM_BO_FLAG_FORCE_MAPPABLE (1ULL << 14)
|
||||
#define DRM_BO_FLAG_TILE (1ULL << 15)
|
||||
|
||||
/*
|
||||
* Memory type flags that can be or'ed together in the mask, but only
|
||||
* one appears in flags.
|
||||
*/
|
||||
|
||||
/* System memory */
|
||||
#define DRM_BO_FLAG_MEM_LOCAL (1ULL << 24)
|
||||
/* Translation table memory */
|
||||
#define DRM_BO_FLAG_MEM_TT (1ULL << 25)
|
||||
/* Vram memory */
|
||||
#define DRM_BO_FLAG_MEM_VRAM (1ULL << 26)
|
||||
/* Up to the driver to define. */
|
||||
#define DRM_BO_FLAG_MEM_PRIV0 (1ULL << 27)
|
||||
#define DRM_BO_FLAG_MEM_PRIV1 (1ULL << 28)
|
||||
#define DRM_BO_FLAG_MEM_PRIV2 (1ULL << 29)
|
||||
#define DRM_BO_FLAG_MEM_PRIV3 (1ULL << 30)
|
||||
#define DRM_BO_FLAG_MEM_PRIV4 (1ULL << 31)
|
||||
/* We can add more of these now with a 64-bit flag type */
|
||||
|
||||
/*
|
||||
* This is a mask covering all of the memory type flags; easier to just
|
||||
* use a single constant than a bunch of | values. It covers
|
||||
* DRM_BO_FLAG_MEM_LOCAL through DRM_BO_FLAG_MEM_PRIV4
|
||||
*/
|
||||
#define DRM_BO_MASK_MEM 0x00000000FF000000ULL
|
||||
/*
|
||||
* This adds all of the CPU-mapping options in with the memory
|
||||
* type to label all bits which change how the page gets mapped
|
||||
*/
|
||||
#define DRM_BO_MASK_MEMTYPE (DRM_BO_MASK_MEM | \
|
||||
DRM_BO_FLAG_CACHED_MAPPED | \
|
||||
DRM_BO_FLAG_CACHED | \
|
||||
DRM_BO_FLAG_MAPPABLE)
|
||||
|
||||
/* Driver-private flags */
|
||||
#define DRM_BO_MASK_DRIVER 0xFFFF000000000000ULL
|
||||
|
||||
/*
|
||||
* Don't block on validate and map. Instead, return EBUSY.
|
||||
*/
|
||||
#define DRM_BO_HINT_DONT_BLOCK 0x00000002
|
||||
/*
|
||||
* Don't place this buffer on the unfenced list. This means
|
||||
* that the buffer will not end up having a fence associated
|
||||
* with it as a result of this operation
|
||||
*/
|
||||
#define DRM_BO_HINT_DONT_FENCE 0x00000004
|
||||
/**
|
||||
* On hardware with no interrupt events for operation completion,
|
||||
* indicates that the kernel should sleep while waiting for any blocking
|
||||
* operation to complete rather than spinning.
|
||||
*
|
||||
* Has no effect otherwise.
|
||||
*/
|
||||
#define DRM_BO_HINT_WAIT_LAZY 0x00000008
|
||||
/*
|
||||
* The client has compute relocations refering to this buffer using the
|
||||
* offset in the presumed_offset field. If that offset ends up matching
|
||||
* where this buffer lands, the kernel is free to skip executing those
|
||||
* relocations
|
||||
*/
|
||||
#define DRM_BO_HINT_PRESUMED_OFFSET 0x00000010
|
||||
|
||||
#define DRM_BO_INIT_MAGIC 0xfe769812
|
||||
#define DRM_BO_INIT_MAJOR 1
|
||||
#define DRM_BO_INIT_MINOR 0
|
||||
#define DRM_BO_INIT_PATCH 0
|
||||
|
||||
|
||||
struct drm_bo_info_req {
|
||||
uint64_t mask;
|
||||
uint64_t flags;
|
||||
unsigned int handle;
|
||||
unsigned int hint;
|
||||
unsigned int fence_class;
|
||||
unsigned int desired_tile_stride;
|
||||
unsigned int tile_info;
|
||||
unsigned int pad64;
|
||||
uint64_t presumed_offset;
|
||||
};
|
||||
|
||||
struct drm_bo_create_req {
|
||||
uint64_t flags;
|
||||
uint64_t size;
|
||||
uint64_t buffer_start;
|
||||
unsigned int hint;
|
||||
unsigned int page_alignment;
|
||||
};
|
||||
|
||||
|
||||
/*
|
||||
* Reply flags
|
||||
*/
|
||||
|
||||
#define DRM_BO_REP_BUSY 0x00000001
|
||||
|
||||
struct drm_bo_info_rep {
|
||||
uint64_t flags;
|
||||
uint64_t proposed_flags;
|
||||
uint64_t size;
|
||||
uint64_t offset;
|
||||
uint64_t arg_handle;
|
||||
uint64_t buffer_start;
|
||||
unsigned int handle;
|
||||
unsigned int fence_flags;
|
||||
unsigned int rep_flags;
|
||||
unsigned int page_alignment;
|
||||
unsigned int desired_tile_stride;
|
||||
unsigned int hw_tile_stride;
|
||||
unsigned int tile_info;
|
||||
unsigned int pad64;
|
||||
uint64_t expand_pad[4]; /*Future expansion */
|
||||
};
|
||||
|
||||
struct drm_bo_arg_rep {
|
||||
struct drm_bo_info_rep bo_info;
|
||||
int ret;
|
||||
unsigned int pad64;
|
||||
};
|
||||
|
||||
struct drm_bo_create_arg {
|
||||
union {
|
||||
struct drm_bo_create_req req;
|
||||
struct drm_bo_info_rep rep;
|
||||
} d;
|
||||
};
|
||||
|
||||
struct drm_bo_handle_arg {
|
||||
unsigned int handle;
|
||||
};
|
||||
|
||||
struct drm_bo_reference_info_arg {
|
||||
union {
|
||||
struct drm_bo_handle_arg req;
|
||||
struct drm_bo_info_rep rep;
|
||||
} d;
|
||||
};
|
||||
|
||||
struct drm_bo_map_wait_idle_arg {
|
||||
union {
|
||||
struct drm_bo_info_req req;
|
||||
struct drm_bo_info_rep rep;
|
||||
} d;
|
||||
};
|
||||
|
||||
struct drm_bo_op_req {
|
||||
enum {
|
||||
drm_bo_validate,
|
||||
drm_bo_fence,
|
||||
drm_bo_ref_fence,
|
||||
} op;
|
||||
unsigned int arg_handle;
|
||||
struct drm_bo_info_req bo_req;
|
||||
};
|
||||
|
||||
|
||||
struct drm_bo_op_arg {
|
||||
uint64_t next;
|
||||
union {
|
||||
struct drm_bo_op_req req;
|
||||
struct drm_bo_arg_rep rep;
|
||||
} d;
|
||||
int handled;
|
||||
unsigned int pad64;
|
||||
};
|
||||
|
||||
|
||||
#define DRM_BO_MEM_LOCAL 0
|
||||
#define DRM_BO_MEM_TT 1
|
||||
#define DRM_BO_MEM_VRAM 2
|
||||
#define DRM_BO_MEM_PRIV0 3
|
||||
#define DRM_BO_MEM_PRIV1 4
|
||||
#define DRM_BO_MEM_PRIV2 5
|
||||
#define DRM_BO_MEM_PRIV3 6
|
||||
#define DRM_BO_MEM_PRIV4 7
|
||||
|
||||
#define DRM_BO_MEM_TYPES 8 /* For now. */
|
||||
|
||||
#define DRM_BO_LOCK_UNLOCK_BM (1 << 0)
|
||||
#define DRM_BO_LOCK_IGNORE_NO_EVICT (1 << 1)
|
||||
|
||||
struct drm_bo_version_arg {
|
||||
uint32_t major;
|
||||
uint32_t minor;
|
||||
uint32_t patchlevel;
|
||||
};
|
||||
|
||||
struct drm_mm_type_arg {
|
||||
unsigned int mem_type;
|
||||
unsigned int lock_flags;
|
||||
};
|
||||
|
||||
struct drm_mm_init_arg {
|
||||
unsigned int magic;
|
||||
unsigned int major;
|
||||
unsigned int minor;
|
||||
unsigned int mem_type;
|
||||
uint64_t p_offset;
|
||||
uint64_t p_size;
|
||||
};
|
||||
|
||||
struct drm_mm_info_arg {
|
||||
unsigned int mem_type;
|
||||
uint64_t p_size;
|
||||
};
|
||||
|
||||
/**
|
||||
* \name Ioctls Definitions
|
||||
*/
|
||||
|
|
@ -1027,31 +708,6 @@ struct drm_mm_info_arg {
|
|||
|
||||
#define DRM_IOCTL_UPDATE_DRAW DRM_IOW(0x3f, struct drm_update_draw)
|
||||
|
||||
#define DRM_IOCTL_MM_INIT DRM_IOWR(0xc0, struct drm_mm_init_arg)
|
||||
#define DRM_IOCTL_MM_TAKEDOWN DRM_IOWR(0xc1, struct drm_mm_type_arg)
|
||||
#define DRM_IOCTL_MM_LOCK DRM_IOWR(0xc2, struct drm_mm_type_arg)
|
||||
#define DRM_IOCTL_MM_UNLOCK DRM_IOWR(0xc3, struct drm_mm_type_arg)
|
||||
|
||||
#define DRM_IOCTL_FENCE_CREATE DRM_IOWR(0xc4, struct drm_fence_arg)
|
||||
#define DRM_IOCTL_FENCE_REFERENCE DRM_IOWR(0xc6, struct drm_fence_arg)
|
||||
#define DRM_IOCTL_FENCE_UNREFERENCE DRM_IOWR(0xc7, struct drm_fence_arg)
|
||||
#define DRM_IOCTL_FENCE_SIGNALED DRM_IOWR(0xc8, struct drm_fence_arg)
|
||||
#define DRM_IOCTL_FENCE_FLUSH DRM_IOWR(0xc9, struct drm_fence_arg)
|
||||
#define DRM_IOCTL_FENCE_WAIT DRM_IOWR(0xca, struct drm_fence_arg)
|
||||
#define DRM_IOCTL_FENCE_EMIT DRM_IOWR(0xcb, struct drm_fence_arg)
|
||||
#define DRM_IOCTL_FENCE_BUFFERS DRM_IOWR(0xcc, struct drm_fence_arg)
|
||||
|
||||
#define DRM_IOCTL_BO_CREATE DRM_IOWR(0xcd, struct drm_bo_create_arg)
|
||||
#define DRM_IOCTL_BO_MAP DRM_IOWR(0xcf, struct drm_bo_map_wait_idle_arg)
|
||||
#define DRM_IOCTL_BO_UNMAP DRM_IOWR(0xd0, struct drm_bo_handle_arg)
|
||||
#define DRM_IOCTL_BO_REFERENCE DRM_IOWR(0xd1, struct drm_bo_reference_info_arg)
|
||||
#define DRM_IOCTL_BO_UNREFERENCE DRM_IOWR(0xd2, struct drm_bo_handle_arg)
|
||||
#define DRM_IOCTL_BO_SETSTATUS DRM_IOWR(0xd3, struct drm_bo_map_wait_idle_arg)
|
||||
#define DRM_IOCTL_BO_INFO DRM_IOWR(0xd4, struct drm_bo_reference_info_arg)
|
||||
#define DRM_IOCTL_BO_WAIT_IDLE DRM_IOWR(0xd5, struct drm_bo_map_wait_idle_arg)
|
||||
#define DRM_IOCTL_BO_VERSION DRM_IOR(0xd6, struct drm_bo_version_arg)
|
||||
#define DRM_IOCTL_MM_INFO DRM_IOWR(0xd7, struct drm_mm_info_arg)
|
||||
|
||||
/*@}*/
|
||||
|
||||
/**
|
||||
|
|
@ -1107,10 +763,6 @@ typedef struct drm_agp_info drm_agp_info_t;
|
|||
typedef struct drm_scatter_gather drm_scatter_gather_t;
|
||||
typedef struct drm_set_version drm_set_version_t;
|
||||
|
||||
typedef struct drm_fence_arg drm_fence_arg_t;
|
||||
typedef struct drm_mm_type_arg drm_mm_type_arg_t;
|
||||
typedef struct drm_mm_init_arg drm_mm_init_arg_t;
|
||||
typedef enum drm_bo_type drm_bo_type_t;
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -138,14 +138,6 @@ typedef struct drm_i915_sarea {
|
|||
|
||||
/* Driver specific fence types and classes.
|
||||
*/
|
||||
|
||||
/* The only fence class we support */
|
||||
#define DRM_I915_FENCE_CLASS_ACCEL 0
|
||||
/* Fence type that guarantees read-write flush */
|
||||
#define DRM_I915_FENCE_TYPE_RW 2
|
||||
/* MI_FLUSH programmed just before the fence */
|
||||
#define DRM_I915_FENCE_FLAG_FLUSHED 0x01000000
|
||||
|
||||
/* Flags for perf_boxes
|
||||
*/
|
||||
#define I915_BOX_RING_EMPTY 0x1
|
||||
|
|
@ -175,7 +167,6 @@ typedef struct drm_i915_sarea {
|
|||
#define DRM_I915_VBLANK_SWAP 0x0f
|
||||
#define DRM_I915_MMIO 0x10
|
||||
#define DRM_I915_HWS_ADDR 0x11
|
||||
#define DRM_I915_EXECBUFFER 0x12
|
||||
|
||||
#define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
|
||||
#define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
|
||||
|
|
@ -194,7 +185,6 @@ typedef struct drm_i915_sarea {
|
|||
#define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
|
||||
#define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t)
|
||||
#define DRM_IOCTL_I915_MMIO DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_MMIO, drm_i915_mmio)
|
||||
#define DRM_IOCTL_I915_EXECBUFFER DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_EXECBUFFER, struct drm_i915_execbuffer)
|
||||
|
||||
/* Asynchronous page flipping:
|
||||
*/
|
||||
|
|
@ -343,56 +333,4 @@ typedef struct drm_i915_hws_addr {
|
|||
uint64_t addr;
|
||||
} drm_i915_hws_addr_t;
|
||||
|
||||
/*
|
||||
* Relocation header is 4 uint32_ts
|
||||
* 0 - 32 bit reloc count
|
||||
* 1 - 32-bit relocation type
|
||||
* 2-3 - 64-bit user buffer handle ptr for another list of relocs.
|
||||
*/
|
||||
#define I915_RELOC_HEADER 4
|
||||
|
||||
/*
|
||||
* type 0 relocation has 4-uint32_t stride
|
||||
* 0 - offset into buffer
|
||||
* 1 - delta to add in
|
||||
* 2 - buffer handle
|
||||
* 3 - reserved (for optimisations later).
|
||||
*/
|
||||
/*
|
||||
* type 1 relocation has 4-uint32_t stride.
|
||||
* Hangs off the first item in the op list.
|
||||
* Performed after all valiations are done.
|
||||
* Try to group relocs into the same relocatee together for
|
||||
* performance reasons.
|
||||
* 0 - offset into buffer
|
||||
* 1 - delta to add in
|
||||
* 2 - buffer index in op list.
|
||||
* 3 - relocatee index in op list.
|
||||
*/
|
||||
#define I915_RELOC_TYPE_0 0
|
||||
#define I915_RELOC0_STRIDE 4
|
||||
#define I915_RELOC_TYPE_1 1
|
||||
#define I915_RELOC1_STRIDE 4
|
||||
|
||||
|
||||
struct drm_i915_op_arg {
|
||||
uint64_t next;
|
||||
uint64_t reloc_ptr;
|
||||
int handled;
|
||||
unsigned int pad64;
|
||||
union {
|
||||
struct drm_bo_op_req req;
|
||||
struct drm_bo_arg_rep rep;
|
||||
} d;
|
||||
|
||||
};
|
||||
|
||||
struct drm_i915_execbuffer {
|
||||
uint64_t ops_list;
|
||||
uint32_t num_buffers;
|
||||
struct drm_i915_batchbuffer batch;
|
||||
drm_context_t context; /* for lockless use in the future */
|
||||
struct drm_fence_arg fence_arg;
|
||||
};
|
||||
|
||||
#endif /* _I915_DRM_H_ */
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue