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drm/nv50: fix nv9x chipsets

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NVIDIA do this fun little sequence after updating the PRAMIN page tables.

On 9xxx chips, none of the PRAMIN BAR bindings (except the initial one)
worked, hence the majority of the setup needed to create a channel
ended up in the wrong place, causing all sorts of fun.

This is done by NVIDIA on nv8x chips also, so we'll do it for them too,
even though they appear to work without it.
This commit is contained in:
Ben Skeggs 2009-02-11 10:48:36 +10:00
parent 7bbd605a21
commit bc92c0edf3
1 changed files with 7 additions and 0 deletions
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7
shared-core/nv50_instmem.c
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@ -297,6 +297,13 @@ nv50_instmem_bind(struct drm_device *dev, struct nouveau_gpuobj *gpuobj)
vram += NV50_INSTMEM_PAGE_SIZE;
}
NV_WRITE(0x070000, 0x00000001);
while(NV_READ(0x070000) & 1);
NV_WRITE(0x100c80, 0x00040001);
while(NV_READ(0x100c80) & 1);
NV_WRITE(0x100c80, 0x00060001);
while(NV_READ(0x100c80) & 1);
gpuobj->im_bound = 1;
return 0;
}