mirror of
https://gitlab.freedesktop.org/mesa/drm.git
synced 2025-12-24 18:20:11 +01:00
Updates from 3.5 branch
This commit is contained in:
Keith Whitwell
parent
ca7e845cc9
commit
a43cc303db
6 changed files with 434 additions and 65 deletions
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@ -41,6 +41,8 @@
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/* DMA customization:
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*/
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#define __HAVE_DMA 1
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#define __HAVE_AGP 1
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#define __MUST_HAVE_AGP 0
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#define __HAVE_OLD_DMA 1
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#define __HAVE_PCI_DMA 1
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@ -67,27 +69,55 @@
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#define __HAVE_DMA_IRQ 1
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#define __HAVE_DMA_IRQ_BH 1
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#if 1
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#define DRIVER_PREINSTALL() do { \
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drm_gamma_private_t *dev_priv = \
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(drm_gamma_private_t *)dev->dev_private;\
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GAMMA_WRITE( GAMMA_GCOMMANDMODE, 0x00000000 ); \
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while(GAMMA_READ(GAMMA_INFIFOSPACE) < 2); \
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GAMMA_WRITE( GAMMA_GCOMMANDMODE, 0x00000004 ); \
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GAMMA_WRITE( GAMMA_GDMACONTROL, 0x00000000 ); \
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} while (0)
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#define DRIVER_POSTINSTALL() do { \
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drm_gamma_private_t *dev_priv = \
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(drm_gamma_private_t *)dev->dev_private;\
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while(GAMMA_READ(GAMMA_INFIFOSPACE) < 2); \
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while(GAMMA_READ(GAMMA_INFIFOSPACE) < 3); \
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GAMMA_WRITE( GAMMA_GINTENABLE, 0x00002001 ); \
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GAMMA_WRITE( GAMMA_COMMANDINTENABLE, 0x00000008 ); \
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GAMMA_WRITE( GAMMA_GDELAYTIMER, 0x00039090 ); \
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} while (0)
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#else
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#define DRIVER_POSTINSTALL() do { \
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drm_gamma_private_t *dev_priv = \
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(drm_gamma_private_t *)dev->dev_private;\
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while(GAMMA_READ(GAMMA_INFIFOSPACE) < 2); \
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while(GAMMA_READ(GAMMA_INFIFOSPACE) < 2); \
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GAMMA_WRITE( GAMMA_GINTENABLE, 0x00002000 ); \
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GAMMA_WRITE( GAMMA_COMMANDINTENABLE, 0x00000004 ); \
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} while (0)
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#define DRIVER_PREINSTALL() do { \
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drm_gamma_private_t *dev_priv = \
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(drm_gamma_private_t *)dev->dev_private;\
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while(GAMMA_READ(GAMMA_INFIFOSPACE) < 2); \
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while(GAMMA_READ(GAMMA_INFIFOSPACE) < 2); \
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GAMMA_WRITE( GAMMA_GCOMMANDMODE, GAMMA_QUEUED_DMA_MODE );\
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GAMMA_WRITE( GAMMA_GDMACONTROL, 0x00000000 );\
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} while (0)
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#endif
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#define DRIVER_UNINSTALL() do { \
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drm_gamma_private_t *dev_priv = \
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(drm_gamma_private_t *)dev->dev_private;\
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while(GAMMA_READ(GAMMA_INFIFOSPACE) < 2); \
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while(GAMMA_READ(GAMMA_INFIFOSPACE) < 3); \
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GAMMA_WRITE( GAMMA_GDELAYTIMER, 0x00000000 ); \
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GAMMA_WRITE( GAMMA_COMMANDINTENABLE, 0x00000000 ); \
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GAMMA_WRITE( GAMMA_GINTENABLE, 0x00000000 ); \
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} while (0)
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#define DRIVER_AGP_BUFFERS_MAP( dev ) \
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((drm_gamma_private_t *)((dev)->dev_private))->buffers
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#endif /* __GAMMA_H__ */
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@ -37,28 +37,25 @@
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#include <linux/interrupt.h> /* For task queue support */
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#include <linux/delay.h>
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static inline void gamma_dma_dispatch(drm_device_t *dev, unsigned long address,
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unsigned long length)
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{
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drm_gamma_private_t *dev_priv =
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(drm_gamma_private_t *)dev->dev_private;
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GAMMA_WRITE(GAMMA_DMAADDRESS, virt_to_phys((void *)address));
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while (GAMMA_READ(GAMMA_GCOMMANDSTATUS) != 4)
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;
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(drm_gamma_private_t *)dev->dev_private;
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mb();
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while ( GAMMA_READ(GAMMA_INFIFOSPACE) < 2);
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GAMMA_WRITE(GAMMA_DMAADDRESS, address);
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while (GAMMA_READ(GAMMA_GCOMMANDSTATUS) != 4);
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GAMMA_WRITE(GAMMA_DMACOUNT, length / 4);
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}
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void gamma_dma_quiescent_single(drm_device_t *dev)
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{
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drm_gamma_private_t *dev_priv =
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(drm_gamma_private_t *)dev->dev_private;
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(drm_gamma_private_t *)dev->dev_private;
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while (GAMMA_READ(GAMMA_DMACOUNT));
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while (GAMMA_READ(GAMMA_DMACOUNT))
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;
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while (GAMMA_READ(GAMMA_INFIFOSPACE) < 3)
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;
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while (GAMMA_READ(GAMMA_INFIFOSPACE) < 2);
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GAMMA_WRITE(GAMMA_FILTERMODE, 1 << 10);
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GAMMA_WRITE(GAMMA_SYNC, 0);
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@ -72,56 +69,50 @@ void gamma_dma_quiescent_single(drm_device_t *dev)
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void gamma_dma_quiescent_dual(drm_device_t *dev)
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{
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drm_gamma_private_t *dev_priv =
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(drm_gamma_private_t *)dev->dev_private;
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(drm_gamma_private_t *)dev->dev_private;
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while (GAMMA_READ(GAMMA_DMACOUNT));
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while (GAMMA_READ(GAMMA_DMACOUNT))
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;
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while (GAMMA_READ(GAMMA_INFIFOSPACE) < 3)
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;
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while (GAMMA_READ(GAMMA_INFIFOSPACE) < 3);
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GAMMA_WRITE(GAMMA_BROADCASTMASK, 3);
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GAMMA_WRITE(GAMMA_FILTERMODE, 1 << 10);
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GAMMA_WRITE(GAMMA_SYNC, 0);
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/* Read from first MX */
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/* Read from first MX */
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do {
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while (!GAMMA_READ(GAMMA_OUTFIFOWORDS))
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;
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while (!GAMMA_READ(GAMMA_OUTFIFOWORDS));
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} while (GAMMA_READ(GAMMA_OUTPUTFIFO) != GAMMA_SYNC_TAG);
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/* Read from second MX */
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/* Read from second MX */
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do {
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while (!GAMMA_READ(GAMMA_OUTFIFOWORDS + 0x10000))
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;
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while (!GAMMA_READ(GAMMA_OUTFIFOWORDS + 0x10000));
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} while (GAMMA_READ(GAMMA_OUTPUTFIFO + 0x10000) != GAMMA_SYNC_TAG);
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}
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void gamma_dma_ready(drm_device_t *dev)
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{
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drm_gamma_private_t *dev_priv =
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(drm_gamma_private_t *)dev->dev_private;
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while (GAMMA_READ(GAMMA_DMACOUNT))
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;
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(drm_gamma_private_t *)dev->dev_private;
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while (GAMMA_READ(GAMMA_DMACOUNT));
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}
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static inline int gamma_dma_is_ready(drm_device_t *dev)
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{
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drm_gamma_private_t *dev_priv =
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(drm_gamma_private_t *)dev->dev_private;
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return !GAMMA_READ(GAMMA_DMACOUNT);
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(drm_gamma_private_t *)dev->dev_private;
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return(!GAMMA_READ(GAMMA_DMACOUNT));
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}
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void gamma_dma_service(int irq, void *device, struct pt_regs *regs)
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{
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drm_device_t *dev = (drm_device_t *)device;
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drm_device_dma_t *dma = dev->dma;
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drm_device_t *dev = (drm_device_t *)device;
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drm_device_dma_t *dma = dev->dma;
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drm_gamma_private_t *dev_priv =
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(drm_gamma_private_t *)dev->dev_private;
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(drm_gamma_private_t *)dev->dev_private;
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atomic_inc(&dev->counts[6]); /* _DRM_STAT_IRQ */
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while (GAMMA_READ(GAMMA_INFIFOSPACE) < 3);
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GAMMA_WRITE(GAMMA_GDELAYTIMER, 0xc350/2); /* 0x05S */
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GAMMA_WRITE(GAMMA_GCOMMANDINTFLAGS, 8);
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GAMMA_WRITE(GAMMA_GINTFLAGS, 0x2001);
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@ -165,7 +156,9 @@ static int gamma_do_dma(drm_device_t *dev, int locked)
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}
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buf = dma->next_buffer;
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address = (unsigned long)buf->address;
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/* WE NOW ARE ON LOGICAL PAGES!! - using page table setup in dma_init */
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/* So we pass the buffer index value into the physical page offset */
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address = buf->idx << 12;
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length = buf->used;
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DRM_DEBUG("context %d, buffer %d (%ld bytes)\n",
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@ -232,6 +225,9 @@ static int gamma_do_dma(drm_device_t *dev, int locked)
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buf->time_dispatched = get_cycles();
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#endif
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/* WE NOW ARE ON LOGICAL PAGES!!! - overriding address */
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address = buf->idx << 12;
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gamma_dma_dispatch(dev, address, length);
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gamma_free_buffer(dev, dma->this_buffer);
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dma->this_buffer = buf;
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@ -582,3 +578,255 @@ int gamma_dma(struct inode *inode, struct file *filp, unsigned int cmd,
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return retcode;
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}
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/* =============================================================
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* DMA initialization, cleanup
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*/
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static int gamma_do_init_dma( drm_device_t *dev, drm_gamma_init_t *init )
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{
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drm_gamma_private_t *dev_priv;
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drm_device_dma_t *dma = dev->dma;
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drm_buf_t *buf;
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int i;
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struct list_head *list;
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unsigned int *pgt;
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DRM_DEBUG( "%s\n", __FUNCTION__ );
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dev_priv = DRM(alloc)( sizeof(drm_gamma_private_t),
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DRM_MEM_DRIVER );
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if ( !dev_priv )
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return -ENOMEM;
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dev->dev_private = (void *)dev_priv;
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memset( dev_priv, 0, sizeof(drm_gamma_private_t) );
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list_for_each(list, &dev->maplist->head) {
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drm_map_list_t *r_list = (drm_map_list_t *)list;
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if( r_list->map &&
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r_list->map->type == _DRM_SHM &&
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r_list->map->flags & _DRM_CONTAINS_LOCK ) {
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dev_priv->sarea = r_list->map;
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break;
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}
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}
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DRM_FIND_MAP( dev_priv->mmio0, init->mmio0 );
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DRM_FIND_MAP( dev_priv->mmio1, init->mmio1 );
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DRM_FIND_MAP( dev_priv->mmio2, init->mmio2 );
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DRM_FIND_MAP( dev_priv->mmio3, init->mmio3 );
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dev_priv->sarea_priv = (drm_gamma_sarea_t *)
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((u8 *)dev_priv->sarea->handle +
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init->sarea_priv_offset);
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if (init->pcimode) {
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buf = dma->buflist[GLINT_DRI_BUF_COUNT];
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pgt = buf->address;
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for (i = 0; i < GLINT_DRI_BUF_COUNT; i++) {
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buf = dma->buflist[i];
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*pgt = virt_to_phys((void*)buf->address) | 0x07;
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pgt++;
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}
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buf = dma->buflist[GLINT_DRI_BUF_COUNT];
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} else {
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DRM_FIND_MAP( dev_priv->buffers, init->buffers_offset );
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DRM_IOREMAP( dev_priv->buffers );
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buf = dma->buflist[GLINT_DRI_BUF_COUNT];
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pgt = buf->address;
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for (i = 0; i < GLINT_DRI_BUF_COUNT; i++) {
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buf = dma->buflist[i];
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*pgt = (unsigned int)buf->address + 0x07;
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pgt++;
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}
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buf = dma->buflist[GLINT_DRI_BUF_COUNT];
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while (GAMMA_READ(GAMMA_INFIFOSPACE) < 1);
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GAMMA_WRITE( GAMMA_GDMACONTROL, 0xe);
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}
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while (GAMMA_READ(GAMMA_INFIFOSPACE) < 2);
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GAMMA_WRITE( GAMMA_PAGETABLEADDR, virt_to_phys((void*)buf->address) );
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GAMMA_WRITE( GAMMA_PAGETABLELENGTH, 2 );
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return 0;
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}
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int gamma_do_cleanup_dma( drm_device_t *dev )
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{
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DRM_DEBUG( "%s\n", __FUNCTION__ );
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if ( dev->dev_private ) {
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drm_gamma_private_t *dev_priv = dev->dev_private;
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DRM_IOREMAPFREE( dev_priv->buffers );
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DRM(free)( dev->dev_private, sizeof(drm_gamma_private_t),
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DRM_MEM_DRIVER );
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dev->dev_private = NULL;
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}
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return 0;
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}
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int gamma_dma_init( struct inode *inode, struct file *filp,
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unsigned int cmd, unsigned long arg )
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{
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drm_file_t *priv = filp->private_data;
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drm_device_t *dev = priv->dev;
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drm_gamma_init_t init;
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if ( copy_from_user( &init, (drm_gamma_init_t *)arg, sizeof(init) ) )
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return -EFAULT;
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switch ( init.func ) {
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case GAMMA_INIT_DMA:
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return gamma_do_init_dma( dev, &init );
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case GAMMA_CLEANUP_DMA:
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return gamma_do_cleanup_dma( dev );
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}
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return -EINVAL;
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}
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static int gamma_do_copy_dma( drm_device_t *dev, drm_gamma_copy_t *copy )
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{
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drm_device_dma_t *dma = dev->dma;
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unsigned int *screenbuf;
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DRM_DEBUG( "%s\n", __FUNCTION__ );
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/* We've DRM_RESTRICTED this DMA buffer */
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screenbuf = dma->buflist[ GLINT_DRI_BUF_COUNT + 1 ]->address;
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#if 0
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*buffer++ = 0x180; /* Tag (FilterMode) */
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*buffer++ = 0x200; /* Allow FBColor through */
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*buffer++ = 0x53B; /* Tag */
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*buffer++ = copy->Pitch;
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*buffer++ = 0x53A; /* Tag */
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*buffer++ = copy->SrcAddress;
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*buffer++ = 0x539; /* Tag */
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*buffer++ = copy->WidthHeight; /* Initiates transfer */
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*buffer++ = 0x53C; /* Tag - DMAOutputAddress */
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*buffer++ = virt_to_phys((void*)screenbuf);
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*buffer++ = 0x53D; /* Tag - DMAOutputCount */
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*buffer++ = copy->Count; /* Reads HostOutFifo BLOCKS until ..*/
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/* Data now sitting in dma->buflist[ GLINT_DRI_BUF_COUNT + 1 ] */
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/* Now put it back to the screen */
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*buffer++ = 0x180; /* Tag (FilterMode) */
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*buffer++ = 0x400; /* Allow Sync through */
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*buffer++ = 0x538; /* Tag - DMARectangleReadTarget */
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*buffer++ = 0x155; /* FBSourceData | count */
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*buffer++ = 0x537; /* Tag */
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*buffer++ = copy->Pitch;
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*buffer++ = 0x536; /* Tag */
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*buffer++ = copy->DstAddress;
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*buffer++ = 0x535; /* Tag */
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*buffer++ = copy->WidthHeight; /* Initiates transfer */
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*buffer++ = 0x530; /* Tag - DMAAddr */
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*buffer++ = virt_to_phys((void*)screenbuf);
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*buffer++ = 0x531;
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*buffer++ = copy->Count; /* initiates DMA transfer of color data */
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#endif
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/* need to dispatch it now */
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return 0;
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}
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int gamma_dma_copy( struct inode *inode, struct file *filp,
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unsigned int cmd, unsigned long arg )
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{
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drm_file_t *priv = filp->private_data;
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drm_device_t *dev = priv->dev;
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drm_gamma_copy_t copy;
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if ( copy_from_user( ©, (drm_gamma_copy_t *)arg, sizeof(copy) ) )
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return -EFAULT;
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return gamma_do_copy_dma( dev, © );
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}
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/* =============================================================
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* Per Context SAREA Support
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*/
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int gamma_getsareactx(struct inode *inode, struct file *filp,
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unsigned int cmd, unsigned long arg)
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{
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drm_file_t *priv = filp->private_data;
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drm_device_t *dev = priv->dev;
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drm_ctx_priv_map_t request;
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drm_map_t *map;
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if (copy_from_user(&request,
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(drm_ctx_priv_map_t *)arg,
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sizeof(request)))
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return -EFAULT;
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down(&dev->struct_sem);
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if ((int)request.ctx_id >= dev->max_context) {
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up(&dev->struct_sem);
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return -EINVAL;
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}
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map = dev->context_sareas[request.ctx_id];
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up(&dev->struct_sem);
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request.handle = map->handle;
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if (copy_to_user((drm_ctx_priv_map_t *)arg, &request, sizeof(request)))
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return -EFAULT;
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return 0;
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}
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int gamma_setsareactx(struct inode *inode, struct file *filp,
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unsigned int cmd, unsigned long arg)
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{
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drm_file_t *priv = filp->private_data;
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drm_device_t *dev = priv->dev;
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drm_ctx_priv_map_t request;
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drm_map_t *map = NULL;
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drm_map_list_t *r_list;
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struct list_head *list;
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if (copy_from_user(&request,
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(drm_ctx_priv_map_t *)arg,
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sizeof(request)))
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return -EFAULT;
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down(&dev->struct_sem);
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r_list = NULL;
|
||||
list_for_each(list, &dev->maplist->head) {
|
||||
r_list = (drm_map_list_t *)list;
|
||||
if(r_list->map &&
|
||||
r_list->map->handle == request.handle) break;
|
||||
}
|
||||
if (list == &(dev->maplist->head)) {
|
||||
up(&dev->struct_sem);
|
||||
return -EINVAL;
|
||||
}
|
||||
map = r_list->map;
|
||||
up(&dev->struct_sem);
|
||||
|
||||
if (!map) return -EINVAL;
|
||||
|
||||
down(&dev->struct_sem);
|
||||
if ((int)request.ctx_id >= dev->max_context) {
|
||||
up(&dev->struct_sem);
|
||||
return -EINVAL;
|
||||
}
|
||||
dev->context_sareas[request.ctx_id] = map;
|
||||
up(&dev->struct_sem);
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
79
linux/gamma_drm.h
Normal file
79
linux/gamma_drm.h
Normal file
|
|
@ -0,0 +1,79 @@
|
|||
#ifndef _GAMMA_DRM_H_
|
||||
#define _GAMMA_DRM_H_
|
||||
|
||||
typedef struct _drm_gamma_tex_region {
|
||||
unsigned char next, prev; /* indices to form a circular LRU */
|
||||
unsigned char in_use; /* owned by a client, or free? */
|
||||
int age; /* tracked by clients to update local LRU's */
|
||||
} drm_gamma_tex_region_t;
|
||||
|
||||
typedef struct {
|
||||
unsigned int GDeltaMode;
|
||||
unsigned int GDepthMode;
|
||||
unsigned int GGeometryMode;
|
||||
unsigned int GTransformMode;
|
||||
} drm_gamma_context_regs_t;
|
||||
|
||||
typedef struct _drm_gamma_sarea {
|
||||
drm_gamma_context_regs_t context_state;
|
||||
|
||||
unsigned int dirty;
|
||||
|
||||
|
||||
/* Maintain an LRU of contiguous regions of texture space. If
|
||||
* you think you own a region of texture memory, and it has an
|
||||
* age different to the one you set, then you are mistaken and
|
||||
* it has been stolen by another client. If global texAge
|
||||
* hasn't changed, there is no need to walk the list.
|
||||
*
|
||||
* These regions can be used as a proxy for the fine-grained
|
||||
* texture information of other clients - by maintaining them
|
||||
* in the same lru which is used to age their own textures,
|
||||
* clients have an approximate lru for the whole of global
|
||||
* texture space, and can make informed decisions as to which
|
||||
* areas to kick out. There is no need to choose whether to
|
||||
* kick out your own texture or someone else's - simply eject
|
||||
* them all in LRU order.
|
||||
*/
|
||||
|
||||
#define GAMMA_NR_TEX_REGIONS 64
|
||||
drm_gamma_tex_region_t texList[GAMMA_NR_TEX_REGIONS+1];
|
||||
/* Last elt is sentinal */
|
||||
int texAge; /* last time texture was uploaded */
|
||||
int last_enqueue; /* last time a buffer was enqueued */
|
||||
int last_dispatch; /* age of the most recently dispatched buffer */
|
||||
int last_quiescent; /* */
|
||||
int ctxOwner; /* last context to upload state */
|
||||
|
||||
int vertex_prim;
|
||||
} drm_gamma_sarea_t;
|
||||
|
||||
typedef struct drm_gamma_copy {
|
||||
unsigned int DMAOutputAddress;
|
||||
unsigned int DMAOutputCount;
|
||||
unsigned int DMAReadGLINTSource;
|
||||
unsigned int DMARectangleWriteAddress;
|
||||
unsigned int DMARectangleWriteLinePitch;
|
||||
unsigned int DMARectangleWrite;
|
||||
unsigned int DMARectangleReadAddress;
|
||||
unsigned int DMARectangleReadLinePitch;
|
||||
unsigned int DMARectangleRead;
|
||||
unsigned int DMARectangleReadTarget;
|
||||
} drm_gamma_copy_t;
|
||||
|
||||
typedef struct drm_gamma_init {
|
||||
enum {
|
||||
GAMMA_INIT_DMA = 0x01,
|
||||
GAMMA_CLEANUP_DMA = 0x02
|
||||
} func;
|
||||
|
||||
int sarea_priv_offset;
|
||||
int pcimode;
|
||||
unsigned int mmio0;
|
||||
unsigned int mmio1;
|
||||
unsigned int mmio2;
|
||||
unsigned int mmio3;
|
||||
unsigned int buffers_offset;
|
||||
} drm_gamma_init_t;
|
||||
|
||||
#endif /* _GAMMA_DRM_H_ */
|
||||
|
|
@ -38,15 +38,19 @@
|
|||
|
||||
#define DRIVER_NAME "gamma"
|
||||
#define DRIVER_DESC "3DLabs gamma"
|
||||
#define DRIVER_DATE "20010216"
|
||||
#define DRIVER_DATE "20010624"
|
||||
|
||||
#define DRIVER_MAJOR 1
|
||||
#define DRIVER_MAJOR 2
|
||||
#define DRIVER_MINOR 0
|
||||
#define DRIVER_PATCHLEVEL 0
|
||||
|
||||
#define DRIVER_IOCTLS \
|
||||
[DRM_IOCTL_NR(DRM_IOCTL_DMA)] = { gamma_dma, 1, 0 }
|
||||
[DRM_IOCTL_NR(DRM_IOCTL_DMA)] = { gamma_dma, 1, 0 }, \
|
||||
[DRM_IOCTL_NR(DRM_IOCTL_GAMMA_INIT)] = { gamma_dma_init, 1, 1 }, \
|
||||
[DRM_IOCTL_NR(DRM_IOCTL_GAMMA_COPY)] = { gamma_dma_copy, 1, 1 }
|
||||
|
||||
#define IOCTL_TABLE_NAME DRM(ioctls)
|
||||
#define IOCTL_FUNC_NAME DRM(ioctl)
|
||||
|
||||
#define __HAVE_COUNTERS 5
|
||||
#define __HAVE_COUNTER6 _DRM_STAT_IRQ
|
||||
|
|
@ -57,10 +61,12 @@
|
|||
|
||||
|
||||
#include "drm_auth.h"
|
||||
#include "drm_agpsupport.h"
|
||||
#include "drm_bufs.h"
|
||||
#include "drm_context.h"
|
||||
#include "drm_dma.h"
|
||||
#include "drm_drawable.h"
|
||||
#include "drm_ioctl_table.h"
|
||||
#include "drm_drv.h"
|
||||
|
||||
#ifndef MODULE
|
||||
|
|
@ -82,7 +88,6 @@ static int __init gamma_options( char *str )
|
|||
__setup( DRIVER_NAME "=", gamma_options );
|
||||
#endif
|
||||
|
||||
|
||||
#include "drm_fops.h"
|
||||
#include "drm_init.h"
|
||||
#include "drm_ioctl.h"
|
||||
|
|
|
|||
|
|
@ -32,8 +32,9 @@
|
|||
#ifndef _GAMMA_DRV_H_
|
||||
#define _GAMMA_DRV_H_
|
||||
|
||||
|
||||
typedef struct drm_gamma_private {
|
||||
drm_gamma_sarea_t *sarea_priv;
|
||||
drm_map_t *sarea;
|
||||
drm_map_t *buffers;
|
||||
drm_map_t *mmio0;
|
||||
drm_map_t *mmio1;
|
||||
|
|
@ -51,6 +52,11 @@ do { \
|
|||
} \
|
||||
} while (0)
|
||||
|
||||
/* gamma_dma.c */
|
||||
extern int gamma_dma_init( struct inode *inode, struct file *filp,
|
||||
unsigned int cmd, unsigned long arg );
|
||||
extern int gamma_dma_copy( struct inode *inode, struct file *filp,
|
||||
unsigned int cmd, unsigned long arg );
|
||||
|
||||
extern void gamma_dma_ready(drm_device_t *dev);
|
||||
extern void gamma_dma_quiescent_single(drm_device_t *dev);
|
||||
|
|
@ -63,6 +69,7 @@ extern int gamma_dma(struct inode *inode, struct file *filp,
|
|||
extern int gamma_find_devices(void);
|
||||
extern int gamma_found(void);
|
||||
|
||||
#define GLINT_DRI_BUF_COUNT 256
|
||||
|
||||
#define GAMMA_OFF(reg) \
|
||||
((reg < 0x1000) \
|
||||
|
|
@ -78,7 +85,6 @@ extern int gamma_found(void);
|
|||
((reg < 0x10000) ? dev_priv->mmio1->handle : \
|
||||
((reg < 0x11000) ? dev_priv->mmio2->handle : \
|
||||
dev_priv->mmio3->handle))))
|
||||
|
||||
#define GAMMA_ADDR(reg) (GAMMA_BASE(reg) + GAMMA_OFF(reg))
|
||||
#define GAMMA_DEREF(reg) *(__volatile__ int *)GAMMA_ADDR(reg)
|
||||
#define GAMMA_READ(reg) GAMMA_DEREF(reg)
|
||||
|
|
@ -91,9 +97,11 @@ extern int gamma_found(void);
|
|||
#define GAMMA_FILTERMODE 0x8c00
|
||||
#define GAMMA_GCOMMANDINTFLAGS 0x0c50
|
||||
#define GAMMA_GCOMMANDMODE 0x0c40
|
||||
#define GAMMA_QUEUED_DMA_MODE 1<<1
|
||||
#define GAMMA_GCOMMANDSTATUS 0x0c60
|
||||
#define GAMMA_GDELAYTIMER 0x0c38
|
||||
#define GAMMA_GDMACONTROL 0x0060
|
||||
#define GAMMA_USE_AGP 1<<1
|
||||
#define GAMMA_GINTENABLE 0x0808
|
||||
#define GAMMA_GINTFLAGS 0x0810
|
||||
#define GAMMA_INFIFOSPACE 0x0018
|
||||
|
|
@ -101,5 +109,12 @@ extern int gamma_found(void);
|
|||
#define GAMMA_OUTPUTFIFO 0x2000
|
||||
#define GAMMA_SYNC 0x8c40
|
||||
#define GAMMA_SYNC_TAG 0x0188
|
||||
#define GAMMA_PAGETABLEADDR 0x0C00
|
||||
#define GAMMA_PAGETABLELENGTH 0x0C08
|
||||
|
||||
#define GAMMA_PASSTHROUGH 0x1FE
|
||||
#define GAMMA_DMAADDRTAG 0x530
|
||||
#define GAMMA_DMACOUNTTAG 0x531
|
||||
#define GAMMA_COMMANDINTTAG 0x532
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -153,28 +153,24 @@ typedef struct {
|
|||
/* Setup state */
|
||||
unsigned int se_cntl_status; /* 0x2140 */
|
||||
|
||||
#ifdef TCL_ENABLE
|
||||
/* TCL state */
|
||||
radeon_color_regs_t se_tcl_material_emmissive; /* 0x2210 */
|
||||
radeon_color_regs_t se_tcl_material_ambient;
|
||||
radeon_color_regs_t se_tcl_material_diffuse;
|
||||
radeon_color_regs_t se_tcl_material_specular;
|
||||
unsigned int se_tcl_shininess;
|
||||
unsigned int se_tcl_output_vtx_fmt;
|
||||
unsigned int se_tcl_output_vtx_sel;
|
||||
unsigned int se_tcl_matrix_select_0;
|
||||
unsigned int se_tcl_matrix_select_1;
|
||||
unsigned int se_tcl_ucp_vert_blend_ctl;
|
||||
unsigned int se_tcl_texture_proc_ctl;
|
||||
unsigned int se_tcl_light_model_ctl;
|
||||
unsigned int se_tcl_per_light_ctl[4];
|
||||
#endif
|
||||
|
||||
/* Misc state */
|
||||
unsigned int re_top_left; /* 0x26c0 */
|
||||
unsigned int re_misc;
|
||||
} drm_radeon_context_regs_t;
|
||||
|
||||
|
||||
/* Space is crucial; there is some redunancy here:
|
||||
*/
|
||||
typedef struct {
|
||||
unsigned int start;
|
||||
unsigned int finish;
|
||||
unsigned int prim:8;
|
||||
unsigned int stateidx:8;
|
||||
unsigned int numverts:16; /* overloaded as offset/64 for elt prims */
|
||||
unsigned int vc_format; /* vertex format */
|
||||
} drm_radeon_prim_t;
|
||||
|
||||
|
||||
/* Setup registers for each texture unit
|
||||
*/
|
||||
typedef struct {
|
||||
|
|
@ -187,10 +183,6 @@ typedef struct {
|
|||
|
||||
unsigned int pp_border_color;
|
||||
|
||||
#ifdef CUBIC_ENABLE
|
||||
unsigned int pp_cubic_faces;
|
||||
unsigned int pp_cubic_offset[5];
|
||||
#endif
|
||||
} drm_radeon_texture_regs_t;
|
||||
|
||||
typedef struct {
|
||||
|
|
@ -295,11 +287,11 @@ typedef struct drm_radeon_vertex {
|
|||
int discard; /* Client finished with buffer? */
|
||||
} drm_radeon_vertex_t;
|
||||
|
||||
typedef struct drm_radeon_vertex {
|
||||
typedef struct drm_radeon_vertex2 {
|
||||
int idx; /* Index of vertex buffer */
|
||||
int discard; /* Client finished with buffer? */
|
||||
int nr_states;
|
||||
drm_radeon_state_t *state;
|
||||
drm_radeon_context_regs_t *state;
|
||||
int nr_prims;
|
||||
drm_radeon_prim_t *prim;
|
||||
} drm_radeon_vertex2_t;
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue