mirror of
https://gitlab.freedesktop.org/mesa/drm.git
synced 2025-12-31 14:50:14 +01:00
Converted all the radeon specific drm calls to drmCommand interface for 2D
driver. 3D driver is not converted, yet...I don't expect a full build
to work at this point.
This commit is contained in:
Jens Owen
parent
ed7b270ac3
commit
a0effcf496
2 changed files with 334 additions and 15 deletions
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@ -1410,41 +1410,53 @@ int drmRemoveSIGIOHandler(int fd)
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int drmCommandNone(int fd, unsigned long drmCommandIndex)
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{
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void *data = NULL; /* dummy */
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unsigned long request;
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void *data = NULL; /* dummy */
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unsigned long request;
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request = DRM_IO( DRM_COMMAND_BASE + drmCommandIndex);
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request = DRM_IO( DRM_COMMAND_BASE + drmCommandIndex);
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return ioctl(fd, request, data);
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if (ioctl(fd, request, data)) {
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return -errno;
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}
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return 0;
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}
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int drmCommandRead(int fd, unsigned long drmCommandIndex,
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void *data, unsigned long size )
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{
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unsigned long request;
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unsigned long request;
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request = DRM_IOR( DRM_COMMAND_BASE + drmCommandIndex, size);
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request = DRM_IOR( DRM_COMMAND_BASE + drmCommandIndex, size);
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return ioctl(fd, request, data);
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if (ioctl(fd, request, data)) {
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return -errno;
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}
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return 0;
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}
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int drmCommandWrite(int fd, unsigned long drmCommandIndex,
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void *data, unsigned long size )
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{
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unsigned long request;
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unsigned long request;
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request = DRM_IOW( DRM_COMMAND_BASE + drmCommandIndex, size);
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request = DRM_IOW( DRM_COMMAND_BASE + drmCommandIndex, size);
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return ioctl(fd, request, data);
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if (ioctl(fd, request, data)) {
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return -errno;
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}
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return 0;
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}
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int drmCommandWriteRead(int fd, unsigned long drmCommandIndex,
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void *data, unsigned long size )
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{
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unsigned long request;
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unsigned long request;
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request = DRM_IOWR( DRM_COMMAND_BASE + drmCommandIndex, size);
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request = DRM_IOWR( DRM_COMMAND_BASE + drmCommandIndex, size);
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return ioctl(fd, request, data);
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if (ioctl(fd, request, data)) {
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return -errno;
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}
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return 0;
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}
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#endif
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@ -81,10 +81,58 @@ extern int xf86RemoveSIGIOHandler(int fd);
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/* WARNING: Do not change, or add, anything to this file. It is only provided
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* for backwards compatability with the old driver specific DRM extensions
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* found in XFree86 4.0, 4.1 and 4.2.
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* for binary backwards compatability with the old driver specific DRM
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* extensions used before XFree86 4.3.
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*/
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/* I810 */
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/*
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drmI810CleanupDma
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drmI810InitDma
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*/
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/* Mga */
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/*
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drmMGAAgpBlit
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drmMGACleanupDMA
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drmMGAClear
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drmMGAEngineReset
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drmMGAFlushDMA
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drmMGAFlushIndices
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drmMGAFlushVertexBuffer
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drmMGAFullScreen
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drmMGAInitDMA
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drmMGASwapBuffers
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drmMGATextureLoad
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*/
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/* R128 */
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/*
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drmR128CleanupCCE
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drmR128Clear
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drmR128EngineReset
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drmR128FlushIndices
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drmR128FlushIndirectBuffer
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drmR128FlushVertexBuffer
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drmR128FullScreen
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drmR128InitCCE
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drmR128PolygonStipple
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drmR128ReadDepthPixels
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drmR128ReadDepthSpan
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drmR128ResetCCE
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drmR128StartCCE
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drmR128StopCCE
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drmR128SwapBuffers
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drmR128TextureBlit
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drmR128WaitForIdleCCE
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drmR128WriteDepthPixels
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drmR128WriteDepthSpan
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*/
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/* Radeon */
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#define RADEON_BUFFER_RETRY 32
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#define RADEON_IDLE_RETRY 16
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int drmRadeonInitCP( int fd, drmCompatRadeonInit *info )
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{
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@ -124,3 +172,262 @@ int drmRadeonInitCP( int fd, drmCompatRadeonInit *info )
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}
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}
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int drmRadeonCleanupCP( int fd )
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{
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drm_radeon_init_t init;
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memset( &init, 0, sizeof(drm_radeon_init_t) );
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init.func = RADEON_CLEANUP_CP;
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if ( ioctl( fd, DRM_IOCTL_RADEON_CP_INIT, &init ) ) {
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return -errno;
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} else {
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return 0;
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}
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}
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int drmRadeonStartCP( int fd )
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{
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if ( ioctl( fd, DRM_IOCTL_RADEON_CP_START, NULL ) ) {
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return -errno;
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} else {
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return 0;
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}
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}
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int drmRadeonStopCP( int fd )
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{
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drm_radeon_cp_stop_t stop;
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int ret, i = 0;
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stop.flush = 1;
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stop.idle = 1;
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ret = ioctl( fd, DRM_IOCTL_RADEON_CP_STOP, &stop );
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if ( ret == 0 ) {
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return 0;
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} else if ( errno != EBUSY ) {
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return -errno;
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}
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stop.flush = 0;
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do {
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ret = ioctl( fd, DRM_IOCTL_RADEON_CP_STOP, &stop );
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} while ( ret && errno == EBUSY && i++ < RADEON_IDLE_RETRY );
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if ( ret == 0 ) {
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return 0;
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} else if ( errno != EBUSY ) {
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return -errno;
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}
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stop.idle = 0;
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if ( ioctl( fd, DRM_IOCTL_RADEON_CP_STOP, &stop ) ) {
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return -errno;
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} else {
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return 0;
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}
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}
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int drmRadeonResetCP( int fd )
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{
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if ( ioctl( fd, DRM_IOCTL_RADEON_CP_RESET, NULL ) ) {
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return -errno;
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} else {
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return 0;
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}
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}
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int drmRadeonWaitForIdleCP( int fd )
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{
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int ret, i = 0;
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do {
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ret = ioctl( fd, DRM_IOCTL_RADEON_CP_IDLE, NULL );
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} while ( ret && errno == EBUSY && i++ < RADEON_IDLE_RETRY );
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if ( ret == 0 ) {
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return 0;
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} else {
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return -errno;
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}
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}
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int drmRadeonEngineReset( int fd )
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{
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if ( ioctl( fd, DRM_IOCTL_RADEON_RESET, NULL ) ) {
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return -errno;
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} else {
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return 0;
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}
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}
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int drmRadeonFullScreen( int fd, int enable )
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{
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drm_radeon_fullscreen_t fs;
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if ( enable ) {
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fs.func = RADEON_INIT_FULLSCREEN;
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} else {
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fs.func = RADEON_CLEANUP_FULLSCREEN;
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}
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if ( ioctl( fd, DRM_IOCTL_RADEON_FULLSCREEN, &fs ) ) {
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return -errno;
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} else {
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return 0;
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}
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}
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int drmRadeonSwapBuffers( int fd )
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{
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if ( ioctl( fd, DRM_IOCTL_RADEON_SWAP, NULL ) ) {
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return -errno;
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} else {
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return 0;
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}
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}
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int drmRadeonClear( int fd, unsigned int flags,
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unsigned int clear_color, unsigned int clear_depth,
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unsigned int color_mask, unsigned int stencil,
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void *b, int nbox )
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{
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drm_radeon_clear_t clear;
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drm_radeon_clear_rect_t depth_boxes[RADEON_NR_SAREA_CLIPRECTS];
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drm_clip_rect_t *boxes = (drm_clip_rect_t *)b;
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int i;
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clear.flags = flags;
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clear.clear_color = clear_color;
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clear.clear_depth = clear_depth;
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clear.color_mask = color_mask;
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clear.depth_mask = stencil; /* misnamed field in ioctl */
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clear.depth_boxes = depth_boxes;
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/* We can remove this when we do real depth clears, instead of
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* rendering a rectangle into the depth buffer. This prevents
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* floating point calculations being done in the kernel.
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*/
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for ( i = 0 ; i < nbox ; i++ ) {
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depth_boxes[i].f[CLEAR_X1] = (float)boxes[i].x1;
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depth_boxes[i].f[CLEAR_Y1] = (float)boxes[i].y1;
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depth_boxes[i].f[CLEAR_X2] = (float)boxes[i].x2;
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depth_boxes[i].f[CLEAR_Y2] = (float)boxes[i].y2;
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depth_boxes[i].f[CLEAR_DEPTH] = (float)clear_depth;
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}
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if ( ioctl( fd, DRM_IOCTL_RADEON_CLEAR, &clear ) < 0 ) {
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return -errno;
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} else {
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return 0;
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}
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}
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int drmRadeonFlushVertexBuffer( int fd, int prim, int index,
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int count, int discard )
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{
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drm_radeon_vertex_t v;
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v.prim = prim;
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v.idx = index;
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v.count = count;
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v.discard = discard;
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if ( ioctl( fd, DRM_IOCTL_RADEON_VERTEX, &v ) < 0 ) {
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return -errno;
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} else {
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return 0;
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}
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}
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int drmRadeonFlushIndices( int fd, int prim, int index,
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int start, int end, int discard )
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{
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drm_radeon_indices_t elts;
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elts.prim = prim;
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elts.idx = index;
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elts.start = start;
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elts.end = end;
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elts.discard = discard;
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if ( ioctl( fd, DRM_IOCTL_RADEON_INDICES, &elts ) < 0 ) {
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return -errno;
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} else {
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return 0;
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}
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}
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int drmRadeonLoadTexture( int fd, int offset, int pitch, int format, int width,
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int height, drmCompatRadeonTexImage *image )
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{
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drm_radeon_texture_t tex;
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drm_radeon_tex_image_t tmp;
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int ret;
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tex.offset = offset;
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tex.pitch = pitch;
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tex.format = format;
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tex.width = width;
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tex.height = height;
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tex.image = &tmp;
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/* This gets updated by the kernel when a multipass blit is needed.
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*/
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memcpy( &tmp, image, sizeof(drm_radeon_tex_image_t) );
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do {
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ret = ioctl( fd, DRM_IOCTL_RADEON_TEXTURE, &tex );
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} while ( ret && errno == EAGAIN );
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if ( ret == 0 ) {
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return 0;
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} else {
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return -errno;
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}
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}
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int drmRadeonPolygonStipple( int fd, unsigned int *mask )
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{
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drm_radeon_stipple_t stipple;
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stipple.mask = mask;
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if ( ioctl( fd, DRM_IOCTL_RADEON_STIPPLE, &stipple ) < 0 ) {
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return -errno;
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} else {
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return 0;
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}
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}
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int drmRadeonFlushIndirectBuffer( int fd, int index,
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int start, int end, int discard )
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{
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drm_radeon_indirect_t ind;
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ind.idx = index;
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ind.start = start;
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ind.end = end;
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ind.discard = discard;
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if ( ioctl( fd, DRM_IOCTL_RADEON_INDIRECT, &ind ) < 0 ) {
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return -errno;
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} else {
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return 0;
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}
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}
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/* SiS */
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/*
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drmSiSAgpInit
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*/
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/* WARNING: Do not change, or add, anything to this file. It is only provided
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* for binary backwards compatability with the old driver specific DRM
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* extensions used before XFree86 4.3.
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*/
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