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intel: add a comment about tiled buffer alloc height alignment from Mesa.

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This commit is contained in:
Eric Anholt 2010-03-02 15:05:30 -08:00
parent cdc788d645
commit a0abb1b14e
1 changed files with 11 additions and 0 deletions
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11
intel/intel_bufmgr_gem.c
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@ -680,6 +680,17 @@ drm_intel_gem_bo_alloc_tiled(drm_intel_bufmgr *bufmgr, const char *name,
unsigned long size, stride, aligned_y = y;
int ret;
/* If we're tiled, our allocations are in 8 or 32-row blocks,
* so failure to align our height means that we won't allocate
* enough pages.
*
* If we're untiled, we still have to align to 2 rows high
* because the data port accesses 2x2 blocks even if the
* bottom row isn't to be rendered, so failure to align means
* we could walk off the end of the GTT and fault. This is
* documented on 965, and may be the case on older chipsets
* too so we try to be careful.
*/
if (*tiling_mode == I915_TILING_NONE)
aligned_y = ALIGN(y, 2);
else if (*tiling_mode == I915_TILING_X)