fdo-mirrors/mesa-drm
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/drm.git synced 2025-12-20 07:00:11 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions

Update from trunk.

Browse source
This commit is contained in:
Eric Anholt 2002-07-04 23:04:27 +00:00
parent 6df32b3a51
commit 9a0d90c74e
2 changed files with 34 additions and 26 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

30
shared-core/radeon_state.c
View file

@ -46,10 +46,11 @@ static __inline__ void radeon_emit_clip_rect( drm_radeon_private_t *dev_priv,
DRM_DEBUG( " box: x1=%d y1=%d x2=%d y2=%d\n", DRM_DEBUG( " box: x1=%d y1=%d x2=%d y2=%d\n",
box->x1, box->y1, box->x2, box->y2 ); box->x1, box->y1, box->x2, box->y2 );
BEGIN_RING( 3 ); BEGIN_RING( 4 );
OUT_RING( CP_PACKET3( RADEON_CNTL_SET_SCISSORS, 1 )); OUT_RING( CP_PACKET0( RADEON_RE_TOP_LEFT, 0 ) );
OUT_RING( (box->y1 << 16) | box->x1 ); OUT_RING( (box->y1 << 16) | box->x1 );
/* OUT_RING( ((box->y2 - 1) << 16) | (box->x2 - 1) );*/ OUT_RING( CP_PACKET0( RADEON_RE_WIDTH_HEIGHT, 0 ) );
/* OUT_RING( ((box->y2 - 1) << 16) | (box->x2 - 1) );*/
OUT_RING( (box->y2 << 16) | box->x2 ); OUT_RING( (box->y2 << 16) | box->x2 );
ADVANCE_RING(); ADVANCE_RING();
} }
@ -1070,15 +1071,17 @@ int radeon_cp_clear( DRM_IOCTL_ARGS )
static int radeon_do_init_pageflip( drm_device_t *dev ) static int radeon_do_init_pageflip( drm_device_t *dev )
{ {
drm_radeon_private_t *dev_priv = dev->dev_private; drm_radeon_private_t *dev_priv = dev->dev_private;
RING_LOCALS;
DRM_DEBUG( "\n" ); DRM_DEBUG( "\n" );
dev_priv->crtc_offset = RADEON_READ( RADEON_CRTC_OFFSET );
dev_priv->crtc_offset_cntl = RADEON_READ( RADEON_CRTC_OFFSET_CNTL ); dev_priv->crtc_offset_cntl = RADEON_READ( RADEON_CRTC_OFFSET_CNTL );
RADEON_WRITE( RADEON_CRTC_OFFSET, dev_priv->front_offset ); BEGIN_RING( 4 );
RADEON_WRITE( RADEON_CRTC_OFFSET_CNTL, RADEON_WAIT_UNTIL_3D_IDLE();
dev_priv->crtc_offset_cntl | OUT_RING( CP_PACKET0( RADEON_CRTC_OFFSET_CNTL, 0 ) );
RADEON_CRTC_OFFSET_FLIP_CNTL ); OUT_RING( dev_priv->crtc_offset_cntl | RADEON_CRTC_OFFSET_FLIP_CNTL );
ADVANCE_RING();
dev_priv->page_flipping = 1; dev_priv->page_flipping = 1;
dev_priv->current_page = 0; dev_priv->current_page = 0;
@ -1092,13 +1095,14 @@ int radeon_do_cleanup_pageflip( drm_device_t *dev )
drm_radeon_private_t *dev_priv = dev->dev_private; drm_radeon_private_t *dev_priv = dev->dev_private;
DRM_DEBUG( "\n" ); DRM_DEBUG( "\n" );
RADEON_WRITE( RADEON_CRTC_OFFSET, dev_priv->crtc_offset ); if (dev_priv->current_page != 0)
RADEON_WRITE( RADEON_CRTC_OFFSET_CNTL, dev_priv->crtc_offset_cntl ); radeon_cp_dispatch_flip( dev );
/* FIXME: If the X server changes screen resolution, it
* clobbers the value of RADEON_CRTC_OFFSET_CNTL, above,
* leading to a flashing efect.
*/
dev_priv->page_flipping = 0; dev_priv->page_flipping = 0;
dev_priv->current_page = 0;
dev_priv->sarea_priv->pfCurrentPage = dev_priv->current_page;
return 0; return 0;
} }

30
shared/radeon_state.c
View file

@ -46,10 +46,11 @@ static __inline__ void radeon_emit_clip_rect( drm_radeon_private_t *dev_priv,
DRM_DEBUG( " box: x1=%d y1=%d x2=%d y2=%d\n", DRM_DEBUG( " box: x1=%d y1=%d x2=%d y2=%d\n",
box->x1, box->y1, box->x2, box->y2 ); box->x1, box->y1, box->x2, box->y2 );
BEGIN_RING( 3 ); BEGIN_RING( 4 );
OUT_RING( CP_PACKET3( RADEON_CNTL_SET_SCISSORS, 1 )); OUT_RING( CP_PACKET0( RADEON_RE_TOP_LEFT, 0 ) );
OUT_RING( (box->y1 << 16) | box->x1 ); OUT_RING( (box->y1 << 16) | box->x1 );
/* OUT_RING( ((box->y2 - 1) << 16) | (box->x2 - 1) );*/ OUT_RING( CP_PACKET0( RADEON_RE_WIDTH_HEIGHT, 0 ) );
/* OUT_RING( ((box->y2 - 1) << 16) | (box->x2 - 1) );*/
OUT_RING( (box->y2 << 16) | box->x2 ); OUT_RING( (box->y2 << 16) | box->x2 );
ADVANCE_RING(); ADVANCE_RING();
} }
@ -1070,15 +1071,17 @@ int radeon_cp_clear( DRM_IOCTL_ARGS )
static int radeon_do_init_pageflip( drm_device_t *dev ) static int radeon_do_init_pageflip( drm_device_t *dev )
{ {
drm_radeon_private_t *dev_priv = dev->dev_private; drm_radeon_private_t *dev_priv = dev->dev_private;
RING_LOCALS;
DRM_DEBUG( "\n" ); DRM_DEBUG( "\n" );
dev_priv->crtc_offset = RADEON_READ( RADEON_CRTC_OFFSET );
dev_priv->crtc_offset_cntl = RADEON_READ( RADEON_CRTC_OFFSET_CNTL ); dev_priv->crtc_offset_cntl = RADEON_READ( RADEON_CRTC_OFFSET_CNTL );
RADEON_WRITE( RADEON_CRTC_OFFSET, dev_priv->front_offset ); BEGIN_RING( 4 );
RADEON_WRITE( RADEON_CRTC_OFFSET_CNTL, RADEON_WAIT_UNTIL_3D_IDLE();
dev_priv->crtc_offset_cntl | OUT_RING( CP_PACKET0( RADEON_CRTC_OFFSET_CNTL, 0 ) );
RADEON_CRTC_OFFSET_FLIP_CNTL ); OUT_RING( dev_priv->crtc_offset_cntl | RADEON_CRTC_OFFSET_FLIP_CNTL );
ADVANCE_RING();
dev_priv->page_flipping = 1; dev_priv->page_flipping = 1;
dev_priv->current_page = 0; dev_priv->current_page = 0;
@ -1092,13 +1095,14 @@ int radeon_do_cleanup_pageflip( drm_device_t *dev )
drm_radeon_private_t *dev_priv = dev->dev_private; drm_radeon_private_t *dev_priv = dev->dev_private;
DRM_DEBUG( "\n" ); DRM_DEBUG( "\n" );
RADEON_WRITE( RADEON_CRTC_OFFSET, dev_priv->crtc_offset ); if (dev_priv->current_page != 0)
RADEON_WRITE( RADEON_CRTC_OFFSET_CNTL, dev_priv->crtc_offset_cntl ); radeon_cp_dispatch_flip( dev );
/* FIXME: If the X server changes screen resolution, it
* clobbers the value of RADEON_CRTC_OFFSET_CNTL, above,
* leading to a flashing efect.
*/
dev_priv->page_flipping = 0; dev_priv->page_flipping = 0;
dev_priv->current_page = 0;
dev_priv->sarea_priv->pfCurrentPage = dev_priv->current_page;
return 0; return 0;
} }