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Commit hacking from a while back. Don't be surprised if this breaks it...

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This commit is contained in:
Gareth Hughes 2001-02-20 06:20:05 +00:00
parent 22d6dd2b29
commit 996eeb8ed8
8 changed files with 468 additions and 80 deletions
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9
linux-core/mach64_drv.c
View file

@ -35,7 +35,7 @@
#define DRIVER_NAME "mach64" #define DRIVER_NAME "mach64"
#define DRIVER_DESC "DRM module for the ATI Rage Pro" #define DRIVER_DESC "DRM module for the ATI Rage Pro"
#define DRIVER_DATE "20001218" #define DRIVER_DATE "20010107"
#define DRIVER_MAJOR 1 #define DRIVER_MAJOR 1
#define DRIVER_MINOR 0 #define DRIVER_MINOR 0
@ -52,8 +52,8 @@ static drm_ioctl_desc_t mach64_ioctls[] = {
[DRM_IOCTL_NR(DRM_IOCTL_BLOCK)] = { drm_block, 1, 1 }, [DRM_IOCTL_NR(DRM_IOCTL_BLOCK)] = { drm_block, 1, 1 },
[DRM_IOCTL_NR(DRM_IOCTL_UNBLOCK)] = { drm_unblock, 1, 1 }, [DRM_IOCTL_NR(DRM_IOCTL_UNBLOCK)] = { drm_unblock, 1, 1 },
[DRM_IOCTL_NR(DRM_IOCTL_AUTH_MAGIC)] = { drm_authmagic, 1, 1 }, [DRM_IOCTL_NR(DRM_IOCTL_AUTH_MAGIC)] = { drm_authmagic, 1, 1 },
[DRM_IOCTL_NR(DRM_IOCTL_ADD_MAP)] = { drm_addmap, 1, 1 },
[DRM_IOCTL_NR(DRM_IOCTL_ADD_MAP)] = { drm_addmap, 1, 1 },
[DRM_IOCTL_NR(DRM_IOCTL_ADD_BUFS)] = { mach64_addbufs, 1, 1 }, [DRM_IOCTL_NR(DRM_IOCTL_ADD_BUFS)] = { mach64_addbufs, 1, 1 },
[DRM_IOCTL_NR(DRM_IOCTL_MARK_BUFS)] = { drm_markbufs, 1, 1 }, [DRM_IOCTL_NR(DRM_IOCTL_MARK_BUFS)] = { drm_markbufs, 1, 1 },
[DRM_IOCTL_NR(DRM_IOCTL_INFO_BUFS)] = { drm_infobufs, 1, 0 }, [DRM_IOCTL_NR(DRM_IOCTL_INFO_BUFS)] = { drm_infobufs, 1, 0 },
@ -100,6 +100,11 @@ static drm_ioctl_desc_t mach64_ioctls[] = {
#define DRIVER_IOCTL_COUNT DRM_ARRAY_SIZE( mach64_ioctls ) #define DRIVER_IOCTL_COUNT DRM_ARRAY_SIZE( mach64_ioctls )
#define HAVE_AGP 1
#define MUST_HAVE_AGP 1
#define HAVE_MTRR 1
#define HAVE_CTX_BITMAP 1 #define HAVE_CTX_BITMAP 1
#define HAVE_DMA 1 #define HAVE_DMA 1

1
linux/bufs_tmp.h
View file

@ -386,6 +386,7 @@ int TAG(mapbufs)( struct inode *inode, struct file *filp,
{ {
drm_file_t *priv = filp->private_data; drm_file_t *priv = filp->private_data;
drm_device_t *dev = priv->dev; drm_device_t *dev = priv->dev;
DRIVER_DEVICE_PRIVATE *dev_priv = dev->dev_private;
drm_device_dma_t *dma = dev->dma; drm_device_dma_t *dma = dev->dma;
int retcode = 0; int retcode = 0;
const int zero = 0; const int zero = 0;

4
linux/mach64_bufs.c
View file

@ -31,10 +31,12 @@
#include "mach64_drv.h" #include "mach64_drv.h"
#define DRIVER_DEVICE_PRIVATE drm_mach64_private_t
#define DRIVER_BUFFER_PRIVATE drm_mach64_buf_priv_t #define DRIVER_BUFFER_PRIVATE drm_mach64_buf_priv_t
#define HAVE_PCI_DMA 1 #define HAVE_AGP 1
#define DRIVER_AGP_BUFFER_MAP dev_priv->buffers
#define TAG(x) mach64_##x #define TAG(x) mach64_##x
#include "bufs_tmp.h" #include "bufs_tmp.h"

306
linux/mach64_dma.c
View file

@ -34,9 +34,9 @@
#include <linux/delay.h> #include <linux/delay.h>
#define DO_REMAP(_m) (_m)->handle = drm_ioremap( (_m)->offset, (_m)->size ) #define DO_IOREMAP(_m) (_m)->handle = drm_ioremap( (_m)->offset, (_m)->size )
#define DO_REMAPFREE(_m) \ #define DO_IOREMAPFREE(_m) \
do { \ do { \
if ( (_m)->handle && (_m)->size ) \ if ( (_m)->handle && (_m)->size ) \
drm_ioremapfree( (_m)->handle, (_m)->size ); \ drm_ioremapfree( (_m)->handle, (_m)->size ); \
@ -54,31 +54,59 @@
} while (0) } while (0)
static unsigned long mach64_alloc_page( void )
{
unsigned long address;
address = __get_free_page( GFP_KERNEL );
if ( address == 0UL ) {
return 0;
}
atomic_inc( &virt_to_page(address)->count );
set_bit( PG_reserved, &virt_to_page(address)->flags );
return address;
}
static void mach64_free_page( unsigned long address )
{
if ( !address ) return;
atomic_dec( &virt_to_page(address)->count );
clear_bit( PG_reserved, &virt_to_page(address)->flags );
free_page( address );
return;
}
/* ================================================================ /* ================================================================
* Engine control * Engine control
*/ */
int mach64_do_wait_for_fifo( drm_mach64_private_t *dev_priv, int entries ) int mach64_do_wait_for_fifo( drm_mach64_private_t *dev_priv, int entries )
{ {
int i; int slots = 0, i;
for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
int slots = (MACH64_READ( MACH64_FIFO_STAT ) & slots = (MACH64_READ( MACH64_FIFO_STAT ) &
MACH64_FIFO_SLOT_MASK); MACH64_FIFO_SLOT_MASK);
if ( slots <= (0x8000 >> entries) ) return 0; if ( slots <= (0x8000 >> entries) ) return 0;
udelay( 1 ); udelay( 1 );
} }
DRM_ERROR( "%s failed!\n", __FUNCTION__ ); DRM_ERROR( "failed! slots=%d entries=%d\n", slots, entries );
return -EBUSY; return -EBUSY;
} }
static int mach64_do_wait_for_idle( drm_mach64_private_t *dev_priv ) int mach64_do_wait_for_idle( drm_mach64_private_t *dev_priv )
{ {
int i, ret; int i, ret;
ret = mach64_do_wait_for_fifo( dev_priv, 16 ); ret = mach64_do_wait_for_fifo( dev_priv, 16 );
if ( ret ) return ret; if ( ret < 0 ) return ret;
for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
if ( !(MACH64_READ( MACH64_GUI_STAT ) & MACH64_GUI_ACTIVE) ) { if ( !(MACH64_READ( MACH64_GUI_STAT ) & MACH64_GUI_ACTIVE) ) {
@ -87,10 +115,36 @@ static int mach64_do_wait_for_idle( drm_mach64_private_t *dev_priv )
udelay( 1 ); udelay( 1 );
} }
DRM_ERROR( "%s failed!\n", __FUNCTION__ ); DRM_ERROR( "failed! GUI_STAT=0x%08x\n",
MACH64_READ( MACH64_GUI_STAT ) );
return -EBUSY; return -EBUSY;
} }
int mach64_do_engine_reset( drm_mach64_private_t *dev_priv )
{
u32 bus_cntl, gen_test_cntl;
/* Kill off any outstanding DMA transfers.
*/
bus_cntl = MACH64_READ( MACH64_BUS_CNTL );
MACH64_WRITE( MACH64_BUS_CNTL,
bus_cntl | MACH64_BUS_MASTER_DIS );
/* Reset the GUI engine (high to low transition).
*/
gen_test_cntl = MACH64_READ( MACH64_GEN_TEST_CNTL );
MACH64_WRITE( MACH64_GEN_TEST_CNTL,
gen_test_cntl | MACH64_GUI_ENGINE_ENABLE );
gen_test_cntl = MACH64_READ( MACH64_GEN_TEST_CNTL );
MACH64_WRITE( MACH64_GEN_TEST_CNTL,
gen_test_cntl & ~MACH64_GUI_ENGINE_ENABLE );
return 0;
}
static int mach64_do_dma_init( drm_device_t *dev, drm_mach64_init_t *init ) static int mach64_do_dma_init( drm_device_t *dev, drm_mach64_init_t *init )
{ {
drm_mach64_private_t *dev_priv; drm_mach64_private_t *dev_priv;
@ -130,6 +184,9 @@ static int mach64_do_dma_init( drm_device_t *dev, drm_mach64_init_t *init )
DO_FIND_MAP( dev_priv->fb, init->fb_offset ); DO_FIND_MAP( dev_priv->fb, init->fb_offset );
DO_FIND_MAP( dev_priv->mmio, init->mmio_offset ); DO_FIND_MAP( dev_priv->mmio, init->mmio_offset );
DO_FIND_MAP( dev_priv->buffers, init->buffers_offset );
DO_IOREMAP( dev_priv->buffers );
/* FIXME: Do the scratch register test for now, can remove /* FIXME: Do the scratch register test for now, can remove
* later on. * later on.
@ -151,6 +208,237 @@ static int mach64_do_dma_init( drm_device_t *dev, drm_mach64_init_t *init )
MACH64_WRITE( MACH64_SCRATCH_REG0, tmp ); MACH64_WRITE( MACH64_SCRATCH_REG0, tmp );
if ( 1 ) {
u32 *table = (u32 *) mach64_alloc_page();
u32 *data = (u32 *) mach64_alloc_page();
int i;
u32 bus_cntl, src_cntl;
mach64_do_engine_reset( dev_priv );
bus_cntl = 0x7b33a010;
src_cntl = 0x00000000;
mach64_do_wait_for_idle( dev_priv );
MACH64_WRITE( MACH64_BUS_CNTL, 0x7b33a010 );
mach64_do_wait_for_idle( dev_priv );
MACH64_WRITE( MACH64_DST_CNTL, 0x00000003 );
MACH64_WRITE( MACH64_DST_OFF_PITCH, 0x19000000 );
MACH64_WRITE( MACH64_Z_OFF_PITCH, 0x0a023280 );
MACH64_WRITE( MACH64_Z_CNTL, 0x00000100 );
MACH64_WRITE( MACH64_ALPHA_TST_CNTL, 0x00000000 );
MACH64_WRITE( MACH64_SRC_CNTL, 0x00000000 );
MACH64_WRITE( MACH64_SRC_OFF_PITCH, 0x19000000 );
MACH64_WRITE( MACH64_DP_PIX_WIDTH, 0x00040404 );
MACH64_WRITE( MACH64_DP_SRC, 0x00000100 );
mach64_do_wait_for_idle( dev_priv );
MACH64_WRITE( MACH64_SCALE_3D_CNTL, 0x00000000 );
MACH64_WRITE( MACH64_TEX_SIZE_PITCH, 0x05555555 );
MACH64_WRITE( MACH64_TEX_CNTL, 0x00000000 );
MACH64_WRITE( MACH64_SETUP_CNTL, 0x00000000 );
mach64_do_wait_for_idle( dev_priv );
MACH64_WRITE( MACH64_AGP_BASE, 0x00000000 );
MACH64_WRITE( MACH64_AGP_CNTL, 0x00000000 );
MACH64_WRITE( MACH64_DST_CNTL, 0x00000003 );
MACH64_WRITE( MACH64_GUI_TRAJ_CNTL, 0x00000003 );
MACH64_WRITE( MACH64_PAT_REG0, 0x11111111 );
#if 1
DRM_INFO( "\n" );
DRM_INFO( " AGP_BASE = 0x%08x\n", MACH64_READ( MACH64_AGP_BASE ) );
DRM_INFO( " AGP_CNTL = 0x%08x\n", MACH64_READ( MACH64_AGP_CNTL ) );
DRM_INFO( " ALPHA_TST_CNTL = 0x%08x\n", MACH64_READ( MACH64_ALPHA_TST_CNTL ) );
DRM_INFO( "\n" );
DRM_INFO( " BM_COMMAND = 0x%08x\n", MACH64_READ( MACH64_BM_COMMAND ) );
DRM_INFO( "BM_FRAME_BUF_OFFSET = 0x%08x\n", MACH64_READ( MACH64_BM_FRAME_BUF_OFFSET ) );
DRM_INFO( " BM_GUI_TABLE = 0x%08x\n", MACH64_READ( MACH64_BM_GUI_TABLE ) );
DRM_INFO( " BM_STATUS = 0x%08x\n", MACH64_READ( MACH64_BM_STATUS ) );
DRM_INFO( " BM_SYSTEM_MEM_ADDR = 0x%08x\n", MACH64_READ( MACH64_BM_SYSTEM_MEM_ADDR ) );
DRM_INFO( " BM_SYSTEM_TABLE = 0x%08x\n", MACH64_READ( MACH64_BM_SYSTEM_TABLE ) );
DRM_INFO( " BUS_CNTL = 0x%08x\n", MACH64_READ( MACH64_BUS_CNTL ) );
DRM_INFO( "\n" );
/* DRM_INFO( " CLOCK_CNTL = 0x%08x\n", MACH64_READ( MACH64_CLOCK_CNTL ) ); */
DRM_INFO( " CLR_CMP_CLR = 0x%08x\n", MACH64_READ( MACH64_CLR_CMP_CLR ) );
DRM_INFO( " CLR_CMP_CNTL = 0x%08x\n", MACH64_READ( MACH64_CLR_CMP_CNTL ) );
/* DRM_INFO( " CLR_CMP_MSK = 0x%08x\n", MACH64_READ( MACH64_CLR_CMP_MSK ) ); */
DRM_INFO( " CONFIG_CHIP_ID = 0x%08x\n", MACH64_READ( MACH64_CONFIG_CHIP_ID ) );
DRM_INFO( " CONFIG_CNTL = 0x%08x\n", MACH64_READ( MACH64_CONFIG_CNTL ) );
DRM_INFO( " CONFIG_STAT0 = 0x%08x\n", MACH64_READ( MACH64_CONFIG_STAT0 ) );
DRM_INFO( " CONFIG_STAT1 = 0x%08x\n", MACH64_READ( MACH64_CONFIG_STAT1 ) );
DRM_INFO( " CONFIG_STAT2 = 0x%08x\n", MACH64_READ( MACH64_CONFIG_STAT2 ) );
DRM_INFO( " CRC_SIG = 0x%08x\n", MACH64_READ( MACH64_CRC_SIG ) );
DRM_INFO( " CUSTOM_MACRO_CNTL = 0x%08x\n", MACH64_READ( MACH64_CUSTOM_MACRO_CNTL ) );
DRM_INFO( "\n" );
/* DRM_INFO( " DAC_CNTL = 0x%08x\n", MACH64_READ( MACH64_DAC_CNTL ) ); */
/* DRM_INFO( " DAC_REGS = 0x%08x\n", MACH64_READ( MACH64_DAC_REGS ) ); */
DRM_INFO( " DP_BKGD_CLR = 0x%08x\n", MACH64_READ( MACH64_DP_BKGD_CLR ) );
DRM_INFO( " DP_FRGD_CLR = 0x%08x\n", MACH64_READ( MACH64_DP_FRGD_CLR ) );
DRM_INFO( " DP_MIX = 0x%08x\n", MACH64_READ( MACH64_DP_MIX ) );
DRM_INFO( " DP_PIX_WIDTH = 0x%08x\n", MACH64_READ( MACH64_DP_PIX_WIDTH ) );
DRM_INFO( " DP_SRC = 0x%08x\n", MACH64_READ( MACH64_DP_SRC ) );
DRM_INFO( " DP_WRITE_MASK = 0x%08x\n", MACH64_READ( MACH64_DP_WRITE_MASK ) );
DRM_INFO( " DSP_CONFIG = 0x%08x\n", MACH64_READ( MACH64_DSP_CONFIG ) );
DRM_INFO( " DSP_ON_OFF = 0x%08x\n", MACH64_READ( MACH64_DSP_ON_OFF ) );
DRM_INFO( " DST_CNTL = 0x%08x\n", MACH64_READ( MACH64_DST_CNTL ) );
DRM_INFO( " DST_OFF_PITCH = 0x%08x\n", MACH64_READ( MACH64_DST_OFF_PITCH ) );
DRM_INFO( "\n" );
/* DRM_INFO( " EXT_DAC_REGS = 0x%08x\n", MACH64_READ( MACH64_EXT_DAC_REGS ) ); */
DRM_INFO( " EXT_MEM_CNTL = 0x%08x\n", MACH64_READ( MACH64_EXT_MEM_CNTL ) );
DRM_INFO( "\n" );
DRM_INFO( " FIFO_STAT = 0x%08x\n", MACH64_READ( MACH64_FIFO_STAT ) );
DRM_INFO( "\n" );
DRM_INFO( " GEN_TEST_CNTL = 0x%08x\n", MACH64_READ( MACH64_GEN_TEST_CNTL ) );
/* DRM_INFO( " GP_IO = 0x%08x\n", MACH64_READ( MACH64_GP_IO ) ); */
DRM_INFO( " GUI_CMDFIFO_DATA = 0x%08x\n", MACH64_READ( MACH64_GUI_CMDFIFO_DATA ) );
DRM_INFO( " GUI_CMDFIFO_DEBUG = 0x%08x\n", MACH64_READ( MACH64_GUI_CMDFIFO_DEBUG ) );
DRM_INFO( " GUI_CNTL = 0x%08x\n", MACH64_READ( MACH64_GUI_CNTL ) );
DRM_INFO( " GUI_STAT = 0x%08x\n", MACH64_READ( MACH64_GUI_STAT ) );
DRM_INFO( " GUI_TRAJ_CNTL = 0x%08x\n", MACH64_READ( MACH64_GUI_TRAJ_CNTL ) );
DRM_INFO( "\n" );
DRM_INFO( " HOST_CNTL = 0x%08x\n", MACH64_READ( MACH64_HOST_CNTL ) );
DRM_INFO( " HW_DEBUG = 0x%08x\n", MACH64_READ( MACH64_HW_DEBUG ) );
DRM_INFO( "\n" );
DRM_INFO( " MEM_ADDR_CONFIG = 0x%08x\n", MACH64_READ( MACH64_MEM_ADDR_CONFIG ) );
DRM_INFO( " MEM_BUF_CNTL = 0x%08x\n", MACH64_READ( MACH64_MEM_BUF_CNTL ) );
DRM_INFO( "\n" );
DRM_INFO( " SCALE_3D_CNTL = 0x%08x\n", MACH64_READ( MACH64_SCALE_3D_CNTL ) );
DRM_INFO( " SCRATCH_REG0 = 0x%08x\n", MACH64_READ( MACH64_SCRATCH_REG0 ) );
DRM_INFO( " SCRATCH_REG1 = 0x%08x\n", MACH64_READ( MACH64_SCRATCH_REG1 ) );
DRM_INFO( " SETUP_CNTL = 0x%08x\n", MACH64_READ( MACH64_SETUP_CNTL ) );
DRM_INFO( " SRC_CNTL = 0x%08x\n", MACH64_READ( MACH64_SRC_CNTL ) );
DRM_INFO( "\n" );
DRM_INFO( " TEX_CNTL = 0x%08x\n", MACH64_READ( MACH64_TEX_CNTL ) );
DRM_INFO( " TEX_SIZE_PITCH = 0x%08x\n", MACH64_READ( MACH64_TEX_SIZE_PITCH ) );
DRM_INFO( " TIMER_CONFIG = 0x%08x\n", MACH64_READ( MACH64_TIMER_CONFIG ) );
DRM_INFO( "\n" );
DRM_INFO( " Z_CNTL = 0x%08x\n", MACH64_READ( MACH64_Z_CNTL ) );
DRM_INFO( " Z_OFF_PITCH = 0x%08x\n", MACH64_READ( MACH64_Z_OFF_PITCH ) );
DRM_INFO( "\n" );
#endif
data[0] = 0x000000a0;
data[1] = 0x22222222;
data[2] = 0x000000a0;
data[3] = 0x22222222;
data[4] = 0x000000a0;
data[5] = 0x22222222;
data[6] = 0x0000006d;
data[7] = 0x00000000;
table[0] = MACH64_BM_ADDR + APERTURE_OFFSET;
table[1] = virt_to_phys(data);
table[2] = 8 * sizeof(u32) | 0xc0000000;
table[3] = 0x00000000;
DRM_INFO( "table[0] = 0x%08x\n", table[0] );
DRM_INFO( "table[1] = 0x%08x\n", table[1] );
DRM_INFO( "table[2] = 0x%08x\n", table[2] );
DRM_INFO( "table[3] = 0x%08x\n", table[3] );
for ( i = 0 ; i < 8 ; i++) {
DRM_INFO( " data[%d] = 0x%08x\n", i, data[i] );
}
mb();
DRM_INFO( "waiting for idle...\n" );
mach64_do_wait_for_idle( dev_priv );
DRM_INFO( "waiting for idle... done.\n" );
DRM_INFO( "BUS_CNTL = 0x%08x\n", bus_cntl );
DRM_INFO( "SRC_CNTL = 0x%08x\n", src_cntl );
DRM_INFO( "\n" );
DRM_INFO( "data = 0x%08x\n", virt_to_phys(data) );
DRM_INFO( "table = 0x%08x\n", virt_to_phys(table) );
DRM_INFO( "starting DMA transfer...\n" );
MACH64_READ( MACH64_BUS_CNTL );
MACH64_WRITE( MACH64_BUS_CNTL, bus_cntl );
MACH64_WRITE( MACH64_BM_GUI_TABLE_CMD, virt_to_phys(table) );
MACH64_READ( MACH64_SRC_CNTL );
MACH64_WRITE( MACH64_SRC_CNTL, 0x00000f00 );
DRM_INFO( "waiting for idle...\n" );
mach64_do_wait_for_idle( dev_priv );
/* Kick off the transfer */
MACH64_WRITE( MACH64_DST_HEIGHT_WIDTH, 0 );
DRM_INFO( "starting DMA transfer... done.\n" );
for ( i = 0 ; i < 1000 ; i++ ) {
udelay( 1 );
}
done:
DRM_INFO( "waiting for idle 0...\n" );
mach64_do_wait_for_idle( dev_priv );
DRM_INFO( "\n" );
DRM_INFO( "BUS_CNTL = 0x%08x\n",
MACH64_READ( MACH64_BUS_CNTL ) );
DRM_INFO( "SRC_CNTL = 0x%08x\n",
MACH64_READ( MACH64_SRC_CNTL ) );
DRM_INFO( "PAT_REG0 = 0x%08x\n",
MACH64_READ( MACH64_PAT_REG0 ) );
DRM_INFO( "\n" );
DRM_INFO( "GUI_CMDFIFO_DEBUG = 0x%08x\n",
MACH64_READ( MACH64_GUI_CMDFIFO_DEBUG ) );
DRM_INFO( "GUI_CMDFIFO_DATA = 0x%08x\n",
MACH64_READ( MACH64_GUI_CMDFIFO_DATA ) );
DRM_INFO( "FIFO_STAT = 0x%08x\n",
MACH64_READ( MACH64_FIFO_STAT ) );
DRM_INFO( "\n" );
DRM_INFO( "BM_FRAME_BUF_OFFSET = 0x%08x\n",
MACH64_READ( MACH64_BM_FRAME_BUF_OFFSET ) );
DRM_INFO( "BM_SYSTEM_MEM_ADDR = 0x%08x\n",
MACH64_READ( MACH64_BM_SYSTEM_MEM_ADDR ) );
DRM_INFO( "BM_COMMAND = 0x%08x\n",
MACH64_READ( MACH64_BM_COMMAND ) );
DRM_INFO( "BM_STATUS = 0x%08x\n",
MACH64_READ( MACH64_BM_STATUS ) );
DRM_INFO( "BM_SYSTEM_TABLE = 0x%08x\n",
MACH64_READ( MACH64_BM_SYSTEM_TABLE ) );
DRM_INFO( "BM_HOSTDATA = 0x%08x\n",
MACH64_READ( MACH64_BM_HOSTDATA ) );
DRM_INFO( "BM_ADDR/BM_DATA = 0x%08x\n",
MACH64_READ( MACH64_BM_ADDR ) );
DRM_INFO( "BM_GUI_TABLE = 0x%08x\n",
MACH64_READ( MACH64_BM_GUI_TABLE ) );
DRM_INFO( "BM_GUI_TABLE_CMD = 0x%08x\n",
MACH64_READ( MACH64_BM_GUI_TABLE_CMD ) );
DRM_INFO( "freeing memory.\n" );
mach64_free_page( (unsigned long)data );
mach64_free_page( (unsigned long)table );
}
return 0; return 0;
} }
@ -161,6 +449,8 @@ static int mach64_do_dma_cleanup( drm_device_t *dev )
if ( dev->dev_private ) { if ( dev->dev_private ) {
drm_mach64_private_t *dev_priv = dev->dev_private; drm_mach64_private_t *dev_priv = dev->dev_private;
DO_IOREMAPFREE( dev_priv->buffers );
drm_free( dev_priv, sizeof(drm_mach64_private_t), drm_free( dev_priv, sizeof(drm_mach64_private_t),
DRM_MEM_DRIVER ); DRM_MEM_DRIVER );
dev->dev_private = NULL; dev->dev_private = NULL;

1
linux/mach64_drm.h
View file

@ -159,6 +159,7 @@ typedef struct drm_mach64_init {
unsigned int fb_offset; unsigned int fb_offset;
unsigned int mmio_offset; unsigned int mmio_offset;
unsigned int buffers_offset;
} drm_mach64_init_t; } drm_mach64_init_t;
typedef struct drm_mach64_clear { typedef struct drm_mach64_clear {

9
linux/mach64_drv.c
View file

@ -35,7 +35,7 @@
#define DRIVER_NAME "mach64" #define DRIVER_NAME "mach64"
#define DRIVER_DESC "DRM module for the ATI Rage Pro" #define DRIVER_DESC "DRM module for the ATI Rage Pro"
#define DRIVER_DATE "20001218" #define DRIVER_DATE "20010107"
#define DRIVER_MAJOR 1 #define DRIVER_MAJOR 1
#define DRIVER_MINOR 0 #define DRIVER_MINOR 0
@ -52,8 +52,8 @@ static drm_ioctl_desc_t mach64_ioctls[] = {
[DRM_IOCTL_NR(DRM_IOCTL_BLOCK)] = { drm_block, 1, 1 }, [DRM_IOCTL_NR(DRM_IOCTL_BLOCK)] = { drm_block, 1, 1 },
[DRM_IOCTL_NR(DRM_IOCTL_UNBLOCK)] = { drm_unblock, 1, 1 }, [DRM_IOCTL_NR(DRM_IOCTL_UNBLOCK)] = { drm_unblock, 1, 1 },
[DRM_IOCTL_NR(DRM_IOCTL_AUTH_MAGIC)] = { drm_authmagic, 1, 1 }, [DRM_IOCTL_NR(DRM_IOCTL_AUTH_MAGIC)] = { drm_authmagic, 1, 1 },
[DRM_IOCTL_NR(DRM_IOCTL_ADD_MAP)] = { drm_addmap, 1, 1 },
[DRM_IOCTL_NR(DRM_IOCTL_ADD_MAP)] = { drm_addmap, 1, 1 },
[DRM_IOCTL_NR(DRM_IOCTL_ADD_BUFS)] = { mach64_addbufs, 1, 1 }, [DRM_IOCTL_NR(DRM_IOCTL_ADD_BUFS)] = { mach64_addbufs, 1, 1 },
[DRM_IOCTL_NR(DRM_IOCTL_MARK_BUFS)] = { drm_markbufs, 1, 1 }, [DRM_IOCTL_NR(DRM_IOCTL_MARK_BUFS)] = { drm_markbufs, 1, 1 },
[DRM_IOCTL_NR(DRM_IOCTL_INFO_BUFS)] = { drm_infobufs, 1, 0 }, [DRM_IOCTL_NR(DRM_IOCTL_INFO_BUFS)] = { drm_infobufs, 1, 0 },
@ -100,6 +100,11 @@ static drm_ioctl_desc_t mach64_ioctls[] = {
#define DRIVER_IOCTL_COUNT DRM_ARRAY_SIZE( mach64_ioctls ) #define DRIVER_IOCTL_COUNT DRM_ARRAY_SIZE( mach64_ioctls )
#define HAVE_AGP 1
#define MUST_HAVE_AGP 1
#define HAVE_MTRR 1
#define HAVE_CTX_BITMAP 1 #define HAVE_CTX_BITMAP 1
#define HAVE_DMA 1 #define HAVE_DMA 1

91
linux/mach64_drv.h
View file

@ -45,11 +45,10 @@ typedef struct drm_mach64_private {
int usec_timeout; int usec_timeout;
u32 *buffers;
drm_map_t *sarea; drm_map_t *sarea;
drm_map_t *fb; drm_map_t *fb;
drm_map_t *mmio; drm_map_t *mmio;
drm_map_t *buffers;
} drm_mach64_private_t; } drm_mach64_private_t;
typedef struct drm_mach64_buf_priv { typedef struct drm_mach64_buf_priv {
@ -102,6 +101,8 @@ extern int mach64_dma_idle( struct inode *inode, struct file *filp,
extern int mach64_do_wait_for_fifo( drm_mach64_private_t *dev_priv, extern int mach64_do_wait_for_fifo( drm_mach64_private_t *dev_priv,
int entries ); int entries );
extern int mach64_do_wait_for_idle( drm_mach64_private_t *dev_priv );
extern int mach64_do_engine_reset( drm_mach64_private_t *dev_priv );
/* r128_state.c */ /* r128_state.c */
extern int mach64_dma_clear( struct inode *inode, struct file *filp, extern int mach64_dma_clear( struct inode *inode, struct file *filp,
@ -114,21 +115,55 @@ extern int mach64_dma_swap( struct inode *inode, struct file *filp,
* Registers * Registers
*/ */
#define MACH64_AGP_BASE 0x0148
#define MACH64_AGP_CNTL 0x014c
#define MACH64_ALPHA_TST_CNTL 0x0550 #define MACH64_ALPHA_TST_CNTL 0x0550
#define MACH64_DSP_CONFIG 0x0420
#define MACH64_DSP_ON_OFF 0x0424
#define MACH64_EXT_MEM_CNTL 0x04ac
#define MACH64_GEN_TEST_CNTL 0x04d0
#define MACH64_HW_DEBUG 0x047c
#define MACH64_MEM_ADDR_CONFIG 0x0434
#define MACH64_MEM_BUF_CNTL 0x042c
#define MACH64_MEM_CNTL 0x04b0
#define MACH64_BM_ADDR 0x0648
#define MACH64_BM_COMMAND 0x0188
#define MACH64_BM_DATA 0x0648
#define MACH64_BM_FRAME_BUF_OFFSET 0x0180
#define MACH64_BM_GUI_TABLE 0x01b8
#define MACH64_BM_GUI_TABLE_CMD 0x064c
# define MACH64_CIRCULAR_BUF_SIZE_16KB (0 << 0)
# define MACH64_CIRCULAR_BUF_SIZE_32KB (1 << 0)
# define MACH64_CIRCULAR_BUF_SIZE_64KB (2 << 0)
# define MACH64_CIRCULAR_BUF_SIZE_128KB (3 << 0)
# define MACH64_LAST_DESCRIPTOR (1 << 31)
#define MACH64_BM_HOSTDATA 0x0644
#define MACH64_BM_STATUS 0x018c
#define MACH64_BM_SYSTEM_MEM_ADDR 0x0184
#define MACH64_BM_SYSTEM_TABLE 0x01bc
#define MACH64_BUS_CNTL 0x04a0 #define MACH64_BUS_CNTL 0x04a0
# define MACH64_BUS_MSTR_RESET (1 << 1) # define MACH64_BUS_MSTR_RESET (1 << 1)
# define MACH64_BUS_FLUSH_BUF (1 << 2) # define MACH64_BUS_FLUSH_BUF (1 << 2)
# define MACH64_BUS_MASTER_DIS (1 << 6) # define MACH64_BUS_MASTER_DIS (1 << 6)
# define MACH64_BUS_EXT_REG_EN (1 << 27) # define MACH64_BUS_EXT_REG_EN (1 << 27)
#define MACH64_COMPOSITE_SHADOW_ID 0x0798
#define MACH64_CONTEXT_LOAD_CNTL 0x072c
#define MACH64_CONTEXT_MASK 0x0720
#define MACH64_CLR_CMP_CLR 0x0700 #define MACH64_CLR_CMP_CLR 0x0700
#define MACH64_CLR_CMP_CNTL 0x0708 #define MACH64_CLR_CMP_CNTL 0x0708
#define MACH64_CLR_CMP_MASK 0x0704 #define MACH64_CLR_CMP_MASK 0x0704
#define MACH64_CONFIG_CHIP_ID 0x04e0
#define MACH64_CONFIG_CNTL 0x04dc
#define MACH64_CONFIG_STAT0 0x04e4
#define MACH64_CONFIG_STAT1 0x0494
#define MACH64_CONFIG_STAT2 0x0498
#define MACH64_CONTEXT_LOAD_CNTL 0x072c
#define MACH64_CONTEXT_MASK 0x0720
#define MACH64_COMPOSITE_SHADOW_ID 0x0798
#define MACH64_CRC_SIG 0x04e8
#define MACH64_CUSTOM_MACRO_CNTL 0x04d4
#define MACH64_DP_BKGD_CLR 0x06c0 #define MACH64_DP_BKGD_CLR 0x06c0
#define MACH64_DP_FOG_CLR 0x06c4 #define MACH64_DP_FOG_CLR 0x06c4
@ -220,23 +255,34 @@ extern int mach64_dma_swap( struct inode *inode, struct file *filp,
# define MACH64_FIFO_SLOT_MASK 0x0000ffff # define MACH64_FIFO_SLOT_MASK 0x0000ffff
# define MACH64_FIFO_ERR (1 << 31) # define MACH64_FIFO_ERR (1 << 31)
#define MACH64_GEN_TEST_CNTL 0x04d0
# define MACH64_GUI_ENGINE_ENABLE (1 << 8)
#define MACH64_GUI_CMDFIFO_DEBUG 0x0170 #define MACH64_GUI_CMDFIFO_DEBUG 0x0170
#define MACH64_GUI_CMDFIFO_DATA 0x0174 #define MACH64_GUI_CMDFIFO_DATA 0x0174
#define MACH64_GUI_CNTL 0x0178 #define MACH64_GUI_CNTL 0x0178
#define MACH64_GUI_STAT 0x0738 #define MACH64_GUI_STAT 0x0738
# define MACH64_GUI_ACTIVE (1 << 0) # define MACH64_GUI_ACTIVE (1 << 0)
#define MACH64_GUI_TRAJ_CNTL 0x0730 #define MACH64_GUI_TRAJ_CNTL 0x0730
#define MACH64_HOST_CNTL 0x0640 #define MACH64_HOST_CNTL 0x0640
#define MACH64_HOST_DATA0 0x0600 #define MACH64_HOST_DATA0 0x0600
#define MACH64_ONE_OVER_AREA 0x029c #define MACH64_ONE_OVER_AREA 0x029c
#define MACH64_ONE_OVER_AREA_UC 0x0300 #define MACH64_ONE_OVER_AREA_UC 0x0300
#define MACH64_PAT_REG0 0x0680
#define MACH64_SCALE_3D_CNTL 0x05fc #define MACH64_SCALE_3D_CNTL 0x05fc
#define MACH64_SCRATCH_REG0 0x0480 #define MACH64_SCRATCH_REG0 0x0480
#define MACH64_SCRATCH_REG1 0x0484 #define MACH64_SCRATCH_REG1 0x0484
#define MACH64_SETUP_CNTL 0x0304 #define MACH64_SETUP_CNTL 0x0304
#define MACH64_SRC_CNTL 0x05b4 #define MACH64_SRC_CNTL 0x05b4
# define MACH64_SRC_BM_ENABLE (1 << 8)
# define MACH64_SRC_BM_SYNC (1 << 9)
# define MACH64_SRC_BM_OP_FRAME_TO_SYSTEM (0 << 10)
# define MACH64_SRC_BM_OP_SYSTEM_TO_FRAME (1 << 10)
# define MACH64_SRC_BM_OP_REG_TO_SYSTEM (2 << 10)
# define MACH64_SRC_BM_OP_SYSTEM_TO_REG (3 << 10)
#define MACH64_SRC_HEIGHT1 0x0594 #define MACH64_SRC_HEIGHT1 0x0594
#define MACH64_SRC_HEIGHT2 0x05ac #define MACH64_SRC_HEIGHT2 0x05ac
#define MACH64_SRC_HEIGHT1_WIDTH1 0x0598 #define MACH64_SRC_HEIGHT1_WIDTH1 0x0598
@ -245,6 +291,10 @@ extern int mach64_dma_swap( struct inode *inode, struct file *filp,
#define MACH64_SRC_WIDTH1 0x0590 #define MACH64_SRC_WIDTH1 0x0590
#define MACH64_SRC_Y_X 0x058c #define MACH64_SRC_Y_X 0x058c
#define MACH64_TEX_CNTL 0x0774
#define MACH64_TEX_SIZE_PITCH 0x0770
#define MACH64_TIMER_CONFIG 0x0428
#define MACH64_VERTEX_1_ARGB 0x0254 #define MACH64_VERTEX_1_ARGB 0x0254
#define MACH64_VERTEX_1_S 0x0240 #define MACH64_VERTEX_1_S 0x0240
#define MACH64_VERTEX_1_SECONDARY_S 0x0328 #define MACH64_VERTEX_1_SECONDARY_S 0x0328
@ -300,6 +350,35 @@ extern int mach64_dma_swap( struct inode *inode, struct file *filp,
#define DWMREG0 0x0400
#define DWMREG0_END 0x07ff
#define DWMREG1 0x0000
#define DWMREG1_END 0x03ff
#define ISREG0(r) (((r) >= DWMREG0) && ((r) <= DWMREG0_END))
#define DMAREG0(r) (((r) - DWMREG0) >> 2)
#define DMAREG1(r) ((((r) - DWMREG1) >> 2 ) | 0x0100)
#define DMAREG(r) (ISREG0(r) ? DMAREG0(r) : DMAREG1(r))
#define MMREG0 0x0000
#define MMREG0_END 0x00ff
#define ISMMREG0(r) (((r) >= MMREG0) && ((r) <= MMREG0_END))
#define MMSELECT0(r) (((r) << 2) + DWMREG0)
#define MMSELECT1(r) (((((r) & 0xff) << 2) + DWMREG1))
#define MMSELECT(r) (ISMMREG0(r) ? MMSELECT0(r) : MMSELECT1(r))
#define DMA_FRAME_BUF_OFFSET 0
#define DMA_SYS_MEM_ADDR 1
#define DMA_COMMAND 2
#define DMA_RESERVED 3
#define DMA_CHUNKSIZE 0x1000
#define APERTURE_OFFSET 0x7ff800
#define MACH64_VERBOSE 0 #define MACH64_VERBOSE 0
#define DMALOCALS #define DMALOCALS

5
linux/mach64_state.c
View file

@ -69,6 +69,7 @@ static void mach64_dma_dispatch_clear( drm_device_t *dev,
DMALOCALS; DMALOCALS;
DRM_DEBUG( "%s\n", __FUNCTION__ ); DRM_DEBUG( "%s\n", __FUNCTION__ );
#if 0
switch ( dev_priv->fb_bpp ) { switch ( dev_priv->fb_bpp ) {
case 16: case 16:
fb_bpp = MACH64_DATATYPE_RGB565; fb_bpp = MACH64_DATATYPE_RGB565;
@ -196,6 +197,10 @@ static void mach64_dma_dispatch_clear( drm_device_t *dev,
DMAADVANCE( dev_priv ); DMAADVANCE( dev_priv );
} }
} }
#endif
} }
static void mach64_dma_dispatch_swap( drm_device_t *dev ) static void mach64_dma_dispatch_swap( drm_device_t *dev )