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radeon: add CS support for r100/r200 in 2D driver

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This commit is contained in:
Dave Airlie 2008-10-16 10:57:31 +10:00
parent 66740cbd54
commit 8d9a11c55c
2 changed files with 69 additions and 0 deletions
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64
shared-core/r300_cmdbuf.c
View file

@ -35,6 +35,7 @@
#include "drm.h"
#include "radeon_drm.h"
#include "radeon_drv.h"
#include "radeon_reg.h"
#include "r300_reg.h"
#define R300_SIMULTANEOUS_CLIPRECTS 4
@ -309,6 +310,69 @@ void r300_init_reg_flags(struct drm_device *dev)
ADD_RANGE(RADEON_RE_WIDTH_HEIGHT, 1);
ADD_RANGE(RADEON_AUX_SC_CNTL, 1);
ADD_RANGE(RADEON_RB3D_DSTCACHE_CTLSTAT, 1);
ADD_RANGE(RADEON_RB3D_PLANEMASK, 1);
ADD_RANGE(RADEON_SE_CNTL, 1);
ADD_RANGE(RADEON_PP_CNTL, 1);
ADD_RANGE(RADEON_RB3D_CNTL, 1);
ADD_RANGE_MARK(RADEON_RB3D_COLOROFFSET, 1, MARK_CHECK_OFFSET);
ADD_RANGE(RADEON_RB3D_COLORPITCH, 1);
ADD_RANGE(RADEON_RB3D_BLENDCNTL, 1);
if (dev_priv->chip_family >= CHIP_R200) {
ADD_RANGE(R200_PP_CNTL_X, 1);
ADD_RANGE(R200_PP_TXMULTI_CTL_0, 1);
ADD_RANGE(R200_SE_VTX_STATE_CNTL, 1);
ADD_RANGE(R200_RE_CNTL, 1);
ADD_RANGE(R200_SE_VTE_CNTL, 1);
ADD_RANGE(R200_SE_VAP_CNTL, 1);
ADD_RANGE(R200_PP_TXFILTER_0, 1);
ADD_RANGE(R200_PP_TXFORMAT_0, 1);
ADD_RANGE(R200_PP_TXFORMAT_X_0, 1);
ADD_RANGE(R200_PP_TXSIZE_0, 1);
ADD_RANGE(R200_PP_TXPITCH_0, 1);
ADD_RANGE(R200_PP_TFACTOR_0, 1);
ADD_RANGE(R200_PP_TXFILTER_1, 1);
ADD_RANGE(R200_PP_TXFORMAT_1, 1);
ADD_RANGE(R200_PP_TXFORMAT_X_1, 1);
ADD_RANGE(R200_PP_TXSIZE_1, 1);
ADD_RANGE(R200_PP_TXPITCH_1, 1);
ADD_RANGE(R200_PP_TFACTOR_1, 1);
ADD_RANGE_MARK(R200_PP_TXOFFSET_0, 1, MARK_CHECK_OFFSET);
ADD_RANGE_MARK(R200_PP_TXOFFSET_1, 1, MARK_CHECK_OFFSET);
ADD_RANGE_MARK(R200_PP_TXOFFSET_2, 1, MARK_CHECK_OFFSET);
ADD_RANGE_MARK(R200_PP_TXOFFSET_3, 1, MARK_CHECK_OFFSET);
ADD_RANGE_MARK(R200_PP_TXOFFSET_4, 1, MARK_CHECK_OFFSET);
ADD_RANGE_MARK(R200_PP_TXOFFSET_5, 1, MARK_CHECK_OFFSET);
ADD_RANGE(R200_SE_VTX_FMT_0, 1);
ADD_RANGE(R200_SE_VTX_FMT_1, 1);
ADD_RANGE(R200_PP_TXCBLEND_0, 1);
ADD_RANGE(R200_PP_TXCBLEND2_0, 1);
ADD_RANGE(R200_PP_TXABLEND_0, 1);
ADD_RANGE(R200_PP_TXABLEND2_0, 1);
} else {
ADD_RANGE(RADEON_PP_TXFILTER_0, 1);
ADD_RANGE(RADEON_PP_TXFORMAT_0, 1);
ADD_RANGE(RADEON_PP_TEX_SIZE_0, 1);
ADD_RANGE(RADEON_PP_TEX_PITCH_0, 1);
ADD_RANGE(RADEON_PP_TXFILTER_1, 1);
ADD_RANGE(RADEON_PP_TXFORMAT_1, 1);
ADD_RANGE(RADEON_PP_TEX_SIZE_1, 1);
ADD_RANGE(RADEON_PP_TEX_PITCH_1, 1);
ADD_RANGE(RADEON_PP_TXCBLEND_0, 1);
ADD_RANGE(RADEON_PP_TXABLEND_0, 1);
ADD_RANGE(RADEON_SE_VTX_FMT, 1);
ADD_RANGE_MARK(RADEON_PP_TXOFFSET_0, 1, MARK_CHECK_OFFSET);
ADD_RANGE_MARK(RADEON_PP_TXOFFSET_1, 1, MARK_CHECK_OFFSET);
ADD_RANGE_MARK(RADEON_PP_TXOFFSET_2, 1, MARK_CHECK_OFFSET);
}
}
}

5
shared-core/radeon_cs.c
View file

@ -139,10 +139,15 @@ static __inline__ int radeon_cs_relocate_packet0(struct drm_device *dev, struct
offset >>= 10;
val |= offset;
break;
case RADEON_RB3D_COLOROFFSET:
case R300_RB3D_COLOROFFSET0:
case R300_ZB_DEPTHOFFSET:
case R300_TX_OFFSET_0:
case R300_TX_OFFSET_0+4:
case R200_PP_TXOFFSET_0:
case R200_PP_TXOFFSET_1:
case RADEON_PP_TXOFFSET_0:
case RADEON_PP_TXOFFSET_1:
ret = dev_priv->cs.relocate(dev, file_priv, packets + offset_dw + 2, &offset);
if (ret)
return ret;