mirror of
https://gitlab.freedesktop.org/mesa/drm.git
synced 2026-05-09 05:08:04 +02:00
Add mach64 to the trunk
This commit is contained in:
Dave Airlie
parent
7e39628577
commit
873e1c4d38
18 changed files with 7465 additions and 6 deletions
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@ -88,3 +88,15 @@ config DRM_VIA
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Choose this option if you have a Via unichrome or compatible video
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chipset. If M is selected the module will be called via.
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config DRM_MACH64
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tristate "ATI Rage Pro (Mach64)"
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depends on DRM
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help
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Choose this option if you have an ATI Rage Pro (mach64 chipset)
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graphics card. Example cards include: 3D Rage Pro, Xpert 98,
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3D Rage LT Pro, 3D Rage XL/XC, and 3D Rage Mobility (P/M, M1).
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Cards earlier than ATI Rage Pro (e.g. Rage II) are not supported.
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If M is selected, the module will be called mach64. AGP support for
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this card is strongly suggested (unless you have a PCI version).
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@ -18,6 +18,7 @@ sis-objs := sis_drv.o sis_ds.o sis_mm.o
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ffb-objs := ffb_drv.o ffb_context.o
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savage-objs := savage_drv.o savage_dma.o
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via-objs := via_irq.o via_drv.o via_ds.o via_map.o via_mm.o
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mach64-objs := mach64_drv.o mach64_dma.o mach64_irq.o mach64_state.o
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# Kernel version checks
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@ -33,7 +34,7 @@ endif
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ifeq ($(BELOW25),y)
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O_TARGET := drm.o
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list-multi := gamma.o tdfx.o r128.o mga.o i810.o i830.o ffb.o radeon.o \
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savage.o via.o
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savage.o via.o mach64.o
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obj-m :=
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obj-n :=
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obj- :=
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@ -51,6 +52,7 @@ obj-$(CONFIG_DRM_SIS) += sis.o
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obj-$(CONFIG_DRM_FFB) += ffb.o
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obj-$(CONFIG_DRM_SAVAGE)+= savage.o
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obj-$(CONFIG_DRM_VIA) += via.o
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obj-$(CONFIG_DRM_MACH64)+= mach64.o
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ifeq ($(BELOW2552),y)
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include $(TOPDIR)/Rules.make
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@ -90,5 +92,8 @@ savage.o: $(savage-objs) $(lib)
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via.o: $(via-objs) $(lib)
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$(LD) -r -o $@ $(via-objs) $(lib)
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mach64.o: $(mach64-objs) $(lib)
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$(LD) -r -o $@ $(mach64-objs) $(lib)
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endif
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@ -1057,6 +1057,12 @@ extern int DRM(ati_pcigart_cleanup)(drm_device_t *dev,
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unsigned long addr,
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dma_addr_t bus_addr);
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extern void *DRM(pci_alloc)(drm_device_t *dev, size_t size,
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size_t align, dma_addr_t maxaddr,
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dma_addr_t *busaddr);
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extern void DRM(pci_free)(drm_device_t *dev, size_t size,
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void *vaddr, dma_addr_t busaddr);
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/*@}*/
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#endif /* __KERNEL__ */
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@ -88,3 +88,15 @@ config DRM_VIA
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Choose this option if you have a Via unichrome or compatible video
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chipset. If M is selected the module will be called via.
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config DRM_MACH64
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tristate "ATI Rage Pro (Mach64)"
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depends on DRM
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help
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Choose this option if you have an ATI Rage Pro (mach64 chipset)
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graphics card. Example cards include: 3D Rage Pro, Xpert 98,
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3D Rage LT Pro, 3D Rage XL/XC, and 3D Rage Mobility (P/M, M1).
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Cards earlier than ATI Rage Pro (e.g. Rage II) are not supported.
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If M is selected, the module will be called mach64. AGP support for
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this card is strongly suggested (unless you have a PCI version).
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@ -18,6 +18,7 @@ sis-objs := sis_drv.o sis_ds.o sis_mm.o
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ffb-objs := ffb_drv.o ffb_context.o
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savage-objs := savage_drv.o savage_dma.o
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via-objs := via_irq.o via_drv.o via_ds.o via_map.o via_mm.o
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mach64-objs := mach64_drv.o mach64_dma.o mach64_irq.o mach64_state.o
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# Kernel version checks
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@ -33,7 +34,7 @@ endif
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ifeq ($(BELOW25),y)
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O_TARGET := drm.o
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list-multi := gamma.o tdfx.o r128.o mga.o i810.o i830.o ffb.o radeon.o \
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savage.o via.o
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savage.o via.o mach64.o
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obj-m :=
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obj-n :=
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obj- :=
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@ -51,6 +52,7 @@ obj-$(CONFIG_DRM_SIS) += sis.o
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obj-$(CONFIG_DRM_FFB) += ffb.o
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obj-$(CONFIG_DRM_SAVAGE)+= savage.o
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obj-$(CONFIG_DRM_VIA) += via.o
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obj-$(CONFIG_DRM_MACH64)+= mach64.o
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ifeq ($(BELOW2552),y)
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include $(TOPDIR)/Rules.make
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@ -90,5 +92,8 @@ savage.o: $(savage-objs) $(lib)
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via.o: $(via-objs) $(lib)
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$(LD) -r -o $@ $(via-objs) $(lib)
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mach64.o: $(mach64-objs) $(lib)
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$(LD) -r -o $@ $(mach64-objs) $(lib)
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endif
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@ -44,7 +44,7 @@ endif
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MACHINE := $(shell uname -m)
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# Modules for all architectures
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MODULE_LIST := gamma.o tdfx.o r128.o radeon.o mga.o sis.o savage.o via.o
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MODULE_LIST := gamma.o tdfx.o r128.o radeon.o mga.o sis.o savage.o via.o mach64.o
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# Modules only for ix86 architectures
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ifneq (,$(findstring 86,$(MACHINE)))
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@ -89,9 +89,13 @@ VIAHEADERS = via_drm.h via_drv.h via.h via_mm.h via_ds.h \
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$(DRMHEADERS) $(DRMTEMPLATES)
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VIASHARED = via_drm.h via_drv.h via.h via_mm.h via_ds.h via_drv.c \
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via_ds.c via_irq.c via_map.c via_mm.c
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MACH64HEADERS = mach64.h mach64_drv.h mach64_drm.h $(DRMHEADERS) \
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$(DRMTEMPLATES)
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MACH64SHARED = mach64.h mach64_drv.h mach64_drm.h mach64_dma.c \
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mach64_irq.c mach64_state.c
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SHAREDSRC = $(DRMSHARED) $(MGASHARED) $(R128SHARED) $(RADEONSHARED) \
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$(SISSHARED) $(TDFXSHARED) $(VIASHARED)
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$(SISSHARED) $(TDFXSHARED) $(VIASHARED) $(MACH64SHARED)
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PROGS = dristat drmstat
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@ -322,7 +326,7 @@ CONFIG_DRM_SIS := n
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CONFIG_DRM_FFB := n
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CONFIG_DRM_SAVAGE := n
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CONFIG_DRM_VIA := n
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CONFIG_DRM_MACH64 := n
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# Enable module builds for the modules requested/supported.
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@ -344,6 +348,10 @@ endif
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ifneq (,$(findstring via,$(DRM_MODULES)))
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CONFIG_DRM_VIA := m
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endif
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ifneq (,$(findstring mach64,$(DRM_MODULES)))
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CONFIG_DRM_MACH64 := m
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endif
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# These require AGP support
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@ -377,7 +385,7 @@ $(sis-objs): $(SISHEADERS)
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$(ffb-objs): $(FFBHEADERS)
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$(savage-objs): $(SAVAGEHEADERS)
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$(via-objs): $(VIAHEADERS)
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$(mach64-objs): $(MACH64HEADERS)
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endif
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@ -1057,6 +1057,12 @@ extern int DRM(ati_pcigart_cleanup)(drm_device_t *dev,
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unsigned long addr,
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dma_addr_t bus_addr);
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extern void *DRM(pci_alloc)(drm_device_t *dev, size_t size,
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size_t align, dma_addr_t maxaddr,
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dma_addr_t *busaddr);
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extern void DRM(pci_free)(drm_device_t *dev, size_t size,
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void *vaddr, dma_addr_t busaddr);
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/*@}*/
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#endif /* __KERNEL__ */
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1325
shared-core/mach64_dma.c
Normal file
1325
shared-core/mach64_dma.c
Normal file
File diff suppressed because it is too large
Load diff
258
shared-core/mach64_drm.h
Normal file
258
shared-core/mach64_drm.h
Normal file
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@ -0,0 +1,258 @@
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/* mach64_drm.h -- Public header for the mach64 driver -*- linux-c -*-
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* Created: Thu Nov 30 20:04:32 2000 by gareth@valinux.com
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*
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* Copyright 2000 Gareth Hughes
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* Copyright 2002 Frank C. Earl
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* Copyright 2002-2003 Leif Delgass
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT OWNER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors:
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* Gareth Hughes <gareth@valinux.com>
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* Frank C. Earl <fearl@airmail.net>
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* Leif Delgass <ldelgass@retinalburn.net>
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*/
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#ifndef __MACH64_DRM_H__
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#define __MACH64_DRM_H__
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/* WARNING: If you change any of these defines, make sure to change the
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* defines in the Xserver file (mach64_sarea.h)
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*/
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#ifndef __MACH64_SAREA_DEFINES__
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#define __MACH64_SAREA_DEFINES__
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/* What needs to be changed for the current vertex buffer?
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* GH: We're going to be pedantic about this. We want the card to do as
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* little as possible, so let's avoid having it fetch a whole bunch of
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* register values that don't change all that often, if at all.
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*/
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#define MACH64_UPLOAD_DST_OFF_PITCH 0x0001
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#define MACH64_UPLOAD_Z_OFF_PITCH 0x0002
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#define MACH64_UPLOAD_Z_ALPHA_CNTL 0x0004
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#define MACH64_UPLOAD_SCALE_3D_CNTL 0x0008
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#define MACH64_UPLOAD_DP_FOG_CLR 0x0010
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#define MACH64_UPLOAD_DP_WRITE_MASK 0x0020
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#define MACH64_UPLOAD_DP_PIX_WIDTH 0x0040
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#define MACH64_UPLOAD_SETUP_CNTL 0x0080
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#define MACH64_UPLOAD_MISC 0x0100
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#define MACH64_UPLOAD_TEXTURE 0x0200
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#define MACH64_UPLOAD_TEX0IMAGE 0x0400
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#define MACH64_UPLOAD_TEX1IMAGE 0x0800
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#define MACH64_UPLOAD_CLIPRECTS 0x1000 /* handled client-side */
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#define MACH64_UPLOAD_CONTEXT 0x00ff
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#define MACH64_UPLOAD_ALL 0x1fff
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/* DMA buffer size
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*/
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#define MACH64_BUFFER_SIZE 16384
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/* Max number of swaps allowed on the ring
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* before the client must wait
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*/
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#define MACH64_MAX_QUEUED_FRAMES 3
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/* Byte offsets for host blit buffer data
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*/
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#define MACH64_HOSTDATA_BLIT_OFFSET 104
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/* Keep these small for testing.
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*/
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#define MACH64_NR_SAREA_CLIPRECTS 8
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#define MACH64_CARD_HEAP 0
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#define MACH64_AGP_HEAP 1
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#define MACH64_NR_TEX_HEAPS 2
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#define MACH64_NR_TEX_REGIONS 64
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#define MACH64_LOG_TEX_GRANULARITY 16
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#define MACH64_TEX_MAXLEVELS 1
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#define MACH64_NR_CONTEXT_REGS 15
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#define MACH64_NR_TEXTURE_REGS 4
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#endif /* __MACH64_SAREA_DEFINES__ */
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typedef struct {
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unsigned int dst_off_pitch;
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unsigned int z_off_pitch;
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unsigned int z_cntl;
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unsigned int alpha_tst_cntl;
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unsigned int scale_3d_cntl;
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unsigned int sc_left_right;
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unsigned int sc_top_bottom;
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unsigned int dp_fog_clr;
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unsigned int dp_write_mask;
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unsigned int dp_pix_width;
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unsigned int dp_mix;
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unsigned int dp_src;
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unsigned int clr_cmp_cntl;
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unsigned int gui_traj_cntl;
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unsigned int setup_cntl;
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unsigned int tex_size_pitch;
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unsigned int tex_cntl;
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unsigned int secondary_tex_off;
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unsigned int tex_offset;
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} drm_mach64_context_regs_t;
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typedef struct drm_mach64_sarea {
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/* The channel for communication of state information to the kernel
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* on firing a vertex dma buffer.
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*/
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drm_mach64_context_regs_t context_state;
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unsigned int dirty;
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unsigned int vertsize;
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/* The current cliprects, or a subset thereof.
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*/
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drm_clip_rect_t boxes[MACH64_NR_SAREA_CLIPRECTS];
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unsigned int nbox;
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/* Counters for client-side throttling of rendering clients.
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*/
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unsigned int frames_queued;
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/* Texture memory LRU.
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*/
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drm_tex_region_t tex_list[MACH64_NR_TEX_HEAPS][MACH64_NR_TEX_REGIONS+1];
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unsigned int tex_age[MACH64_NR_TEX_HEAPS];
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int ctx_owner;
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} drm_mach64_sarea_t;
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/* WARNING: If you change any of these defines, make sure to change the
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* defines in the Xserver file (mach64_common.h)
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*/
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/* Mach64 specific ioctls
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* The device specific ioctl range is 0x40 to 0x79.
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*/
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#define DRM_MACH64_INIT 0x00
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#define DRM_MACH64_IDLE 0x01
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#define DRM_MACH64_RESET 0x02
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#define DRM_MACH64_SWAP 0x03
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#define DRM_MACH64_CLEAR 0x04
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#define DRM_MACH64_VERTEX 0x05
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#define DRM_MACH64_BLIT 0x06
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#define DRM_MACH64_FLUSH 0x07
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#define DRM_MACH64_GETPARAM 0x08
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#define DRM_IOCTL_MACH64_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_MACH64_INIT, drm_mach64_init_t)
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#define DRM_IOCTL_MACH64_IDLE DRM_IO( DRM_COMMAND_BASE + DRM_MACH64_IDLE )
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#define DRM_IOCTL_MACH64_RESET DRM_IO( DRM_COMMAND_BASE + DRM_MACH64_RESET )
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#define DRM_IOCTL_MACH64_SWAP DRM_IO( DRM_COMMAND_BASE + DRM_MACH64_SWAP )
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#define DRM_IOCTL_MACH64_CLEAR DRM_IOW( DRM_COMMAND_BASE + DRM_MACH64_CLEAR, drm_mach64_clear_t)
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#define DRM_IOCTL_MACH64_VERTEX DRM_IOW( DRM_COMMAND_BASE + DRM_MACH64_VERTEX, drm_mach64_vertex_t)
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#define DRM_IOCTL_MACH64_BLIT DRM_IOW( DRM_COMMAND_BASE + DRM_MACH64_BLIT, drm_mach64_blit_t)
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#define DRM_IOCTL_MACH64_FLUSH DRM_IO( DRM_COMMAND_BASE + DRM_MACH64_FLUSH )
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#define DRM_IOCTL_MACH64_GETPARAM DRM_IOWR( DRM_COMMAND_BASE + DRM_MACH64_GETPARAM, drm_mach64_getparam_t)
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/* Buffer flags for clears
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*/
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#define MACH64_FRONT 0x1
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#define MACH64_BACK 0x2
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#define MACH64_DEPTH 0x4
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/* Primitive types for vertex buffers
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*/
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#define MACH64_PRIM_POINTS 0x00000000
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#define MACH64_PRIM_LINES 0x00000001
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#define MACH64_PRIM_LINE_LOOP 0x00000002
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#define MACH64_PRIM_LINE_STRIP 0x00000003
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#define MACH64_PRIM_TRIANGLES 0x00000004
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#define MACH64_PRIM_TRIANGLE_STRIP 0x00000005
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#define MACH64_PRIM_TRIANGLE_FAN 0x00000006
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#define MACH64_PRIM_QUADS 0x00000007
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#define MACH64_PRIM_QUAD_STRIP 0x00000008
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#define MACH64_PRIM_POLYGON 0x00000009
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typedef enum _drm_mach64_dma_mode_t {
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MACH64_MODE_DMA_ASYNC,
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MACH64_MODE_DMA_SYNC,
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MACH64_MODE_MMIO
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} drm_mach64_dma_mode_t;
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typedef struct drm_mach64_init {
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enum {
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DRM_MACH64_INIT_DMA = 0x01,
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DRM_MACH64_CLEANUP_DMA = 0x02
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} func;
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unsigned long sarea_priv_offset;
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int is_pci;
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drm_mach64_dma_mode_t dma_mode;
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unsigned int fb_bpp;
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unsigned int front_offset, front_pitch;
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unsigned int back_offset, back_pitch;
|
||||
|
||||
unsigned int depth_bpp;
|
||||
unsigned int depth_offset, depth_pitch;
|
||||
|
||||
unsigned long fb_offset;
|
||||
unsigned long mmio_offset;
|
||||
unsigned long ring_offset;
|
||||
unsigned long buffers_offset;
|
||||
unsigned long agp_textures_offset;
|
||||
} drm_mach64_init_t;
|
||||
|
||||
typedef struct drm_mach64_clear {
|
||||
unsigned int flags;
|
||||
int x, y, w, h;
|
||||
unsigned int clear_color;
|
||||
unsigned int clear_depth;
|
||||
} drm_mach64_clear_t;
|
||||
|
||||
typedef struct drm_mach64_vertex {
|
||||
int prim;
|
||||
void *buf; /* Address of vertex buffer */
|
||||
unsigned long used; /* Number of bytes in buffer */
|
||||
int discard; /* Client finished with buffer? */
|
||||
} drm_mach64_vertex_t;
|
||||
|
||||
typedef struct drm_mach64_blit {
|
||||
int idx;
|
||||
int pitch;
|
||||
int offset;
|
||||
int format;
|
||||
unsigned short x, y;
|
||||
unsigned short width, height;
|
||||
} drm_mach64_blit_t;
|
||||
|
||||
typedef struct drm_mach64_getparam {
|
||||
enum {
|
||||
MACH64_PARAM_FRAMES_QUEUED = 0x01,
|
||||
MACH64_PARAM_IRQ_NR = 0x02
|
||||
} param;
|
||||
void *value;
|
||||
} drm_mach64_getparam_t;
|
||||
|
||||
#endif
|
||||
1034
shared-core/mach64_drv.h
Normal file
1034
shared-core/mach64_drv.h
Normal file
File diff suppressed because it is too large
Load diff
130
shared-core/mach64_irq.c
Normal file
130
shared-core/mach64_irq.c
Normal file
|
|
@ -0,0 +1,130 @@
|
|||
/* mach64_irq.c -- IRQ handling for ATI Mach64 -*- linux-c -*-
|
||||
* Created: Tue Feb 25, 2003 by Leif Delgass, based on radeon_irq.c/r128_irq.c
|
||||
*
|
||||
* Copyright (C) The Weather Channel, Inc. 2002.
|
||||
* Copyright 2003 Leif Delgass
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* The Weather Channel (TM) funded Tungsten Graphics to develop the
|
||||
* initial release of the Radeon 8500 driver under the XFree86 license.
|
||||
* This notice must be preserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice (including the next
|
||||
* paragraph) shall be included in all copies or substantial portions of the
|
||||
* Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Authors:
|
||||
* Keith Whitwell <keith@tungstengraphics.com>
|
||||
* Eric Anholt <anholt@FreeBSD.org>
|
||||
* Leif Delgass <ldelgass@retinalburn.net>
|
||||
*/
|
||||
|
||||
#include "mach64.h"
|
||||
#include "drmP.h"
|
||||
#include "drm.h"
|
||||
#include "mach64_drm.h"
|
||||
#include "mach64_drv.h"
|
||||
|
||||
irqreturn_t DRM(irq_handler)( DRM_IRQ_ARGS )
|
||||
{
|
||||
drm_device_t *dev = (drm_device_t *) arg;
|
||||
drm_mach64_private_t *dev_priv =
|
||||
(drm_mach64_private_t *)dev->dev_private;
|
||||
int status;
|
||||
|
||||
status = MACH64_READ( MACH64_CRTC_INT_CNTL );
|
||||
|
||||
/* VBLANK interrupt */
|
||||
if (status & MACH64_CRTC_VBLANK_INT) {
|
||||
/* Mask off all interrupt ack bits before setting the ack bit, since
|
||||
* there may be other handlers outside the DRM.
|
||||
*
|
||||
* NOTE: On mach64, you need to keep the enable bits set when doing
|
||||
* the ack, despite what the docs say about not acking and enabling
|
||||
* in a single write.
|
||||
*/
|
||||
MACH64_WRITE( MACH64_CRTC_INT_CNTL, (status & ~MACH64_CRTC_INT_ACKS)
|
||||
| MACH64_CRTC_VBLANK_INT );
|
||||
|
||||
atomic_inc(&dev->vbl_received);
|
||||
DRM_WAKEUP(&dev->vbl_queue);
|
||||
DRM(vbl_send_signals)( dev );
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
return IRQ_NONE;
|
||||
}
|
||||
|
||||
int DRM(vblank_wait)(drm_device_t *dev, unsigned int *sequence)
|
||||
{
|
||||
unsigned int cur_vblank;
|
||||
int ret = 0;
|
||||
|
||||
/* Assume that the user has missed the current sequence number
|
||||
* by about a day rather than she wants to wait for years
|
||||
* using vertical blanks...
|
||||
*/
|
||||
DRM_WAIT_ON( ret, dev->vbl_queue, 3*DRM_HZ,
|
||||
( ( ( cur_vblank = atomic_read(&dev->vbl_received ) )
|
||||
- *sequence ) <= (1<<23) ) );
|
||||
|
||||
*sequence = cur_vblank;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* drm_dma.h hooks
|
||||
*/
|
||||
void DRM(driver_irq_preinstall)( drm_device_t *dev ) {
|
||||
drm_mach64_private_t *dev_priv =
|
||||
(drm_mach64_private_t *)dev->dev_private;
|
||||
|
||||
u32 status = MACH64_READ( MACH64_CRTC_INT_CNTL );
|
||||
|
||||
DRM_DEBUG("before install CRTC_INT_CTNL: 0x%08x\n", status );
|
||||
|
||||
/* Disable and clear VBLANK interrupt */
|
||||
MACH64_WRITE( MACH64_CRTC_INT_CNTL, (status & ~MACH64_CRTC_VBLANK_INT_EN)
|
||||
| MACH64_CRTC_VBLANK_INT );
|
||||
}
|
||||
|
||||
void DRM(driver_irq_postinstall)( drm_device_t *dev ) {
|
||||
drm_mach64_private_t *dev_priv =
|
||||
(drm_mach64_private_t *)dev->dev_private;
|
||||
|
||||
/* Turn on VBLANK interrupt */
|
||||
MACH64_WRITE( MACH64_CRTC_INT_CNTL, MACH64_READ( MACH64_CRTC_INT_CNTL )
|
||||
| MACH64_CRTC_VBLANK_INT_EN );
|
||||
|
||||
DRM_DEBUG("after install CRTC_INT_CTNL: 0x%08x\n", MACH64_READ( MACH64_CRTC_INT_CNTL ));
|
||||
|
||||
}
|
||||
|
||||
void DRM(driver_irq_uninstall)( drm_device_t *dev ) {
|
||||
drm_mach64_private_t *dev_priv =
|
||||
(drm_mach64_private_t *)dev->dev_private;
|
||||
if ( !dev_priv )
|
||||
return;
|
||||
|
||||
/* Disable and clear VBLANK interrupt */
|
||||
MACH64_WRITE( MACH64_CRTC_INT_CNTL,
|
||||
(MACH64_READ( MACH64_CRTC_INT_CNTL ) & ~MACH64_CRTC_VBLANK_INT_EN)
|
||||
| MACH64_CRTC_VBLANK_INT );
|
||||
|
||||
DRM_DEBUG("after uninstall CRTC_INT_CTNL: 0x%08x\n",
|
||||
MACH64_READ( MACH64_CRTC_INT_CNTL ));
|
||||
}
|
||||
897
shared-core/mach64_state.c
Normal file
897
shared-core/mach64_state.c
Normal file
|
|
@ -0,0 +1,897 @@
|
|||
/* mach64_state.c -- State support for mach64 (Rage Pro) driver -*- linux-c -*-
|
||||
* Created: Sun Dec 03 19:20:26 2000 by gareth@valinux.com
|
||||
*
|
||||
* Copyright 2000 Gareth Hughes
|
||||
* Copyright 2002-2003 Leif Delgass
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice (including the next
|
||||
* paragraph) shall be included in all copies or substantial portions of the
|
||||
* Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT OWNER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Authors:
|
||||
* Gareth Hughes <gareth@valinux.com>
|
||||
* Leif Delgass <ldelgass@retinalburn.net>
|
||||
* José Fonseca <j_r_fonseca@yahoo.co.uk>
|
||||
*/
|
||||
|
||||
#define __NO_VERSION__
|
||||
#include "mach64.h"
|
||||
#include "drmP.h"
|
||||
#include "drm.h"
|
||||
#include "mach64_drm.h"
|
||||
#include "mach64_drv.h"
|
||||
|
||||
|
||||
/* ================================================================
|
||||
* DMA hardware state programming functions
|
||||
*/
|
||||
|
||||
static void mach64_print_dirty( const char *msg, unsigned int flags )
|
||||
{
|
||||
DRM_DEBUG( "%s: (0x%x) %s%s%s%s%s%s%s%s%s%s%s%s\n",
|
||||
msg,
|
||||
flags,
|
||||
(flags & MACH64_UPLOAD_DST_OFF_PITCH) ? "dst_off_pitch, " : "",
|
||||
(flags & MACH64_UPLOAD_Z_ALPHA_CNTL) ? "z_alpha_cntl, " : "",
|
||||
(flags & MACH64_UPLOAD_SCALE_3D_CNTL) ? "scale_3d_cntl, " : "",
|
||||
(flags & MACH64_UPLOAD_DP_FOG_CLR) ? "dp_fog_clr, " : "",
|
||||
(flags & MACH64_UPLOAD_DP_WRITE_MASK) ? "dp_write_mask, " : "",
|
||||
(flags & MACH64_UPLOAD_DP_PIX_WIDTH) ? "dp_pix_width, " : "",
|
||||
(flags & MACH64_UPLOAD_SETUP_CNTL) ? "setup_cntl, " : "",
|
||||
(flags & MACH64_UPLOAD_MISC) ? "misc, " : "",
|
||||
(flags & MACH64_UPLOAD_TEXTURE) ? "texture, " : "",
|
||||
(flags & MACH64_UPLOAD_TEX0IMAGE) ? "tex0 image, " : "",
|
||||
(flags & MACH64_UPLOAD_TEX1IMAGE) ? "tex1 image, " : "",
|
||||
(flags & MACH64_UPLOAD_CLIPRECTS) ? "cliprects, " : "" );
|
||||
}
|
||||
|
||||
/* Mach64 doesn't have hardware cliprects, just one hardware scissor,
|
||||
* so the GL scissor is intersected with each cliprect here
|
||||
*/
|
||||
/* This function returns 0 on success, 1 for no intersection, and
|
||||
* negative for an error
|
||||
*/
|
||||
static int mach64_emit_cliprect( DRMFILE filp, drm_mach64_private_t *dev_priv,
|
||||
drm_clip_rect_t *box )
|
||||
{
|
||||
u32 sc_left_right, sc_top_bottom;
|
||||
drm_clip_rect_t scissor;
|
||||
drm_mach64_sarea_t *sarea_priv = dev_priv->sarea_priv;
|
||||
drm_mach64_context_regs_t *regs = &sarea_priv->context_state;
|
||||
DMALOCALS;
|
||||
|
||||
DRM_DEBUG( "%s: box=%p\n", __FUNCTION__, box );
|
||||
|
||||
/* Get GL scissor */
|
||||
/* FIXME: store scissor in SAREA as a cliprect instead of in
|
||||
* hardware format, or do intersection client-side
|
||||
*/
|
||||
scissor.x1 = regs->sc_left_right & 0xffff;
|
||||
scissor.x2 = (regs->sc_left_right & 0xffff0000) >> 16;
|
||||
scissor.y1 = regs->sc_top_bottom & 0xffff;
|
||||
scissor.y2 = (regs->sc_top_bottom & 0xffff0000) >> 16;
|
||||
|
||||
/* Intersect GL scissor with cliprect */
|
||||
if ( box->x1 > scissor.x1 ) scissor.x1 = box->x1;
|
||||
if ( box->y1 > scissor.y1 ) scissor.y1 = box->y1;
|
||||
if ( box->x2 < scissor.x2 ) scissor.x2 = box->x2;
|
||||
if ( box->y2 < scissor.y2 ) scissor.y2 = box->y2;
|
||||
/* positive return means skip */
|
||||
if ( scissor.x1 >= scissor.x2 ) return 1;
|
||||
if ( scissor.y1 >= scissor.y2 ) return 1;
|
||||
|
||||
DMAGETPTR( filp, dev_priv, 2 ); /* returns on failure to get buffer */
|
||||
|
||||
sc_left_right = ( (scissor.x1 << 0) | (scissor.x2 << 16) );
|
||||
sc_top_bottom = ( (scissor.y1 << 0) | (scissor.y2 << 16) );
|
||||
|
||||
DMAOUTREG( MACH64_SC_LEFT_RIGHT, sc_left_right );
|
||||
DMAOUTREG( MACH64_SC_TOP_BOTTOM, sc_top_bottom );
|
||||
|
||||
DMAADVANCE( dev_priv, 1 );
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static __inline__ int mach64_emit_state( DRMFILE filp, drm_mach64_private_t *dev_priv )
|
||||
{
|
||||
drm_mach64_sarea_t *sarea_priv = dev_priv->sarea_priv;
|
||||
drm_mach64_context_regs_t *regs = &sarea_priv->context_state;
|
||||
unsigned int dirty = sarea_priv->dirty;
|
||||
u32 offset = ((regs->tex_size_pitch & 0xf0) >> 2);
|
||||
DMALOCALS;
|
||||
|
||||
if ( MACH64_VERBOSE ) {
|
||||
mach64_print_dirty( __FUNCTION__, dirty );
|
||||
} else {
|
||||
DRM_DEBUG( "%s: dirty=0x%08x\n", __FUNCTION__, dirty );
|
||||
}
|
||||
|
||||
DMAGETPTR( filp, dev_priv, 17 ); /* returns on failure to get buffer */
|
||||
|
||||
if ( dirty & MACH64_UPLOAD_MISC ) {
|
||||
DMAOUTREG( MACH64_DP_MIX, regs->dp_mix );
|
||||
DMAOUTREG( MACH64_DP_SRC, regs->dp_src );
|
||||
DMAOUTREG( MACH64_CLR_CMP_CNTL, regs->clr_cmp_cntl );
|
||||
DMAOUTREG( MACH64_GUI_TRAJ_CNTL, regs->gui_traj_cntl );
|
||||
sarea_priv->dirty &= ~MACH64_UPLOAD_MISC;
|
||||
}
|
||||
|
||||
if ( dirty & MACH64_UPLOAD_DST_OFF_PITCH ) {
|
||||
DMAOUTREG( MACH64_DST_OFF_PITCH, regs->dst_off_pitch );
|
||||
sarea_priv->dirty &= ~MACH64_UPLOAD_DST_OFF_PITCH;
|
||||
}
|
||||
if ( dirty & MACH64_UPLOAD_Z_OFF_PITCH ) {
|
||||
DMAOUTREG( MACH64_Z_OFF_PITCH, regs->z_off_pitch );
|
||||
sarea_priv->dirty &= ~MACH64_UPLOAD_Z_OFF_PITCH;
|
||||
}
|
||||
if ( dirty & MACH64_UPLOAD_Z_ALPHA_CNTL ) {
|
||||
DMAOUTREG( MACH64_Z_CNTL, regs->z_cntl );
|
||||
DMAOUTREG( MACH64_ALPHA_TST_CNTL, regs->alpha_tst_cntl );
|
||||
sarea_priv->dirty &= ~MACH64_UPLOAD_Z_ALPHA_CNTL;
|
||||
}
|
||||
if ( dirty & MACH64_UPLOAD_SCALE_3D_CNTL ) {
|
||||
DMAOUTREG( MACH64_SCALE_3D_CNTL, regs->scale_3d_cntl );
|
||||
sarea_priv->dirty &= ~MACH64_UPLOAD_SCALE_3D_CNTL;
|
||||
}
|
||||
if ( dirty & MACH64_UPLOAD_DP_FOG_CLR ) {
|
||||
DMAOUTREG( MACH64_DP_FOG_CLR, regs->dp_fog_clr );
|
||||
sarea_priv->dirty &= ~MACH64_UPLOAD_DP_FOG_CLR;
|
||||
}
|
||||
if ( dirty & MACH64_UPLOAD_DP_WRITE_MASK ) {
|
||||
DMAOUTREG( MACH64_DP_WRITE_MASK, regs->dp_write_mask );
|
||||
sarea_priv->dirty &= ~MACH64_UPLOAD_DP_WRITE_MASK;
|
||||
}
|
||||
if ( dirty & MACH64_UPLOAD_DP_PIX_WIDTH ) {
|
||||
DMAOUTREG( MACH64_DP_PIX_WIDTH, regs->dp_pix_width );
|
||||
sarea_priv->dirty &= ~MACH64_UPLOAD_DP_PIX_WIDTH;
|
||||
}
|
||||
if ( dirty & MACH64_UPLOAD_SETUP_CNTL ) {
|
||||
DMAOUTREG( MACH64_SETUP_CNTL, regs->setup_cntl );
|
||||
sarea_priv->dirty &= ~MACH64_UPLOAD_SETUP_CNTL;
|
||||
}
|
||||
|
||||
if ( dirty & MACH64_UPLOAD_TEXTURE ) {
|
||||
DMAOUTREG( MACH64_TEX_SIZE_PITCH, regs->tex_size_pitch );
|
||||
DMAOUTREG( MACH64_TEX_CNTL, regs->tex_cntl );
|
||||
DMAOUTREG( MACH64_SECONDARY_TEX_OFF, regs->secondary_tex_off );
|
||||
DMAOUTREG( MACH64_TEX_0_OFF + offset, regs->tex_offset );
|
||||
sarea_priv->dirty &= ~MACH64_UPLOAD_TEXTURE;
|
||||
}
|
||||
|
||||
DMAADVANCE( dev_priv, 1 );
|
||||
|
||||
sarea_priv->dirty &= MACH64_UPLOAD_CLIPRECTS;
|
||||
|
||||
return 0;
|
||||
|
||||
}
|
||||
|
||||
|
||||
/* ================================================================
|
||||
* DMA command dispatch functions
|
||||
*/
|
||||
|
||||
static int mach64_dma_dispatch_clear( DRMFILE filp, drm_device_t *dev,
|
||||
unsigned int flags,
|
||||
int cx, int cy, int cw, int ch,
|
||||
unsigned int clear_color,
|
||||
unsigned int clear_depth )
|
||||
{
|
||||
drm_mach64_private_t *dev_priv = dev->dev_private;
|
||||
drm_mach64_sarea_t *sarea_priv = dev_priv->sarea_priv;
|
||||
drm_mach64_context_regs_t *ctx = &sarea_priv->context_state;
|
||||
int nbox = sarea_priv->nbox;
|
||||
drm_clip_rect_t *pbox = sarea_priv->boxes;
|
||||
u32 fb_bpp, depth_bpp;
|
||||
int i;
|
||||
DMALOCALS;
|
||||
|
||||
DRM_DEBUG( "%s\n", __FUNCTION__ );
|
||||
|
||||
switch ( dev_priv->fb_bpp ) {
|
||||
case 16:
|
||||
fb_bpp = MACH64_DATATYPE_RGB565;
|
||||
break;
|
||||
case 32:
|
||||
fb_bpp = MACH64_DATATYPE_ARGB8888;
|
||||
break;
|
||||
default:
|
||||
return DRM_ERR(EINVAL);
|
||||
}
|
||||
switch ( dev_priv->depth_bpp ) {
|
||||
case 16:
|
||||
depth_bpp = MACH64_DATATYPE_RGB565;
|
||||
break;
|
||||
case 24:
|
||||
case 32:
|
||||
depth_bpp = MACH64_DATATYPE_ARGB8888;
|
||||
break;
|
||||
default:
|
||||
return DRM_ERR(EINVAL);
|
||||
}
|
||||
|
||||
if ( !nbox )
|
||||
return 0;
|
||||
|
||||
DMAGETPTR( filp, dev_priv, nbox * 31 ); /* returns on failure to get buffer */
|
||||
|
||||
for ( i = 0 ; i < nbox ; i++ ) {
|
||||
int x = pbox[i].x1;
|
||||
int y = pbox[i].y1;
|
||||
int w = pbox[i].x2 - x;
|
||||
int h = pbox[i].y2 - y;
|
||||
|
||||
DRM_DEBUG( "dispatch clear %d,%d-%d,%d flags 0x%x\n",
|
||||
pbox[i].x1, pbox[i].y1,
|
||||
pbox[i].x2, pbox[i].y2, flags );
|
||||
|
||||
if ( flags & (MACH64_FRONT | MACH64_BACK) ) {
|
||||
/* Setup for color buffer clears
|
||||
*/
|
||||
|
||||
DMAOUTREG( MACH64_Z_CNTL, 0 );
|
||||
DMAOUTREG( MACH64_SCALE_3D_CNTL, 0 );
|
||||
|
||||
DMAOUTREG( MACH64_SC_LEFT_RIGHT, ctx->sc_left_right );
|
||||
DMAOUTREG( MACH64_SC_TOP_BOTTOM, ctx->sc_top_bottom );
|
||||
|
||||
DMAOUTREG( MACH64_CLR_CMP_CNTL, 0 );
|
||||
DMAOUTREG( MACH64_GUI_TRAJ_CNTL,
|
||||
(MACH64_DST_X_LEFT_TO_RIGHT |
|
||||
MACH64_DST_Y_TOP_TO_BOTTOM) );
|
||||
|
||||
DMAOUTREG( MACH64_DP_PIX_WIDTH, ((fb_bpp << 0) |
|
||||
(fb_bpp << 4) |
|
||||
(fb_bpp << 8) |
|
||||
(fb_bpp << 16) |
|
||||
(fb_bpp << 28)) );
|
||||
|
||||
DMAOUTREG( MACH64_DP_FRGD_CLR, clear_color );
|
||||
DMAOUTREG( MACH64_DP_WRITE_MASK, ctx->dp_write_mask );
|
||||
DMAOUTREG( MACH64_DP_MIX, (MACH64_BKGD_MIX_D |
|
||||
MACH64_FRGD_MIX_S) );
|
||||
DMAOUTREG( MACH64_DP_SRC, (MACH64_BKGD_SRC_FRGD_CLR |
|
||||
MACH64_FRGD_SRC_FRGD_CLR |
|
||||
MACH64_MONO_SRC_ONE) );
|
||||
|
||||
|
||||
}
|
||||
|
||||
if ( flags & MACH64_FRONT ) {
|
||||
|
||||
DMAOUTREG( MACH64_DST_OFF_PITCH,
|
||||
dev_priv->front_offset_pitch );
|
||||
DMAOUTREG( MACH64_DST_X_Y,
|
||||
(y << 16) | x );
|
||||
DMAOUTREG( MACH64_DST_WIDTH_HEIGHT,
|
||||
(h << 16) | w );
|
||||
|
||||
}
|
||||
|
||||
if ( flags & MACH64_BACK ) {
|
||||
|
||||
DMAOUTREG( MACH64_DST_OFF_PITCH,
|
||||
dev_priv->back_offset_pitch );
|
||||
DMAOUTREG( MACH64_DST_X_Y,
|
||||
(y << 16) | x );
|
||||
DMAOUTREG( MACH64_DST_WIDTH_HEIGHT,
|
||||
(h << 16) | w );
|
||||
|
||||
}
|
||||
|
||||
if ( flags & MACH64_DEPTH ) {
|
||||
/* Setup for depth buffer clear
|
||||
*/
|
||||
DMAOUTREG( MACH64_Z_CNTL, 0 );
|
||||
DMAOUTREG( MACH64_SCALE_3D_CNTL, 0 );
|
||||
|
||||
DMAOUTREG( MACH64_SC_LEFT_RIGHT, ctx->sc_left_right );
|
||||
DMAOUTREG( MACH64_SC_TOP_BOTTOM, ctx->sc_top_bottom );
|
||||
|
||||
DMAOUTREG( MACH64_CLR_CMP_CNTL, 0 );
|
||||
DMAOUTREG( MACH64_GUI_TRAJ_CNTL,
|
||||
(MACH64_DST_X_LEFT_TO_RIGHT |
|
||||
MACH64_DST_Y_TOP_TO_BOTTOM) );
|
||||
|
||||
DMAOUTREG( MACH64_DP_PIX_WIDTH, ((depth_bpp << 0) |
|
||||
(depth_bpp << 4) |
|
||||
(depth_bpp << 8) |
|
||||
(depth_bpp << 16) |
|
||||
(depth_bpp << 28)) );
|
||||
|
||||
DMAOUTREG( MACH64_DP_FRGD_CLR, clear_depth );
|
||||
DMAOUTREG( MACH64_DP_WRITE_MASK, 0xffffffff );
|
||||
DMAOUTREG( MACH64_DP_MIX, (MACH64_BKGD_MIX_D |
|
||||
MACH64_FRGD_MIX_S) );
|
||||
DMAOUTREG( MACH64_DP_SRC, (MACH64_BKGD_SRC_FRGD_CLR |
|
||||
MACH64_FRGD_SRC_FRGD_CLR |
|
||||
MACH64_MONO_SRC_ONE) );
|
||||
|
||||
DMAOUTREG( MACH64_DST_OFF_PITCH,
|
||||
dev_priv->depth_offset_pitch );
|
||||
DMAOUTREG( MACH64_DST_X_Y,
|
||||
(y << 16) | x );
|
||||
DMAOUTREG( MACH64_DST_WIDTH_HEIGHT,
|
||||
(h << 16) | w );
|
||||
}
|
||||
}
|
||||
|
||||
DMAADVANCE( dev_priv, 1 );
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mach64_dma_dispatch_swap( DRMFILE filp, drm_device_t *dev )
|
||||
{
|
||||
drm_mach64_private_t *dev_priv = dev->dev_private;
|
||||
drm_mach64_sarea_t *sarea_priv = dev_priv->sarea_priv;
|
||||
int nbox = sarea_priv->nbox;
|
||||
drm_clip_rect_t *pbox = sarea_priv->boxes;
|
||||
u32 fb_bpp;
|
||||
int i;
|
||||
DMALOCALS;
|
||||
|
||||
DRM_DEBUG( "%s\n", __FUNCTION__ );
|
||||
|
||||
switch ( dev_priv->fb_bpp ) {
|
||||
case 16:
|
||||
fb_bpp = MACH64_DATATYPE_RGB565;
|
||||
break;
|
||||
case 32:
|
||||
default:
|
||||
fb_bpp = MACH64_DATATYPE_ARGB8888;
|
||||
break;
|
||||
}
|
||||
|
||||
if ( !nbox )
|
||||
return 0;
|
||||
|
||||
DMAGETPTR( filp, dev_priv, 13 + nbox * 4 ); /* returns on failure to get buffer */
|
||||
|
||||
DMAOUTREG( MACH64_Z_CNTL, 0 );
|
||||
DMAOUTREG( MACH64_SCALE_3D_CNTL, 0 );
|
||||
|
||||
DMAOUTREG( MACH64_SC_LEFT_RIGHT, 0 | ( 8191 << 16 ) ); /* no scissor */
|
||||
DMAOUTREG( MACH64_SC_TOP_BOTTOM, 0 | ( 16383 << 16 ) );
|
||||
|
||||
DMAOUTREG( MACH64_CLR_CMP_CNTL, 0 );
|
||||
DMAOUTREG( MACH64_GUI_TRAJ_CNTL, (MACH64_DST_X_LEFT_TO_RIGHT |
|
||||
MACH64_DST_Y_TOP_TO_BOTTOM) );
|
||||
|
||||
DMAOUTREG( MACH64_DP_PIX_WIDTH, ((fb_bpp << 0) |
|
||||
(fb_bpp << 4) |
|
||||
(fb_bpp << 8) |
|
||||
(fb_bpp << 16) |
|
||||
(fb_bpp << 28)) );
|
||||
|
||||
DMAOUTREG( MACH64_DP_WRITE_MASK, 0xffffffff );
|
||||
DMAOUTREG( MACH64_DP_MIX, (MACH64_BKGD_MIX_D |
|
||||
MACH64_FRGD_MIX_S) );
|
||||
DMAOUTREG( MACH64_DP_SRC, (MACH64_BKGD_SRC_BKGD_CLR |
|
||||
MACH64_FRGD_SRC_BLIT |
|
||||
MACH64_MONO_SRC_ONE) );
|
||||
|
||||
DMAOUTREG( MACH64_SRC_OFF_PITCH, dev_priv->back_offset_pitch );
|
||||
DMAOUTREG( MACH64_DST_OFF_PITCH, dev_priv->front_offset_pitch );
|
||||
|
||||
for ( i = 0 ; i < nbox ; i++ ) {
|
||||
int x = pbox[i].x1;
|
||||
int y = pbox[i].y1;
|
||||
int w = pbox[i].x2 - x;
|
||||
int h = pbox[i].y2 - y;
|
||||
|
||||
DRM_DEBUG( "dispatch swap %d,%d-%d,%d\n",
|
||||
pbox[i].x1, pbox[i].y1,
|
||||
pbox[i].x2, pbox[i].y2 );
|
||||
|
||||
DMAOUTREG( MACH64_SRC_WIDTH1, w );
|
||||
DMAOUTREG( MACH64_SRC_Y_X, (x << 16) | y );
|
||||
DMAOUTREG( MACH64_DST_Y_X, (x << 16) | y );
|
||||
DMAOUTREG( MACH64_DST_WIDTH_HEIGHT, (h << 16) | w );
|
||||
|
||||
}
|
||||
|
||||
DMAADVANCE( dev_priv, 1 );
|
||||
|
||||
if (dev_priv->driver_mode == MACH64_MODE_DMA_ASYNC) {
|
||||
for (i = 0; i < MACH64_MAX_QUEUED_FRAMES - 1; i++) {
|
||||
dev_priv->frame_ofs[i] = dev_priv->frame_ofs[i+1];
|
||||
}
|
||||
dev_priv->frame_ofs[i] = GETRINGOFFSET();
|
||||
|
||||
dev_priv->sarea_priv->frames_queued++;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mach64_do_get_frames_queued( drm_mach64_private_t *dev_priv )
|
||||
{
|
||||
drm_mach64_descriptor_ring_t *ring = &dev_priv->ring;
|
||||
drm_mach64_sarea_t *sarea_priv = dev_priv->sarea_priv;
|
||||
int i, start;
|
||||
u32 head, tail, ofs;
|
||||
|
||||
DRM_DEBUG( "%s\n", __FUNCTION__ );
|
||||
|
||||
if (sarea_priv->frames_queued == 0)
|
||||
return 0;
|
||||
|
||||
tail = ring->tail;
|
||||
mach64_ring_tick( dev_priv, ring );
|
||||
head = ring->head;
|
||||
|
||||
start = ( MACH64_MAX_QUEUED_FRAMES -
|
||||
DRM_MIN(MACH64_MAX_QUEUED_FRAMES, sarea_priv->frames_queued) );
|
||||
|
||||
if ( head == tail ) {
|
||||
sarea_priv->frames_queued = 0;
|
||||
for (i = start; i < MACH64_MAX_QUEUED_FRAMES; i++) {
|
||||
dev_priv->frame_ofs[i] = ~0;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
for ( i = start; i < MACH64_MAX_QUEUED_FRAMES; i++ ) {
|
||||
ofs = dev_priv->frame_ofs[i];
|
||||
DRM_DEBUG( "frame_ofs[%d] ofs: %d\n", i, ofs );
|
||||
if ( ofs == ~0 ||
|
||||
( head < tail && (ofs < head || ofs >= tail) ) ||
|
||||
( head > tail && (ofs < head && ofs >= tail) ) ) {
|
||||
sarea_priv->frames_queued = (MACH64_MAX_QUEUED_FRAMES - 1) - i;
|
||||
dev_priv->frame_ofs[i] = ~0;
|
||||
}
|
||||
}
|
||||
|
||||
return sarea_priv->frames_queued;
|
||||
}
|
||||
|
||||
/* Copy and verify a client submited buffer.
|
||||
* FIXME: Make an assembly optimized version
|
||||
*/
|
||||
static __inline__ int copy_and_verify_from_user( u32 *to, const u32 *from, unsigned long bytes )
|
||||
{
|
||||
unsigned long n = bytes; /* dwords remaining in buffer */
|
||||
|
||||
if ( DRM_VERIFYAREA_READ( from, n ) ) {
|
||||
DRM_ERROR( "%s: verify_area\n", __FUNCTION__ );
|
||||
return DRM_ERR(EFAULT);
|
||||
}
|
||||
|
||||
n >>= 2;
|
||||
|
||||
while ( n > 1 ) {
|
||||
u32 data, reg, count;
|
||||
|
||||
if ( DRM_GET_USER_UNCHECKED( data, from++ ) ) {
|
||||
DRM_ERROR( "%s: get_user\n", __FUNCTION__ );
|
||||
return DRM_ERR(EFAULT);
|
||||
}
|
||||
|
||||
n--;
|
||||
|
||||
reg = le32_to_cpu(data);
|
||||
count = (reg >> 16) + 1;
|
||||
if( count <= n ) {
|
||||
n -= count;
|
||||
reg &= 0xffff;
|
||||
|
||||
/* This is an exact match of Mach64's Setup Engine registers,
|
||||
* excluding SETUP_CNTL (1_C1).
|
||||
*/
|
||||
if( (reg >= 0x0190 && reg < 0x01c1) ||
|
||||
(reg >= 0x01ca && reg <= 0x01cf) ) {
|
||||
*to++ = data;
|
||||
if ( DRM_COPY_FROM_USER_UNCHECKED( to, from, count << 2 ) ) {
|
||||
DRM_ERROR( "%s: copy_from_user\n", __FUNCTION__ );
|
||||
return DRM_ERR(EFAULT);
|
||||
}
|
||||
to += count;
|
||||
} else {
|
||||
DRM_ERROR( "%s: Got bad command: 0x%04x\n", __FUNCTION__, reg );
|
||||
return DRM_ERR(EACCES);
|
||||
}
|
||||
|
||||
from += count;
|
||||
} else {
|
||||
DRM_ERROR( "%s: Got bad command count(=%u) dwords remaining=%lu\n",
|
||||
__FUNCTION__, count, n );
|
||||
return DRM_ERR(EINVAL);
|
||||
}
|
||||
}
|
||||
|
||||
if (n == 0)
|
||||
return 0;
|
||||
else {
|
||||
DRM_ERROR( "%s: Bad buf->used(=%lu)\n", __FUNCTION__, bytes );
|
||||
return DRM_ERR(EINVAL);
|
||||
}
|
||||
}
|
||||
|
||||
static int mach64_dma_dispatch_vertex( DRMFILE filp, drm_device_t *dev, int prim, void *buf,
|
||||
unsigned long used, int discard )
|
||||
{
|
||||
drm_mach64_private_t *dev_priv = dev->dev_private;
|
||||
drm_mach64_sarea_t *sarea_priv = dev_priv->sarea_priv;
|
||||
drm_buf_t *copy_buf;
|
||||
int done = 0;
|
||||
int verify_ret = 0;
|
||||
DMALOCALS;
|
||||
|
||||
DRM_DEBUG( "%s: buf=%p used=%lu nbox=%d\n",
|
||||
__FUNCTION__, buf, used, sarea_priv->nbox );
|
||||
|
||||
if ( used ) {
|
||||
int ret = 0;
|
||||
int i = 0;
|
||||
|
||||
copy_buf = mach64_freelist_get( dev_priv );
|
||||
if (copy_buf == NULL) {
|
||||
DRM_ERROR("%s: couldn't get buffer in DMAGETPTR\n",
|
||||
__FUNCTION__ );
|
||||
return DRM_ERR(EAGAIN);
|
||||
}
|
||||
|
||||
if ( (verify_ret =
|
||||
copy_and_verify_from_user( GETBUFPTR( copy_buf ), buf, used )) == 0 ) {
|
||||
|
||||
copy_buf->used = used;
|
||||
|
||||
DMASETPTR( copy_buf );
|
||||
|
||||
if ( sarea_priv->dirty & ~MACH64_UPLOAD_CLIPRECTS ) {
|
||||
ret = mach64_emit_state( filp, dev_priv );
|
||||
if (ret < 0) return ret;
|
||||
}
|
||||
|
||||
do {
|
||||
/* Emit the next cliprect */
|
||||
if ( i < sarea_priv->nbox ) {
|
||||
ret = mach64_emit_cliprect(filp, dev_priv,
|
||||
&sarea_priv->boxes[i]);
|
||||
if ( ret < 0 ) {
|
||||
/* failed to get buffer */
|
||||
return ret;
|
||||
} else if ( ret != 0 ) {
|
||||
/* null intersection with scissor */
|
||||
continue;
|
||||
}
|
||||
}
|
||||
if ((i >= sarea_priv->nbox - 1))
|
||||
done = 1;
|
||||
|
||||
/* Add the buffer to the DMA queue */
|
||||
DMAADVANCE( dev_priv, done );
|
||||
|
||||
} while ( ++i < sarea_priv->nbox );
|
||||
}
|
||||
|
||||
if (copy_buf->pending && !done) {
|
||||
DMADISCARDBUF();
|
||||
} else if (!done) {
|
||||
/* This buffer wasn't used (no cliprects or verify failed), so place it back
|
||||
* on the free list
|
||||
*/
|
||||
struct list_head *ptr;
|
||||
drm_mach64_freelist_t *entry;
|
||||
#if MACH64_EXTRA_CHECKING
|
||||
list_for_each(ptr, &dev_priv->pending) {
|
||||
entry = list_entry(ptr, drm_mach64_freelist_t, list);
|
||||
if (copy_buf == entry->buf) {
|
||||
DRM_ERROR( "%s: Trying to release a pending buf\n",
|
||||
__FUNCTION__ );
|
||||
return DRM_ERR(EFAULT);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
ptr = dev_priv->placeholders.next;
|
||||
entry = list_entry(ptr, drm_mach64_freelist_t, list);
|
||||
copy_buf->pending = 0;
|
||||
copy_buf->used = 0;
|
||||
entry->buf = copy_buf;
|
||||
entry->discard = 1;
|
||||
list_del(ptr);
|
||||
list_add_tail(ptr, &dev_priv->free_list);
|
||||
}
|
||||
}
|
||||
|
||||
sarea_priv->dirty &= ~MACH64_UPLOAD_CLIPRECTS;
|
||||
sarea_priv->nbox = 0;
|
||||
|
||||
return verify_ret;
|
||||
}
|
||||
|
||||
|
||||
static int mach64_dma_dispatch_blit( DRMFILE filp, drm_device_t *dev,
|
||||
drm_mach64_blit_t *blit )
|
||||
{
|
||||
drm_mach64_private_t *dev_priv = dev->dev_private;
|
||||
drm_device_dma_t *dma = dev->dma;
|
||||
int dword_shift, dwords;
|
||||
drm_buf_t *buf;
|
||||
DMALOCALS;
|
||||
|
||||
/* The compiler won't optimize away a division by a variable,
|
||||
* even if the only legal values are powers of two. Thus, we'll
|
||||
* use a shift instead.
|
||||
*/
|
||||
switch ( blit->format ) {
|
||||
case MACH64_DATATYPE_ARGB8888:
|
||||
dword_shift = 0;
|
||||
break;
|
||||
case MACH64_DATATYPE_ARGB1555:
|
||||
case MACH64_DATATYPE_RGB565:
|
||||
case MACH64_DATATYPE_VYUY422:
|
||||
case MACH64_DATATYPE_YVYU422:
|
||||
case MACH64_DATATYPE_ARGB4444:
|
||||
dword_shift = 1;
|
||||
break;
|
||||
case MACH64_DATATYPE_CI8:
|
||||
case MACH64_DATATYPE_RGB8:
|
||||
dword_shift = 2;
|
||||
break;
|
||||
default:
|
||||
DRM_ERROR( "invalid blit format %d\n", blit->format );
|
||||
return DRM_ERR(EINVAL);
|
||||
}
|
||||
|
||||
/* Dispatch the blit buffer.
|
||||
*/
|
||||
buf = dma->buflist[blit->idx];
|
||||
|
||||
if ( buf->filp != filp ) {
|
||||
DRM_ERROR( "process %d (filp %p) using buffer with filp %p\n",
|
||||
DRM_CURRENTPID, filp, buf->filp );
|
||||
return DRM_ERR(EINVAL);
|
||||
}
|
||||
|
||||
if ( buf->pending ) {
|
||||
DRM_ERROR( "sending pending buffer %d\n", blit->idx );
|
||||
return DRM_ERR(EINVAL);
|
||||
}
|
||||
|
||||
/* Set buf->used to the bytes of blit data based on the blit dimensions
|
||||
* and verify the size. When the setup is emitted to the buffer with
|
||||
* the DMA* macros below, buf->used is incremented to include the bytes
|
||||
* used for setup as well as the blit data.
|
||||
*/
|
||||
dwords = (blit->width * blit->height) >> dword_shift;
|
||||
buf->used = dwords << 2;
|
||||
if ( buf->used <= 0 ||
|
||||
buf->used > MACH64_BUFFER_SIZE - MACH64_HOSTDATA_BLIT_OFFSET ) {
|
||||
DRM_ERROR( "Invalid blit size: %d bytes\n", buf->used );
|
||||
return DRM_ERR(EINVAL);
|
||||
}
|
||||
|
||||
/* FIXME: Use a last buffer flag and reduce the state emitted for subsequent,
|
||||
* continuation buffers?
|
||||
*/
|
||||
|
||||
/* Blit via BM_HOSTDATA (gui-master) - like HOST_DATA[0-15], but doesn't require
|
||||
* a register command every 16 dwords. State setup is added at the start of the
|
||||
* buffer -- the client leaves space for this based on MACH64_HOSTDATA_BLIT_OFFSET
|
||||
*/
|
||||
DMASETPTR( buf );
|
||||
|
||||
DMAOUTREG( MACH64_Z_CNTL, 0 );
|
||||
DMAOUTREG( MACH64_SCALE_3D_CNTL, 0 );
|
||||
|
||||
DMAOUTREG( MACH64_SC_LEFT_RIGHT, 0 | ( 8191 << 16 ) ); /* no scissor */
|
||||
DMAOUTREG( MACH64_SC_TOP_BOTTOM, 0 | ( 16383 << 16 ) );
|
||||
|
||||
DMAOUTREG( MACH64_CLR_CMP_CNTL, 0 ); /* disable */
|
||||
DMAOUTREG( MACH64_GUI_TRAJ_CNTL,
|
||||
MACH64_DST_X_LEFT_TO_RIGHT
|
||||
| MACH64_DST_Y_TOP_TO_BOTTOM );
|
||||
|
||||
DMAOUTREG( MACH64_DP_PIX_WIDTH,
|
||||
( blit->format << 0 ) /* dst pix width */
|
||||
| ( blit->format << 4 ) /* composite pix width */
|
||||
| ( blit->format << 8 ) /* src pix width */
|
||||
| ( blit->format << 16 ) /* host data pix width */
|
||||
| ( blit->format << 28 ) /* scaler/3D pix width */
|
||||
);
|
||||
|
||||
DMAOUTREG( MACH64_DP_WRITE_MASK, 0xffffffff ); /* enable all planes */
|
||||
DMAOUTREG( MACH64_DP_MIX,
|
||||
MACH64_BKGD_MIX_D
|
||||
| MACH64_FRGD_MIX_S );
|
||||
DMAOUTREG( MACH64_DP_SRC,
|
||||
MACH64_BKGD_SRC_BKGD_CLR
|
||||
| MACH64_FRGD_SRC_HOST
|
||||
| MACH64_MONO_SRC_ONE );
|
||||
|
||||
DMAOUTREG( MACH64_DST_OFF_PITCH, (blit->pitch << 22) | (blit->offset >> 3) );
|
||||
DMAOUTREG( MACH64_DST_X_Y, (blit->y << 16) | blit->x );
|
||||
DMAOUTREG( MACH64_DST_WIDTH_HEIGHT, (blit->height << 16) | blit->width );
|
||||
|
||||
DRM_DEBUG( "%s: %d bytes\n", __FUNCTION__, buf->used );
|
||||
|
||||
/* Add the buffer to the queue */
|
||||
DMAADVANCEHOSTDATA( dev_priv );
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* ================================================================
|
||||
* IOCTL functions
|
||||
*/
|
||||
|
||||
int mach64_dma_clear( DRM_IOCTL_ARGS )
|
||||
{
|
||||
DRM_DEVICE;
|
||||
drm_mach64_private_t *dev_priv = dev->dev_private;
|
||||
drm_mach64_sarea_t *sarea_priv = dev_priv->sarea_priv;
|
||||
drm_mach64_clear_t clear;
|
||||
int ret;
|
||||
|
||||
DRM_DEBUG( "%s: pid=%d\n", __FUNCTION__, DRM_CURRENTPID );
|
||||
|
||||
LOCK_TEST_WITH_RETURN( dev, filp );
|
||||
|
||||
DRM_COPY_FROM_USER_IOCTL( clear, (drm_mach64_clear_t *)data,
|
||||
sizeof(clear) );
|
||||
|
||||
if ( sarea_priv->nbox > MACH64_NR_SAREA_CLIPRECTS )
|
||||
sarea_priv->nbox = MACH64_NR_SAREA_CLIPRECTS;
|
||||
|
||||
ret = mach64_dma_dispatch_clear( filp, dev, clear.flags,
|
||||
clear.x, clear.y, clear.w, clear.h,
|
||||
clear.clear_color, clear.clear_depth );
|
||||
|
||||
/* Make sure we restore the 3D state next time.
|
||||
*/
|
||||
sarea_priv->dirty |= (MACH64_UPLOAD_CONTEXT |
|
||||
MACH64_UPLOAD_MISC);
|
||||
return ret;
|
||||
}
|
||||
|
||||
int mach64_dma_swap( DRM_IOCTL_ARGS )
|
||||
{
|
||||
DRM_DEVICE;
|
||||
drm_mach64_private_t *dev_priv = dev->dev_private;
|
||||
drm_mach64_sarea_t *sarea_priv = dev_priv->sarea_priv;
|
||||
int ret;
|
||||
|
||||
DRM_DEBUG( "%s: pid=%d\n", __FUNCTION__, DRM_CURRENTPID );
|
||||
|
||||
LOCK_TEST_WITH_RETURN( dev, filp );
|
||||
|
||||
if ( sarea_priv->nbox > MACH64_NR_SAREA_CLIPRECTS )
|
||||
sarea_priv->nbox = MACH64_NR_SAREA_CLIPRECTS;
|
||||
|
||||
ret = mach64_dma_dispatch_swap( filp, dev );
|
||||
|
||||
/* Make sure we restore the 3D state next time.
|
||||
*/
|
||||
sarea_priv->dirty |= (MACH64_UPLOAD_CONTEXT |
|
||||
MACH64_UPLOAD_MISC);
|
||||
return ret;
|
||||
}
|
||||
|
||||
int mach64_dma_vertex( DRM_IOCTL_ARGS )
|
||||
{
|
||||
DRM_DEVICE;
|
||||
drm_mach64_private_t *dev_priv = dev->dev_private;
|
||||
drm_mach64_sarea_t *sarea_priv = dev_priv->sarea_priv;
|
||||
drm_mach64_vertex_t vertex;
|
||||
|
||||
LOCK_TEST_WITH_RETURN( dev, filp );
|
||||
|
||||
if ( !dev_priv ) {
|
||||
DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ );
|
||||
return DRM_ERR(EINVAL);
|
||||
}
|
||||
|
||||
DRM_COPY_FROM_USER_IOCTL( vertex, (drm_mach64_vertex_t *)data,
|
||||
sizeof(vertex) );
|
||||
|
||||
DRM_DEBUG( "%s: pid=%d buf=%p used=%lu discard=%d\n",
|
||||
__FUNCTION__, DRM_CURRENTPID,
|
||||
vertex.buf, vertex.used, vertex.discard );
|
||||
|
||||
if ( vertex.prim < 0 ||
|
||||
vertex.prim > MACH64_PRIM_POLYGON ) {
|
||||
DRM_ERROR( "buffer prim %d\n", vertex.prim );
|
||||
return DRM_ERR(EINVAL);
|
||||
}
|
||||
|
||||
if ( vertex.used > MACH64_BUFFER_SIZE || (vertex.used & 3) != 0) {
|
||||
DRM_ERROR( "Invalid vertex buffer size: %lu bytes\n", vertex.used );
|
||||
return DRM_ERR(EINVAL);
|
||||
}
|
||||
|
||||
if ( sarea_priv->nbox > MACH64_NR_SAREA_CLIPRECTS )
|
||||
sarea_priv->nbox = MACH64_NR_SAREA_CLIPRECTS;
|
||||
|
||||
return mach64_dma_dispatch_vertex( filp, dev, vertex.prim, vertex.buf,
|
||||
vertex.used, vertex.discard );
|
||||
}
|
||||
|
||||
int mach64_dma_blit( DRM_IOCTL_ARGS )
|
||||
{
|
||||
DRM_DEVICE;
|
||||
drm_device_dma_t *dma = dev->dma;
|
||||
drm_mach64_private_t *dev_priv = dev->dev_private;
|
||||
drm_mach64_sarea_t *sarea_priv = dev_priv->sarea_priv;
|
||||
drm_mach64_blit_t blit;
|
||||
int ret;
|
||||
|
||||
LOCK_TEST_WITH_RETURN( dev, filp );
|
||||
|
||||
DRM_COPY_FROM_USER_IOCTL( blit, (drm_mach64_blit_t *)data,
|
||||
sizeof(blit) );
|
||||
|
||||
DRM_DEBUG( "%s: pid=%d index=%d\n",
|
||||
__FUNCTION__, DRM_CURRENTPID, blit.idx );
|
||||
|
||||
if ( blit.idx < 0 || blit.idx >= dma->buf_count ) {
|
||||
DRM_ERROR( "buffer index %d (of %d max)\n",
|
||||
blit.idx, dma->buf_count - 1 );
|
||||
return DRM_ERR(EINVAL);
|
||||
}
|
||||
|
||||
ret = mach64_dma_dispatch_blit( filp, dev, &blit );
|
||||
|
||||
/* Make sure we restore the 3D state next time.
|
||||
*/
|
||||
sarea_priv->dirty |= (MACH64_UPLOAD_CONTEXT |
|
||||
MACH64_UPLOAD_MISC |
|
||||
MACH64_UPLOAD_CLIPRECTS);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
int mach64_get_param( DRM_IOCTL_ARGS )
|
||||
{
|
||||
DRM_DEVICE;
|
||||
drm_mach64_private_t *dev_priv = dev->dev_private;
|
||||
drm_mach64_getparam_t param;
|
||||
int value;
|
||||
|
||||
DRM_DEBUG( "%s\n", __FUNCTION__ );
|
||||
|
||||
if ( !dev_priv ) {
|
||||
DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ );
|
||||
return DRM_ERR(EINVAL);
|
||||
}
|
||||
|
||||
DRM_COPY_FROM_USER_IOCTL( param, (drm_mach64_getparam_t *)data,
|
||||
sizeof(param) );
|
||||
|
||||
switch ( param.param ) {
|
||||
case MACH64_PARAM_FRAMES_QUEUED:
|
||||
/* Needs lock since it calls mach64_ring_tick() */
|
||||
LOCK_TEST_WITH_RETURN( dev, filp );
|
||||
value = mach64_do_get_frames_queued( dev_priv );
|
||||
break;
|
||||
case MACH64_PARAM_IRQ_NR:
|
||||
value = dev->irq;
|
||||
break;
|
||||
default:
|
||||
return DRM_ERR(EINVAL);
|
||||
}
|
||||
|
||||
if ( DRM_COPY_TO_USER( param.value, &value, sizeof(int) ) ) {
|
||||
DRM_ERROR( "copy_to_user\n" );
|
||||
return DRM_ERR(EFAULT);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
117
shared/mach64.h
Normal file
117
shared/mach64.h
Normal file
|
|
@ -0,0 +1,117 @@
|
|||
/* mach64.h -- ATI Mach 64 DRM template customization -*- linux-c -*-
|
||||
* Created: Wed Feb 14 16:07:10 2001 by gareth@valinux.com
|
||||
*
|
||||
* Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
|
||||
* Copyright 2002-2003 Leif Delgass
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice (including the next
|
||||
* paragraph) shall be included in all copies or substantial portions of the
|
||||
* Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Authors:
|
||||
* Gareth Hughes <gareth@valinux.com>
|
||||
* Leif Delgass <ldelgass@retinalburn.net>
|
||||
*/
|
||||
|
||||
#ifndef __MACH64_H__
|
||||
#define __MACH64_H__
|
||||
|
||||
/* This remains constant for all DRM template files.
|
||||
*/
|
||||
#define DRM(x) mach64_##x
|
||||
|
||||
/* General customization:
|
||||
*/
|
||||
#define __HAVE_AGP 1
|
||||
#define __MUST_HAVE_AGP 0
|
||||
#define __HAVE_MTRR 1
|
||||
#define __HAVE_CTX_BITMAP 1
|
||||
#define __HAVE_PCI_DMA 1
|
||||
|
||||
#define DRIVER_AUTHOR "Gareth Hughes, Leif Delgass, José Fonseca"
|
||||
|
||||
#define DRIVER_NAME "mach64"
|
||||
#define DRIVER_DESC "DRM module for the ATI Rage Pro"
|
||||
#define DRIVER_DATE "20020904"
|
||||
|
||||
#define DRIVER_MAJOR 1
|
||||
#define DRIVER_MINOR 0
|
||||
#define DRIVER_PATCHLEVEL 0
|
||||
|
||||
/* Interface history:
|
||||
*
|
||||
* 1.0 - Initial mach64 DRM
|
||||
*
|
||||
*/
|
||||
#define DRIVER_IOCTLS \
|
||||
[DRM_IOCTL_NR(DRM_IOCTL_DMA)] = { mach64_dma_buffers, 1, 0 }, \
|
||||
[DRM_IOCTL_NR(DRM_IOCTL_MACH64_INIT)] = { mach64_dma_init, 1, 1 }, \
|
||||
[DRM_IOCTL_NR(DRM_IOCTL_MACH64_CLEAR)] = { mach64_dma_clear, 1, 0 }, \
|
||||
[DRM_IOCTL_NR(DRM_IOCTL_MACH64_SWAP)] = { mach64_dma_swap, 1, 0 }, \
|
||||
[DRM_IOCTL_NR(DRM_IOCTL_MACH64_IDLE)] = { mach64_dma_idle, 1, 0 }, \
|
||||
[DRM_IOCTL_NR(DRM_IOCTL_MACH64_RESET)] = { mach64_engine_reset, 1, 0 }, \
|
||||
[DRM_IOCTL_NR(DRM_IOCTL_MACH64_VERTEX)] = { mach64_dma_vertex, 1, 0 }, \
|
||||
[DRM_IOCTL_NR(DRM_IOCTL_MACH64_BLIT)] = { mach64_dma_blit, 1, 0 }, \
|
||||
[DRM_IOCTL_NR(DRM_IOCTL_MACH64_FLUSH)] = { mach64_dma_flush, 1, 0 }, \
|
||||
[DRM_IOCTL_NR(DRM_IOCTL_MACH64_GETPARAM)] = { mach64_get_param, 1, 0 }
|
||||
|
||||
#define DRIVER_PCI_IDS \
|
||||
{0x1002, 0x4749, 0, "3D Rage Pro"}, \
|
||||
{0x1002, 0x4750, 0, "3D Rage Pro 215GP"}, \
|
||||
{0x1002, 0x4751, 0, "3D Rage Pro 215GQ"}, \
|
||||
{0x1002, 0x4742, 0, "3D Rage Pro AGP 1X/2X"}, \
|
||||
{0x1002, 0x4744, 0, "3D Rage Pro AGP 1X"}, \
|
||||
{0x1002, 0x4c49, 0, "3D Rage LT Pro"}, \
|
||||
{0x1002, 0x4c50, 0, "3D Rage LT Pro"}, \
|
||||
{0x1002, 0x4c51, 0, "3D Rage LT Pro"}, \
|
||||
{0x1002, 0x4c42, 0, "3D Rage LT Pro AGP-133"}, \
|
||||
{0x1002, 0x4c44, 0, "3D Rage LT Pro AGP-66"}, \
|
||||
{0x1002, 0x474c, 0, "Rage XC"}, \
|
||||
{0x1002, 0x474f, 0, "Rage XL"}, \
|
||||
{0x1002, 0x4752, 0, "Rage XL"}, \
|
||||
{0x1002, 0x4753, 0, "Rage XC"}, \
|
||||
{0x1002, 0x474d, 0, "Rage XL AGP 2X"}, \
|
||||
{0x1002, 0x474e, 0, "Rage XC AGP"}, \
|
||||
{0x1002, 0x4c52, 0, "Rage Mobility P/M"}, \
|
||||
{0x1002, 0x4c53, 0, "Rage Mobility L"}, \
|
||||
{0x1002, 0x4c4d, 0, "Rage Mobility P/M AGP 2X"}, \
|
||||
{0x1002, 0x4c4e, 0, "Rage Mobility L AGP 2X"}, \
|
||||
{0, 0, 0, NULL}
|
||||
|
||||
/* Driver customization:
|
||||
*/
|
||||
#define DRIVER_PRETAKEDOWN() do { \
|
||||
mach64_do_cleanup_dma( dev ); \
|
||||
} while (0)
|
||||
|
||||
/* DMA customization:
|
||||
*/
|
||||
#define __HAVE_DMA 1
|
||||
#define __HAVE_DMA_IRQ 1
|
||||
#define __HAVE_VBL_IRQ 1
|
||||
#define __HAVE_SHARED_IRQ 1
|
||||
#define __HAVE_IRQ 1
|
||||
|
||||
/* Buffer customization:
|
||||
*/
|
||||
|
||||
#define DRIVER_AGP_BUFFERS_MAP( dev ) \
|
||||
((drm_mach64_private_t *)((dev)->dev_private))->buffers
|
||||
|
||||
#endif
|
||||
1325
shared/mach64_dma.c
Normal file
1325
shared/mach64_dma.c
Normal file
File diff suppressed because it is too large
Load diff
258
shared/mach64_drm.h
Normal file
258
shared/mach64_drm.h
Normal file
|
|
@ -0,0 +1,258 @@
|
|||
/* mach64_drm.h -- Public header for the mach64 driver -*- linux-c -*-
|
||||
* Created: Thu Nov 30 20:04:32 2000 by gareth@valinux.com
|
||||
*
|
||||
* Copyright 2000 Gareth Hughes
|
||||
* Copyright 2002 Frank C. Earl
|
||||
* Copyright 2002-2003 Leif Delgass
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice (including the next
|
||||
* paragraph) shall be included in all copies or substantial portions of the
|
||||
* Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT OWNER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Authors:
|
||||
* Gareth Hughes <gareth@valinux.com>
|
||||
* Frank C. Earl <fearl@airmail.net>
|
||||
* Leif Delgass <ldelgass@retinalburn.net>
|
||||
*/
|
||||
|
||||
#ifndef __MACH64_DRM_H__
|
||||
#define __MACH64_DRM_H__
|
||||
|
||||
|
||||
/* WARNING: If you change any of these defines, make sure to change the
|
||||
* defines in the Xserver file (mach64_sarea.h)
|
||||
*/
|
||||
#ifndef __MACH64_SAREA_DEFINES__
|
||||
#define __MACH64_SAREA_DEFINES__
|
||||
|
||||
/* What needs to be changed for the current vertex buffer?
|
||||
* GH: We're going to be pedantic about this. We want the card to do as
|
||||
* little as possible, so let's avoid having it fetch a whole bunch of
|
||||
* register values that don't change all that often, if at all.
|
||||
*/
|
||||
#define MACH64_UPLOAD_DST_OFF_PITCH 0x0001
|
||||
#define MACH64_UPLOAD_Z_OFF_PITCH 0x0002
|
||||
#define MACH64_UPLOAD_Z_ALPHA_CNTL 0x0004
|
||||
#define MACH64_UPLOAD_SCALE_3D_CNTL 0x0008
|
||||
#define MACH64_UPLOAD_DP_FOG_CLR 0x0010
|
||||
#define MACH64_UPLOAD_DP_WRITE_MASK 0x0020
|
||||
#define MACH64_UPLOAD_DP_PIX_WIDTH 0x0040
|
||||
#define MACH64_UPLOAD_SETUP_CNTL 0x0080
|
||||
#define MACH64_UPLOAD_MISC 0x0100
|
||||
#define MACH64_UPLOAD_TEXTURE 0x0200
|
||||
#define MACH64_UPLOAD_TEX0IMAGE 0x0400
|
||||
#define MACH64_UPLOAD_TEX1IMAGE 0x0800
|
||||
#define MACH64_UPLOAD_CLIPRECTS 0x1000 /* handled client-side */
|
||||
#define MACH64_UPLOAD_CONTEXT 0x00ff
|
||||
#define MACH64_UPLOAD_ALL 0x1fff
|
||||
|
||||
/* DMA buffer size
|
||||
*/
|
||||
#define MACH64_BUFFER_SIZE 16384
|
||||
|
||||
/* Max number of swaps allowed on the ring
|
||||
* before the client must wait
|
||||
*/
|
||||
#define MACH64_MAX_QUEUED_FRAMES 3
|
||||
|
||||
/* Byte offsets for host blit buffer data
|
||||
*/
|
||||
#define MACH64_HOSTDATA_BLIT_OFFSET 104
|
||||
|
||||
/* Keep these small for testing.
|
||||
*/
|
||||
#define MACH64_NR_SAREA_CLIPRECTS 8
|
||||
|
||||
|
||||
#define MACH64_CARD_HEAP 0
|
||||
#define MACH64_AGP_HEAP 1
|
||||
#define MACH64_NR_TEX_HEAPS 2
|
||||
#define MACH64_NR_TEX_REGIONS 64
|
||||
#define MACH64_LOG_TEX_GRANULARITY 16
|
||||
|
||||
#define MACH64_TEX_MAXLEVELS 1
|
||||
|
||||
#define MACH64_NR_CONTEXT_REGS 15
|
||||
#define MACH64_NR_TEXTURE_REGS 4
|
||||
|
||||
#endif /* __MACH64_SAREA_DEFINES__ */
|
||||
|
||||
typedef struct {
|
||||
unsigned int dst_off_pitch;
|
||||
|
||||
unsigned int z_off_pitch;
|
||||
unsigned int z_cntl;
|
||||
unsigned int alpha_tst_cntl;
|
||||
|
||||
unsigned int scale_3d_cntl;
|
||||
|
||||
unsigned int sc_left_right;
|
||||
unsigned int sc_top_bottom;
|
||||
|
||||
unsigned int dp_fog_clr;
|
||||
unsigned int dp_write_mask;
|
||||
unsigned int dp_pix_width;
|
||||
unsigned int dp_mix;
|
||||
unsigned int dp_src;
|
||||
|
||||
unsigned int clr_cmp_cntl;
|
||||
unsigned int gui_traj_cntl;
|
||||
|
||||
unsigned int setup_cntl;
|
||||
|
||||
unsigned int tex_size_pitch;
|
||||
unsigned int tex_cntl;
|
||||
unsigned int secondary_tex_off;
|
||||
unsigned int tex_offset;
|
||||
} drm_mach64_context_regs_t;
|
||||
|
||||
typedef struct drm_mach64_sarea {
|
||||
/* The channel for communication of state information to the kernel
|
||||
* on firing a vertex dma buffer.
|
||||
*/
|
||||
drm_mach64_context_regs_t context_state;
|
||||
unsigned int dirty;
|
||||
unsigned int vertsize;
|
||||
|
||||
/* The current cliprects, or a subset thereof.
|
||||
*/
|
||||
drm_clip_rect_t boxes[MACH64_NR_SAREA_CLIPRECTS];
|
||||
unsigned int nbox;
|
||||
|
||||
/* Counters for client-side throttling of rendering clients.
|
||||
*/
|
||||
unsigned int frames_queued;
|
||||
|
||||
/* Texture memory LRU.
|
||||
*/
|
||||
drm_tex_region_t tex_list[MACH64_NR_TEX_HEAPS][MACH64_NR_TEX_REGIONS+1];
|
||||
unsigned int tex_age[MACH64_NR_TEX_HEAPS];
|
||||
int ctx_owner;
|
||||
} drm_mach64_sarea_t;
|
||||
|
||||
|
||||
/* WARNING: If you change any of these defines, make sure to change the
|
||||
* defines in the Xserver file (mach64_common.h)
|
||||
*/
|
||||
|
||||
/* Mach64 specific ioctls
|
||||
* The device specific ioctl range is 0x40 to 0x79.
|
||||
*/
|
||||
|
||||
#define DRM_MACH64_INIT 0x00
|
||||
#define DRM_MACH64_IDLE 0x01
|
||||
#define DRM_MACH64_RESET 0x02
|
||||
#define DRM_MACH64_SWAP 0x03
|
||||
#define DRM_MACH64_CLEAR 0x04
|
||||
#define DRM_MACH64_VERTEX 0x05
|
||||
#define DRM_MACH64_BLIT 0x06
|
||||
#define DRM_MACH64_FLUSH 0x07
|
||||
#define DRM_MACH64_GETPARAM 0x08
|
||||
|
||||
#define DRM_IOCTL_MACH64_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_MACH64_INIT, drm_mach64_init_t)
|
||||
#define DRM_IOCTL_MACH64_IDLE DRM_IO( DRM_COMMAND_BASE + DRM_MACH64_IDLE )
|
||||
#define DRM_IOCTL_MACH64_RESET DRM_IO( DRM_COMMAND_BASE + DRM_MACH64_RESET )
|
||||
#define DRM_IOCTL_MACH64_SWAP DRM_IO( DRM_COMMAND_BASE + DRM_MACH64_SWAP )
|
||||
#define DRM_IOCTL_MACH64_CLEAR DRM_IOW( DRM_COMMAND_BASE + DRM_MACH64_CLEAR, drm_mach64_clear_t)
|
||||
#define DRM_IOCTL_MACH64_VERTEX DRM_IOW( DRM_COMMAND_BASE + DRM_MACH64_VERTEX, drm_mach64_vertex_t)
|
||||
#define DRM_IOCTL_MACH64_BLIT DRM_IOW( DRM_COMMAND_BASE + DRM_MACH64_BLIT, drm_mach64_blit_t)
|
||||
#define DRM_IOCTL_MACH64_FLUSH DRM_IO( DRM_COMMAND_BASE + DRM_MACH64_FLUSH )
|
||||
#define DRM_IOCTL_MACH64_GETPARAM DRM_IOWR( DRM_COMMAND_BASE + DRM_MACH64_GETPARAM, drm_mach64_getparam_t)
|
||||
|
||||
/* Buffer flags for clears
|
||||
*/
|
||||
#define MACH64_FRONT 0x1
|
||||
#define MACH64_BACK 0x2
|
||||
#define MACH64_DEPTH 0x4
|
||||
|
||||
/* Primitive types for vertex buffers
|
||||
*/
|
||||
#define MACH64_PRIM_POINTS 0x00000000
|
||||
#define MACH64_PRIM_LINES 0x00000001
|
||||
#define MACH64_PRIM_LINE_LOOP 0x00000002
|
||||
#define MACH64_PRIM_LINE_STRIP 0x00000003
|
||||
#define MACH64_PRIM_TRIANGLES 0x00000004
|
||||
#define MACH64_PRIM_TRIANGLE_STRIP 0x00000005
|
||||
#define MACH64_PRIM_TRIANGLE_FAN 0x00000006
|
||||
#define MACH64_PRIM_QUADS 0x00000007
|
||||
#define MACH64_PRIM_QUAD_STRIP 0x00000008
|
||||
#define MACH64_PRIM_POLYGON 0x00000009
|
||||
|
||||
|
||||
typedef enum _drm_mach64_dma_mode_t {
|
||||
MACH64_MODE_DMA_ASYNC,
|
||||
MACH64_MODE_DMA_SYNC,
|
||||
MACH64_MODE_MMIO
|
||||
} drm_mach64_dma_mode_t;
|
||||
|
||||
typedef struct drm_mach64_init {
|
||||
enum {
|
||||
DRM_MACH64_INIT_DMA = 0x01,
|
||||
DRM_MACH64_CLEANUP_DMA = 0x02
|
||||
} func;
|
||||
|
||||
unsigned long sarea_priv_offset;
|
||||
int is_pci;
|
||||
drm_mach64_dma_mode_t dma_mode;
|
||||
|
||||
unsigned int fb_bpp;
|
||||
unsigned int front_offset, front_pitch;
|
||||
unsigned int back_offset, back_pitch;
|
||||
|
||||
unsigned int depth_bpp;
|
||||
unsigned int depth_offset, depth_pitch;
|
||||
|
||||
unsigned long fb_offset;
|
||||
unsigned long mmio_offset;
|
||||
unsigned long ring_offset;
|
||||
unsigned long buffers_offset;
|
||||
unsigned long agp_textures_offset;
|
||||
} drm_mach64_init_t;
|
||||
|
||||
typedef struct drm_mach64_clear {
|
||||
unsigned int flags;
|
||||
int x, y, w, h;
|
||||
unsigned int clear_color;
|
||||
unsigned int clear_depth;
|
||||
} drm_mach64_clear_t;
|
||||
|
||||
typedef struct drm_mach64_vertex {
|
||||
int prim;
|
||||
void *buf; /* Address of vertex buffer */
|
||||
unsigned long used; /* Number of bytes in buffer */
|
||||
int discard; /* Client finished with buffer? */
|
||||
} drm_mach64_vertex_t;
|
||||
|
||||
typedef struct drm_mach64_blit {
|
||||
int idx;
|
||||
int pitch;
|
||||
int offset;
|
||||
int format;
|
||||
unsigned short x, y;
|
||||
unsigned short width, height;
|
||||
} drm_mach64_blit_t;
|
||||
|
||||
typedef struct drm_mach64_getparam {
|
||||
enum {
|
||||
MACH64_PARAM_FRAMES_QUEUED = 0x01,
|
||||
MACH64_PARAM_IRQ_NR = 0x02
|
||||
} param;
|
||||
void *value;
|
||||
} drm_mach64_getparam_t;
|
||||
|
||||
#endif
|
||||
1034
shared/mach64_drv.h
Normal file
1034
shared/mach64_drv.h
Normal file
File diff suppressed because it is too large
Load diff
130
shared/mach64_irq.c
Normal file
130
shared/mach64_irq.c
Normal file
|
|
@ -0,0 +1,130 @@
|
|||
/* mach64_irq.c -- IRQ handling for ATI Mach64 -*- linux-c -*-
|
||||
* Created: Tue Feb 25, 2003 by Leif Delgass, based on radeon_irq.c/r128_irq.c
|
||||
*
|
||||
* Copyright (C) The Weather Channel, Inc. 2002.
|
||||
* Copyright 2003 Leif Delgass
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* The Weather Channel (TM) funded Tungsten Graphics to develop the
|
||||
* initial release of the Radeon 8500 driver under the XFree86 license.
|
||||
* This notice must be preserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice (including the next
|
||||
* paragraph) shall be included in all copies or substantial portions of the
|
||||
* Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Authors:
|
||||
* Keith Whitwell <keith@tungstengraphics.com>
|
||||
* Eric Anholt <anholt@FreeBSD.org>
|
||||
* Leif Delgass <ldelgass@retinalburn.net>
|
||||
*/
|
||||
|
||||
#include "mach64.h"
|
||||
#include "drmP.h"
|
||||
#include "drm.h"
|
||||
#include "mach64_drm.h"
|
||||
#include "mach64_drv.h"
|
||||
|
||||
irqreturn_t DRM(irq_handler)( DRM_IRQ_ARGS )
|
||||
{
|
||||
drm_device_t *dev = (drm_device_t *) arg;
|
||||
drm_mach64_private_t *dev_priv =
|
||||
(drm_mach64_private_t *)dev->dev_private;
|
||||
int status;
|
||||
|
||||
status = MACH64_READ( MACH64_CRTC_INT_CNTL );
|
||||
|
||||
/* VBLANK interrupt */
|
||||
if (status & MACH64_CRTC_VBLANK_INT) {
|
||||
/* Mask off all interrupt ack bits before setting the ack bit, since
|
||||
* there may be other handlers outside the DRM.
|
||||
*
|
||||
* NOTE: On mach64, you need to keep the enable bits set when doing
|
||||
* the ack, despite what the docs say about not acking and enabling
|
||||
* in a single write.
|
||||
*/
|
||||
MACH64_WRITE( MACH64_CRTC_INT_CNTL, (status & ~MACH64_CRTC_INT_ACKS)
|
||||
| MACH64_CRTC_VBLANK_INT );
|
||||
|
||||
atomic_inc(&dev->vbl_received);
|
||||
DRM_WAKEUP(&dev->vbl_queue);
|
||||
DRM(vbl_send_signals)( dev );
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
return IRQ_NONE;
|
||||
}
|
||||
|
||||
int DRM(vblank_wait)(drm_device_t *dev, unsigned int *sequence)
|
||||
{
|
||||
unsigned int cur_vblank;
|
||||
int ret = 0;
|
||||
|
||||
/* Assume that the user has missed the current sequence number
|
||||
* by about a day rather than she wants to wait for years
|
||||
* using vertical blanks...
|
||||
*/
|
||||
DRM_WAIT_ON( ret, dev->vbl_queue, 3*DRM_HZ,
|
||||
( ( ( cur_vblank = atomic_read(&dev->vbl_received ) )
|
||||
- *sequence ) <= (1<<23) ) );
|
||||
|
||||
*sequence = cur_vblank;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* drm_dma.h hooks
|
||||
*/
|
||||
void DRM(driver_irq_preinstall)( drm_device_t *dev ) {
|
||||
drm_mach64_private_t *dev_priv =
|
||||
(drm_mach64_private_t *)dev->dev_private;
|
||||
|
||||
u32 status = MACH64_READ( MACH64_CRTC_INT_CNTL );
|
||||
|
||||
DRM_DEBUG("before install CRTC_INT_CTNL: 0x%08x\n", status );
|
||||
|
||||
/* Disable and clear VBLANK interrupt */
|
||||
MACH64_WRITE( MACH64_CRTC_INT_CNTL, (status & ~MACH64_CRTC_VBLANK_INT_EN)
|
||||
| MACH64_CRTC_VBLANK_INT );
|
||||
}
|
||||
|
||||
void DRM(driver_irq_postinstall)( drm_device_t *dev ) {
|
||||
drm_mach64_private_t *dev_priv =
|
||||
(drm_mach64_private_t *)dev->dev_private;
|
||||
|
||||
/* Turn on VBLANK interrupt */
|
||||
MACH64_WRITE( MACH64_CRTC_INT_CNTL, MACH64_READ( MACH64_CRTC_INT_CNTL )
|
||||
| MACH64_CRTC_VBLANK_INT_EN );
|
||||
|
||||
DRM_DEBUG("after install CRTC_INT_CTNL: 0x%08x\n", MACH64_READ( MACH64_CRTC_INT_CNTL ));
|
||||
|
||||
}
|
||||
|
||||
void DRM(driver_irq_uninstall)( drm_device_t *dev ) {
|
||||
drm_mach64_private_t *dev_priv =
|
||||
(drm_mach64_private_t *)dev->dev_private;
|
||||
if ( !dev_priv )
|
||||
return;
|
||||
|
||||
/* Disable and clear VBLANK interrupt */
|
||||
MACH64_WRITE( MACH64_CRTC_INT_CNTL,
|
||||
(MACH64_READ( MACH64_CRTC_INT_CNTL ) & ~MACH64_CRTC_VBLANK_INT_EN)
|
||||
| MACH64_CRTC_VBLANK_INT );
|
||||
|
||||
DRM_DEBUG("after uninstall CRTC_INT_CTNL: 0x%08x\n",
|
||||
MACH64_READ( MACH64_CRTC_INT_CNTL ));
|
||||
}
|
||||
897
shared/mach64_state.c
Normal file
897
shared/mach64_state.c
Normal file
|
|
@ -0,0 +1,897 @@
|
|||
/* mach64_state.c -- State support for mach64 (Rage Pro) driver -*- linux-c -*-
|
||||
* Created: Sun Dec 03 19:20:26 2000 by gareth@valinux.com
|
||||
*
|
||||
* Copyright 2000 Gareth Hughes
|
||||
* Copyright 2002-2003 Leif Delgass
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice (including the next
|
||||
* paragraph) shall be included in all copies or substantial portions of the
|
||||
* Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT OWNER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Authors:
|
||||
* Gareth Hughes <gareth@valinux.com>
|
||||
* Leif Delgass <ldelgass@retinalburn.net>
|
||||
* José Fonseca <j_r_fonseca@yahoo.co.uk>
|
||||
*/
|
||||
|
||||
#define __NO_VERSION__
|
||||
#include "mach64.h"
|
||||
#include "drmP.h"
|
||||
#include "drm.h"
|
||||
#include "mach64_drm.h"
|
||||
#include "mach64_drv.h"
|
||||
|
||||
|
||||
/* ================================================================
|
||||
* DMA hardware state programming functions
|
||||
*/
|
||||
|
||||
static void mach64_print_dirty( const char *msg, unsigned int flags )
|
||||
{
|
||||
DRM_DEBUG( "%s: (0x%x) %s%s%s%s%s%s%s%s%s%s%s%s\n",
|
||||
msg,
|
||||
flags,
|
||||
(flags & MACH64_UPLOAD_DST_OFF_PITCH) ? "dst_off_pitch, " : "",
|
||||
(flags & MACH64_UPLOAD_Z_ALPHA_CNTL) ? "z_alpha_cntl, " : "",
|
||||
(flags & MACH64_UPLOAD_SCALE_3D_CNTL) ? "scale_3d_cntl, " : "",
|
||||
(flags & MACH64_UPLOAD_DP_FOG_CLR) ? "dp_fog_clr, " : "",
|
||||
(flags & MACH64_UPLOAD_DP_WRITE_MASK) ? "dp_write_mask, " : "",
|
||||
(flags & MACH64_UPLOAD_DP_PIX_WIDTH) ? "dp_pix_width, " : "",
|
||||
(flags & MACH64_UPLOAD_SETUP_CNTL) ? "setup_cntl, " : "",
|
||||
(flags & MACH64_UPLOAD_MISC) ? "misc, " : "",
|
||||
(flags & MACH64_UPLOAD_TEXTURE) ? "texture, " : "",
|
||||
(flags & MACH64_UPLOAD_TEX0IMAGE) ? "tex0 image, " : "",
|
||||
(flags & MACH64_UPLOAD_TEX1IMAGE) ? "tex1 image, " : "",
|
||||
(flags & MACH64_UPLOAD_CLIPRECTS) ? "cliprects, " : "" );
|
||||
}
|
||||
|
||||
/* Mach64 doesn't have hardware cliprects, just one hardware scissor,
|
||||
* so the GL scissor is intersected with each cliprect here
|
||||
*/
|
||||
/* This function returns 0 on success, 1 for no intersection, and
|
||||
* negative for an error
|
||||
*/
|
||||
static int mach64_emit_cliprect( DRMFILE filp, drm_mach64_private_t *dev_priv,
|
||||
drm_clip_rect_t *box )
|
||||
{
|
||||
u32 sc_left_right, sc_top_bottom;
|
||||
drm_clip_rect_t scissor;
|
||||
drm_mach64_sarea_t *sarea_priv = dev_priv->sarea_priv;
|
||||
drm_mach64_context_regs_t *regs = &sarea_priv->context_state;
|
||||
DMALOCALS;
|
||||
|
||||
DRM_DEBUG( "%s: box=%p\n", __FUNCTION__, box );
|
||||
|
||||
/* Get GL scissor */
|
||||
/* FIXME: store scissor in SAREA as a cliprect instead of in
|
||||
* hardware format, or do intersection client-side
|
||||
*/
|
||||
scissor.x1 = regs->sc_left_right & 0xffff;
|
||||
scissor.x2 = (regs->sc_left_right & 0xffff0000) >> 16;
|
||||
scissor.y1 = regs->sc_top_bottom & 0xffff;
|
||||
scissor.y2 = (regs->sc_top_bottom & 0xffff0000) >> 16;
|
||||
|
||||
/* Intersect GL scissor with cliprect */
|
||||
if ( box->x1 > scissor.x1 ) scissor.x1 = box->x1;
|
||||
if ( box->y1 > scissor.y1 ) scissor.y1 = box->y1;
|
||||
if ( box->x2 < scissor.x2 ) scissor.x2 = box->x2;
|
||||
if ( box->y2 < scissor.y2 ) scissor.y2 = box->y2;
|
||||
/* positive return means skip */
|
||||
if ( scissor.x1 >= scissor.x2 ) return 1;
|
||||
if ( scissor.y1 >= scissor.y2 ) return 1;
|
||||
|
||||
DMAGETPTR( filp, dev_priv, 2 ); /* returns on failure to get buffer */
|
||||
|
||||
sc_left_right = ( (scissor.x1 << 0) | (scissor.x2 << 16) );
|
||||
sc_top_bottom = ( (scissor.y1 << 0) | (scissor.y2 << 16) );
|
||||
|
||||
DMAOUTREG( MACH64_SC_LEFT_RIGHT, sc_left_right );
|
||||
DMAOUTREG( MACH64_SC_TOP_BOTTOM, sc_top_bottom );
|
||||
|
||||
DMAADVANCE( dev_priv, 1 );
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static __inline__ int mach64_emit_state( DRMFILE filp, drm_mach64_private_t *dev_priv )
|
||||
{
|
||||
drm_mach64_sarea_t *sarea_priv = dev_priv->sarea_priv;
|
||||
drm_mach64_context_regs_t *regs = &sarea_priv->context_state;
|
||||
unsigned int dirty = sarea_priv->dirty;
|
||||
u32 offset = ((regs->tex_size_pitch & 0xf0) >> 2);
|
||||
DMALOCALS;
|
||||
|
||||
if ( MACH64_VERBOSE ) {
|
||||
mach64_print_dirty( __FUNCTION__, dirty );
|
||||
} else {
|
||||
DRM_DEBUG( "%s: dirty=0x%08x\n", __FUNCTION__, dirty );
|
||||
}
|
||||
|
||||
DMAGETPTR( filp, dev_priv, 17 ); /* returns on failure to get buffer */
|
||||
|
||||
if ( dirty & MACH64_UPLOAD_MISC ) {
|
||||
DMAOUTREG( MACH64_DP_MIX, regs->dp_mix );
|
||||
DMAOUTREG( MACH64_DP_SRC, regs->dp_src );
|
||||
DMAOUTREG( MACH64_CLR_CMP_CNTL, regs->clr_cmp_cntl );
|
||||
DMAOUTREG( MACH64_GUI_TRAJ_CNTL, regs->gui_traj_cntl );
|
||||
sarea_priv->dirty &= ~MACH64_UPLOAD_MISC;
|
||||
}
|
||||
|
||||
if ( dirty & MACH64_UPLOAD_DST_OFF_PITCH ) {
|
||||
DMAOUTREG( MACH64_DST_OFF_PITCH, regs->dst_off_pitch );
|
||||
sarea_priv->dirty &= ~MACH64_UPLOAD_DST_OFF_PITCH;
|
||||
}
|
||||
if ( dirty & MACH64_UPLOAD_Z_OFF_PITCH ) {
|
||||
DMAOUTREG( MACH64_Z_OFF_PITCH, regs->z_off_pitch );
|
||||
sarea_priv->dirty &= ~MACH64_UPLOAD_Z_OFF_PITCH;
|
||||
}
|
||||
if ( dirty & MACH64_UPLOAD_Z_ALPHA_CNTL ) {
|
||||
DMAOUTREG( MACH64_Z_CNTL, regs->z_cntl );
|
||||
DMAOUTREG( MACH64_ALPHA_TST_CNTL, regs->alpha_tst_cntl );
|
||||
sarea_priv->dirty &= ~MACH64_UPLOAD_Z_ALPHA_CNTL;
|
||||
}
|
||||
if ( dirty & MACH64_UPLOAD_SCALE_3D_CNTL ) {
|
||||
DMAOUTREG( MACH64_SCALE_3D_CNTL, regs->scale_3d_cntl );
|
||||
sarea_priv->dirty &= ~MACH64_UPLOAD_SCALE_3D_CNTL;
|
||||
}
|
||||
if ( dirty & MACH64_UPLOAD_DP_FOG_CLR ) {
|
||||
DMAOUTREG( MACH64_DP_FOG_CLR, regs->dp_fog_clr );
|
||||
sarea_priv->dirty &= ~MACH64_UPLOAD_DP_FOG_CLR;
|
||||
}
|
||||
if ( dirty & MACH64_UPLOAD_DP_WRITE_MASK ) {
|
||||
DMAOUTREG( MACH64_DP_WRITE_MASK, regs->dp_write_mask );
|
||||
sarea_priv->dirty &= ~MACH64_UPLOAD_DP_WRITE_MASK;
|
||||
}
|
||||
if ( dirty & MACH64_UPLOAD_DP_PIX_WIDTH ) {
|
||||
DMAOUTREG( MACH64_DP_PIX_WIDTH, regs->dp_pix_width );
|
||||
sarea_priv->dirty &= ~MACH64_UPLOAD_DP_PIX_WIDTH;
|
||||
}
|
||||
if ( dirty & MACH64_UPLOAD_SETUP_CNTL ) {
|
||||
DMAOUTREG( MACH64_SETUP_CNTL, regs->setup_cntl );
|
||||
sarea_priv->dirty &= ~MACH64_UPLOAD_SETUP_CNTL;
|
||||
}
|
||||
|
||||
if ( dirty & MACH64_UPLOAD_TEXTURE ) {
|
||||
DMAOUTREG( MACH64_TEX_SIZE_PITCH, regs->tex_size_pitch );
|
||||
DMAOUTREG( MACH64_TEX_CNTL, regs->tex_cntl );
|
||||
DMAOUTREG( MACH64_SECONDARY_TEX_OFF, regs->secondary_tex_off );
|
||||
DMAOUTREG( MACH64_TEX_0_OFF + offset, regs->tex_offset );
|
||||
sarea_priv->dirty &= ~MACH64_UPLOAD_TEXTURE;
|
||||
}
|
||||
|
||||
DMAADVANCE( dev_priv, 1 );
|
||||
|
||||
sarea_priv->dirty &= MACH64_UPLOAD_CLIPRECTS;
|
||||
|
||||
return 0;
|
||||
|
||||
}
|
||||
|
||||
|
||||
/* ================================================================
|
||||
* DMA command dispatch functions
|
||||
*/
|
||||
|
||||
static int mach64_dma_dispatch_clear( DRMFILE filp, drm_device_t *dev,
|
||||
unsigned int flags,
|
||||
int cx, int cy, int cw, int ch,
|
||||
unsigned int clear_color,
|
||||
unsigned int clear_depth )
|
||||
{
|
||||
drm_mach64_private_t *dev_priv = dev->dev_private;
|
||||
drm_mach64_sarea_t *sarea_priv = dev_priv->sarea_priv;
|
||||
drm_mach64_context_regs_t *ctx = &sarea_priv->context_state;
|
||||
int nbox = sarea_priv->nbox;
|
||||
drm_clip_rect_t *pbox = sarea_priv->boxes;
|
||||
u32 fb_bpp, depth_bpp;
|
||||
int i;
|
||||
DMALOCALS;
|
||||
|
||||
DRM_DEBUG( "%s\n", __FUNCTION__ );
|
||||
|
||||
switch ( dev_priv->fb_bpp ) {
|
||||
case 16:
|
||||
fb_bpp = MACH64_DATATYPE_RGB565;
|
||||
break;
|
||||
case 32:
|
||||
fb_bpp = MACH64_DATATYPE_ARGB8888;
|
||||
break;
|
||||
default:
|
||||
return DRM_ERR(EINVAL);
|
||||
}
|
||||
switch ( dev_priv->depth_bpp ) {
|
||||
case 16:
|
||||
depth_bpp = MACH64_DATATYPE_RGB565;
|
||||
break;
|
||||
case 24:
|
||||
case 32:
|
||||
depth_bpp = MACH64_DATATYPE_ARGB8888;
|
||||
break;
|
||||
default:
|
||||
return DRM_ERR(EINVAL);
|
||||
}
|
||||
|
||||
if ( !nbox )
|
||||
return 0;
|
||||
|
||||
DMAGETPTR( filp, dev_priv, nbox * 31 ); /* returns on failure to get buffer */
|
||||
|
||||
for ( i = 0 ; i < nbox ; i++ ) {
|
||||
int x = pbox[i].x1;
|
||||
int y = pbox[i].y1;
|
||||
int w = pbox[i].x2 - x;
|
||||
int h = pbox[i].y2 - y;
|
||||
|
||||
DRM_DEBUG( "dispatch clear %d,%d-%d,%d flags 0x%x\n",
|
||||
pbox[i].x1, pbox[i].y1,
|
||||
pbox[i].x2, pbox[i].y2, flags );
|
||||
|
||||
if ( flags & (MACH64_FRONT | MACH64_BACK) ) {
|
||||
/* Setup for color buffer clears
|
||||
*/
|
||||
|
||||
DMAOUTREG( MACH64_Z_CNTL, 0 );
|
||||
DMAOUTREG( MACH64_SCALE_3D_CNTL, 0 );
|
||||
|
||||
DMAOUTREG( MACH64_SC_LEFT_RIGHT, ctx->sc_left_right );
|
||||
DMAOUTREG( MACH64_SC_TOP_BOTTOM, ctx->sc_top_bottom );
|
||||
|
||||
DMAOUTREG( MACH64_CLR_CMP_CNTL, 0 );
|
||||
DMAOUTREG( MACH64_GUI_TRAJ_CNTL,
|
||||
(MACH64_DST_X_LEFT_TO_RIGHT |
|
||||
MACH64_DST_Y_TOP_TO_BOTTOM) );
|
||||
|
||||
DMAOUTREG( MACH64_DP_PIX_WIDTH, ((fb_bpp << 0) |
|
||||
(fb_bpp << 4) |
|
||||
(fb_bpp << 8) |
|
||||
(fb_bpp << 16) |
|
||||
(fb_bpp << 28)) );
|
||||
|
||||
DMAOUTREG( MACH64_DP_FRGD_CLR, clear_color );
|
||||
DMAOUTREG( MACH64_DP_WRITE_MASK, ctx->dp_write_mask );
|
||||
DMAOUTREG( MACH64_DP_MIX, (MACH64_BKGD_MIX_D |
|
||||
MACH64_FRGD_MIX_S) );
|
||||
DMAOUTREG( MACH64_DP_SRC, (MACH64_BKGD_SRC_FRGD_CLR |
|
||||
MACH64_FRGD_SRC_FRGD_CLR |
|
||||
MACH64_MONO_SRC_ONE) );
|
||||
|
||||
|
||||
}
|
||||
|
||||
if ( flags & MACH64_FRONT ) {
|
||||
|
||||
DMAOUTREG( MACH64_DST_OFF_PITCH,
|
||||
dev_priv->front_offset_pitch );
|
||||
DMAOUTREG( MACH64_DST_X_Y,
|
||||
(y << 16) | x );
|
||||
DMAOUTREG( MACH64_DST_WIDTH_HEIGHT,
|
||||
(h << 16) | w );
|
||||
|
||||
}
|
||||
|
||||
if ( flags & MACH64_BACK ) {
|
||||
|
||||
DMAOUTREG( MACH64_DST_OFF_PITCH,
|
||||
dev_priv->back_offset_pitch );
|
||||
DMAOUTREG( MACH64_DST_X_Y,
|
||||
(y << 16) | x );
|
||||
DMAOUTREG( MACH64_DST_WIDTH_HEIGHT,
|
||||
(h << 16) | w );
|
||||
|
||||
}
|
||||
|
||||
if ( flags & MACH64_DEPTH ) {
|
||||
/* Setup for depth buffer clear
|
||||
*/
|
||||
DMAOUTREG( MACH64_Z_CNTL, 0 );
|
||||
DMAOUTREG( MACH64_SCALE_3D_CNTL, 0 );
|
||||
|
||||
DMAOUTREG( MACH64_SC_LEFT_RIGHT, ctx->sc_left_right );
|
||||
DMAOUTREG( MACH64_SC_TOP_BOTTOM, ctx->sc_top_bottom );
|
||||
|
||||
DMAOUTREG( MACH64_CLR_CMP_CNTL, 0 );
|
||||
DMAOUTREG( MACH64_GUI_TRAJ_CNTL,
|
||||
(MACH64_DST_X_LEFT_TO_RIGHT |
|
||||
MACH64_DST_Y_TOP_TO_BOTTOM) );
|
||||
|
||||
DMAOUTREG( MACH64_DP_PIX_WIDTH, ((depth_bpp << 0) |
|
||||
(depth_bpp << 4) |
|
||||
(depth_bpp << 8) |
|
||||
(depth_bpp << 16) |
|
||||
(depth_bpp << 28)) );
|
||||
|
||||
DMAOUTREG( MACH64_DP_FRGD_CLR, clear_depth );
|
||||
DMAOUTREG( MACH64_DP_WRITE_MASK, 0xffffffff );
|
||||
DMAOUTREG( MACH64_DP_MIX, (MACH64_BKGD_MIX_D |
|
||||
MACH64_FRGD_MIX_S) );
|
||||
DMAOUTREG( MACH64_DP_SRC, (MACH64_BKGD_SRC_FRGD_CLR |
|
||||
MACH64_FRGD_SRC_FRGD_CLR |
|
||||
MACH64_MONO_SRC_ONE) );
|
||||
|
||||
DMAOUTREG( MACH64_DST_OFF_PITCH,
|
||||
dev_priv->depth_offset_pitch );
|
||||
DMAOUTREG( MACH64_DST_X_Y,
|
||||
(y << 16) | x );
|
||||
DMAOUTREG( MACH64_DST_WIDTH_HEIGHT,
|
||||
(h << 16) | w );
|
||||
}
|
||||
}
|
||||
|
||||
DMAADVANCE( dev_priv, 1 );
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mach64_dma_dispatch_swap( DRMFILE filp, drm_device_t *dev )
|
||||
{
|
||||
drm_mach64_private_t *dev_priv = dev->dev_private;
|
||||
drm_mach64_sarea_t *sarea_priv = dev_priv->sarea_priv;
|
||||
int nbox = sarea_priv->nbox;
|
||||
drm_clip_rect_t *pbox = sarea_priv->boxes;
|
||||
u32 fb_bpp;
|
||||
int i;
|
||||
DMALOCALS;
|
||||
|
||||
DRM_DEBUG( "%s\n", __FUNCTION__ );
|
||||
|
||||
switch ( dev_priv->fb_bpp ) {
|
||||
case 16:
|
||||
fb_bpp = MACH64_DATATYPE_RGB565;
|
||||
break;
|
||||
case 32:
|
||||
default:
|
||||
fb_bpp = MACH64_DATATYPE_ARGB8888;
|
||||
break;
|
||||
}
|
||||
|
||||
if ( !nbox )
|
||||
return 0;
|
||||
|
||||
DMAGETPTR( filp, dev_priv, 13 + nbox * 4 ); /* returns on failure to get buffer */
|
||||
|
||||
DMAOUTREG( MACH64_Z_CNTL, 0 );
|
||||
DMAOUTREG( MACH64_SCALE_3D_CNTL, 0 );
|
||||
|
||||
DMAOUTREG( MACH64_SC_LEFT_RIGHT, 0 | ( 8191 << 16 ) ); /* no scissor */
|
||||
DMAOUTREG( MACH64_SC_TOP_BOTTOM, 0 | ( 16383 << 16 ) );
|
||||
|
||||
DMAOUTREG( MACH64_CLR_CMP_CNTL, 0 );
|
||||
DMAOUTREG( MACH64_GUI_TRAJ_CNTL, (MACH64_DST_X_LEFT_TO_RIGHT |
|
||||
MACH64_DST_Y_TOP_TO_BOTTOM) );
|
||||
|
||||
DMAOUTREG( MACH64_DP_PIX_WIDTH, ((fb_bpp << 0) |
|
||||
(fb_bpp << 4) |
|
||||
(fb_bpp << 8) |
|
||||
(fb_bpp << 16) |
|
||||
(fb_bpp << 28)) );
|
||||
|
||||
DMAOUTREG( MACH64_DP_WRITE_MASK, 0xffffffff );
|
||||
DMAOUTREG( MACH64_DP_MIX, (MACH64_BKGD_MIX_D |
|
||||
MACH64_FRGD_MIX_S) );
|
||||
DMAOUTREG( MACH64_DP_SRC, (MACH64_BKGD_SRC_BKGD_CLR |
|
||||
MACH64_FRGD_SRC_BLIT |
|
||||
MACH64_MONO_SRC_ONE) );
|
||||
|
||||
DMAOUTREG( MACH64_SRC_OFF_PITCH, dev_priv->back_offset_pitch );
|
||||
DMAOUTREG( MACH64_DST_OFF_PITCH, dev_priv->front_offset_pitch );
|
||||
|
||||
for ( i = 0 ; i < nbox ; i++ ) {
|
||||
int x = pbox[i].x1;
|
||||
int y = pbox[i].y1;
|
||||
int w = pbox[i].x2 - x;
|
||||
int h = pbox[i].y2 - y;
|
||||
|
||||
DRM_DEBUG( "dispatch swap %d,%d-%d,%d\n",
|
||||
pbox[i].x1, pbox[i].y1,
|
||||
pbox[i].x2, pbox[i].y2 );
|
||||
|
||||
DMAOUTREG( MACH64_SRC_WIDTH1, w );
|
||||
DMAOUTREG( MACH64_SRC_Y_X, (x << 16) | y );
|
||||
DMAOUTREG( MACH64_DST_Y_X, (x << 16) | y );
|
||||
DMAOUTREG( MACH64_DST_WIDTH_HEIGHT, (h << 16) | w );
|
||||
|
||||
}
|
||||
|
||||
DMAADVANCE( dev_priv, 1 );
|
||||
|
||||
if (dev_priv->driver_mode == MACH64_MODE_DMA_ASYNC) {
|
||||
for (i = 0; i < MACH64_MAX_QUEUED_FRAMES - 1; i++) {
|
||||
dev_priv->frame_ofs[i] = dev_priv->frame_ofs[i+1];
|
||||
}
|
||||
dev_priv->frame_ofs[i] = GETRINGOFFSET();
|
||||
|
||||
dev_priv->sarea_priv->frames_queued++;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mach64_do_get_frames_queued( drm_mach64_private_t *dev_priv )
|
||||
{
|
||||
drm_mach64_descriptor_ring_t *ring = &dev_priv->ring;
|
||||
drm_mach64_sarea_t *sarea_priv = dev_priv->sarea_priv;
|
||||
int i, start;
|
||||
u32 head, tail, ofs;
|
||||
|
||||
DRM_DEBUG( "%s\n", __FUNCTION__ );
|
||||
|
||||
if (sarea_priv->frames_queued == 0)
|
||||
return 0;
|
||||
|
||||
tail = ring->tail;
|
||||
mach64_ring_tick( dev_priv, ring );
|
||||
head = ring->head;
|
||||
|
||||
start = ( MACH64_MAX_QUEUED_FRAMES -
|
||||
DRM_MIN(MACH64_MAX_QUEUED_FRAMES, sarea_priv->frames_queued) );
|
||||
|
||||
if ( head == tail ) {
|
||||
sarea_priv->frames_queued = 0;
|
||||
for (i = start; i < MACH64_MAX_QUEUED_FRAMES; i++) {
|
||||
dev_priv->frame_ofs[i] = ~0;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
for ( i = start; i < MACH64_MAX_QUEUED_FRAMES; i++ ) {
|
||||
ofs = dev_priv->frame_ofs[i];
|
||||
DRM_DEBUG( "frame_ofs[%d] ofs: %d\n", i, ofs );
|
||||
if ( ofs == ~0 ||
|
||||
( head < tail && (ofs < head || ofs >= tail) ) ||
|
||||
( head > tail && (ofs < head && ofs >= tail) ) ) {
|
||||
sarea_priv->frames_queued = (MACH64_MAX_QUEUED_FRAMES - 1) - i;
|
||||
dev_priv->frame_ofs[i] = ~0;
|
||||
}
|
||||
}
|
||||
|
||||
return sarea_priv->frames_queued;
|
||||
}
|
||||
|
||||
/* Copy and verify a client submited buffer.
|
||||
* FIXME: Make an assembly optimized version
|
||||
*/
|
||||
static __inline__ int copy_and_verify_from_user( u32 *to, const u32 *from, unsigned long bytes )
|
||||
{
|
||||
unsigned long n = bytes; /* dwords remaining in buffer */
|
||||
|
||||
if ( DRM_VERIFYAREA_READ( from, n ) ) {
|
||||
DRM_ERROR( "%s: verify_area\n", __FUNCTION__ );
|
||||
return DRM_ERR(EFAULT);
|
||||
}
|
||||
|
||||
n >>= 2;
|
||||
|
||||
while ( n > 1 ) {
|
||||
u32 data, reg, count;
|
||||
|
||||
if ( DRM_GET_USER_UNCHECKED( data, from++ ) ) {
|
||||
DRM_ERROR( "%s: get_user\n", __FUNCTION__ );
|
||||
return DRM_ERR(EFAULT);
|
||||
}
|
||||
|
||||
n--;
|
||||
|
||||
reg = le32_to_cpu(data);
|
||||
count = (reg >> 16) + 1;
|
||||
if( count <= n ) {
|
||||
n -= count;
|
||||
reg &= 0xffff;
|
||||
|
||||
/* This is an exact match of Mach64's Setup Engine registers,
|
||||
* excluding SETUP_CNTL (1_C1).
|
||||
*/
|
||||
if( (reg >= 0x0190 && reg < 0x01c1) ||
|
||||
(reg >= 0x01ca && reg <= 0x01cf) ) {
|
||||
*to++ = data;
|
||||
if ( DRM_COPY_FROM_USER_UNCHECKED( to, from, count << 2 ) ) {
|
||||
DRM_ERROR( "%s: copy_from_user\n", __FUNCTION__ );
|
||||
return DRM_ERR(EFAULT);
|
||||
}
|
||||
to += count;
|
||||
} else {
|
||||
DRM_ERROR( "%s: Got bad command: 0x%04x\n", __FUNCTION__, reg );
|
||||
return DRM_ERR(EACCES);
|
||||
}
|
||||
|
||||
from += count;
|
||||
} else {
|
||||
DRM_ERROR( "%s: Got bad command count(=%u) dwords remaining=%lu\n",
|
||||
__FUNCTION__, count, n );
|
||||
return DRM_ERR(EINVAL);
|
||||
}
|
||||
}
|
||||
|
||||
if (n == 0)
|
||||
return 0;
|
||||
else {
|
||||
DRM_ERROR( "%s: Bad buf->used(=%lu)\n", __FUNCTION__, bytes );
|
||||
return DRM_ERR(EINVAL);
|
||||
}
|
||||
}
|
||||
|
||||
static int mach64_dma_dispatch_vertex( DRMFILE filp, drm_device_t *dev, int prim, void *buf,
|
||||
unsigned long used, int discard )
|
||||
{
|
||||
drm_mach64_private_t *dev_priv = dev->dev_private;
|
||||
drm_mach64_sarea_t *sarea_priv = dev_priv->sarea_priv;
|
||||
drm_buf_t *copy_buf;
|
||||
int done = 0;
|
||||
int verify_ret = 0;
|
||||
DMALOCALS;
|
||||
|
||||
DRM_DEBUG( "%s: buf=%p used=%lu nbox=%d\n",
|
||||
__FUNCTION__, buf, used, sarea_priv->nbox );
|
||||
|
||||
if ( used ) {
|
||||
int ret = 0;
|
||||
int i = 0;
|
||||
|
||||
copy_buf = mach64_freelist_get( dev_priv );
|
||||
if (copy_buf == NULL) {
|
||||
DRM_ERROR("%s: couldn't get buffer in DMAGETPTR\n",
|
||||
__FUNCTION__ );
|
||||
return DRM_ERR(EAGAIN);
|
||||
}
|
||||
|
||||
if ( (verify_ret =
|
||||
copy_and_verify_from_user( GETBUFPTR( copy_buf ), buf, used )) == 0 ) {
|
||||
|
||||
copy_buf->used = used;
|
||||
|
||||
DMASETPTR( copy_buf );
|
||||
|
||||
if ( sarea_priv->dirty & ~MACH64_UPLOAD_CLIPRECTS ) {
|
||||
ret = mach64_emit_state( filp, dev_priv );
|
||||
if (ret < 0) return ret;
|
||||
}
|
||||
|
||||
do {
|
||||
/* Emit the next cliprect */
|
||||
if ( i < sarea_priv->nbox ) {
|
||||
ret = mach64_emit_cliprect(filp, dev_priv,
|
||||
&sarea_priv->boxes[i]);
|
||||
if ( ret < 0 ) {
|
||||
/* failed to get buffer */
|
||||
return ret;
|
||||
} else if ( ret != 0 ) {
|
||||
/* null intersection with scissor */
|
||||
continue;
|
||||
}
|
||||
}
|
||||
if ((i >= sarea_priv->nbox - 1))
|
||||
done = 1;
|
||||
|
||||
/* Add the buffer to the DMA queue */
|
||||
DMAADVANCE( dev_priv, done );
|
||||
|
||||
} while ( ++i < sarea_priv->nbox );
|
||||
}
|
||||
|
||||
if (copy_buf->pending && !done) {
|
||||
DMADISCARDBUF();
|
||||
} else if (!done) {
|
||||
/* This buffer wasn't used (no cliprects or verify failed), so place it back
|
||||
* on the free list
|
||||
*/
|
||||
struct list_head *ptr;
|
||||
drm_mach64_freelist_t *entry;
|
||||
#if MACH64_EXTRA_CHECKING
|
||||
list_for_each(ptr, &dev_priv->pending) {
|
||||
entry = list_entry(ptr, drm_mach64_freelist_t, list);
|
||||
if (copy_buf == entry->buf) {
|
||||
DRM_ERROR( "%s: Trying to release a pending buf\n",
|
||||
__FUNCTION__ );
|
||||
return DRM_ERR(EFAULT);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
ptr = dev_priv->placeholders.next;
|
||||
entry = list_entry(ptr, drm_mach64_freelist_t, list);
|
||||
copy_buf->pending = 0;
|
||||
copy_buf->used = 0;
|
||||
entry->buf = copy_buf;
|
||||
entry->discard = 1;
|
||||
list_del(ptr);
|
||||
list_add_tail(ptr, &dev_priv->free_list);
|
||||
}
|
||||
}
|
||||
|
||||
sarea_priv->dirty &= ~MACH64_UPLOAD_CLIPRECTS;
|
||||
sarea_priv->nbox = 0;
|
||||
|
||||
return verify_ret;
|
||||
}
|
||||
|
||||
|
||||
static int mach64_dma_dispatch_blit( DRMFILE filp, drm_device_t *dev,
|
||||
drm_mach64_blit_t *blit )
|
||||
{
|
||||
drm_mach64_private_t *dev_priv = dev->dev_private;
|
||||
drm_device_dma_t *dma = dev->dma;
|
||||
int dword_shift, dwords;
|
||||
drm_buf_t *buf;
|
||||
DMALOCALS;
|
||||
|
||||
/* The compiler won't optimize away a division by a variable,
|
||||
* even if the only legal values are powers of two. Thus, we'll
|
||||
* use a shift instead.
|
||||
*/
|
||||
switch ( blit->format ) {
|
||||
case MACH64_DATATYPE_ARGB8888:
|
||||
dword_shift = 0;
|
||||
break;
|
||||
case MACH64_DATATYPE_ARGB1555:
|
||||
case MACH64_DATATYPE_RGB565:
|
||||
case MACH64_DATATYPE_VYUY422:
|
||||
case MACH64_DATATYPE_YVYU422:
|
||||
case MACH64_DATATYPE_ARGB4444:
|
||||
dword_shift = 1;
|
||||
break;
|
||||
case MACH64_DATATYPE_CI8:
|
||||
case MACH64_DATATYPE_RGB8:
|
||||
dword_shift = 2;
|
||||
break;
|
||||
default:
|
||||
DRM_ERROR( "invalid blit format %d\n", blit->format );
|
||||
return DRM_ERR(EINVAL);
|
||||
}
|
||||
|
||||
/* Dispatch the blit buffer.
|
||||
*/
|
||||
buf = dma->buflist[blit->idx];
|
||||
|
||||
if ( buf->filp != filp ) {
|
||||
DRM_ERROR( "process %d (filp %p) using buffer with filp %p\n",
|
||||
DRM_CURRENTPID, filp, buf->filp );
|
||||
return DRM_ERR(EINVAL);
|
||||
}
|
||||
|
||||
if ( buf->pending ) {
|
||||
DRM_ERROR( "sending pending buffer %d\n", blit->idx );
|
||||
return DRM_ERR(EINVAL);
|
||||
}
|
||||
|
||||
/* Set buf->used to the bytes of blit data based on the blit dimensions
|
||||
* and verify the size. When the setup is emitted to the buffer with
|
||||
* the DMA* macros below, buf->used is incremented to include the bytes
|
||||
* used for setup as well as the blit data.
|
||||
*/
|
||||
dwords = (blit->width * blit->height) >> dword_shift;
|
||||
buf->used = dwords << 2;
|
||||
if ( buf->used <= 0 ||
|
||||
buf->used > MACH64_BUFFER_SIZE - MACH64_HOSTDATA_BLIT_OFFSET ) {
|
||||
DRM_ERROR( "Invalid blit size: %d bytes\n", buf->used );
|
||||
return DRM_ERR(EINVAL);
|
||||
}
|
||||
|
||||
/* FIXME: Use a last buffer flag and reduce the state emitted for subsequent,
|
||||
* continuation buffers?
|
||||
*/
|
||||
|
||||
/* Blit via BM_HOSTDATA (gui-master) - like HOST_DATA[0-15], but doesn't require
|
||||
* a register command every 16 dwords. State setup is added at the start of the
|
||||
* buffer -- the client leaves space for this based on MACH64_HOSTDATA_BLIT_OFFSET
|
||||
*/
|
||||
DMASETPTR( buf );
|
||||
|
||||
DMAOUTREG( MACH64_Z_CNTL, 0 );
|
||||
DMAOUTREG( MACH64_SCALE_3D_CNTL, 0 );
|
||||
|
||||
DMAOUTREG( MACH64_SC_LEFT_RIGHT, 0 | ( 8191 << 16 ) ); /* no scissor */
|
||||
DMAOUTREG( MACH64_SC_TOP_BOTTOM, 0 | ( 16383 << 16 ) );
|
||||
|
||||
DMAOUTREG( MACH64_CLR_CMP_CNTL, 0 ); /* disable */
|
||||
DMAOUTREG( MACH64_GUI_TRAJ_CNTL,
|
||||
MACH64_DST_X_LEFT_TO_RIGHT
|
||||
| MACH64_DST_Y_TOP_TO_BOTTOM );
|
||||
|
||||
DMAOUTREG( MACH64_DP_PIX_WIDTH,
|
||||
( blit->format << 0 ) /* dst pix width */
|
||||
| ( blit->format << 4 ) /* composite pix width */
|
||||
| ( blit->format << 8 ) /* src pix width */
|
||||
| ( blit->format << 16 ) /* host data pix width */
|
||||
| ( blit->format << 28 ) /* scaler/3D pix width */
|
||||
);
|
||||
|
||||
DMAOUTREG( MACH64_DP_WRITE_MASK, 0xffffffff ); /* enable all planes */
|
||||
DMAOUTREG( MACH64_DP_MIX,
|
||||
MACH64_BKGD_MIX_D
|
||||
| MACH64_FRGD_MIX_S );
|
||||
DMAOUTREG( MACH64_DP_SRC,
|
||||
MACH64_BKGD_SRC_BKGD_CLR
|
||||
| MACH64_FRGD_SRC_HOST
|
||||
| MACH64_MONO_SRC_ONE );
|
||||
|
||||
DMAOUTREG( MACH64_DST_OFF_PITCH, (blit->pitch << 22) | (blit->offset >> 3) );
|
||||
DMAOUTREG( MACH64_DST_X_Y, (blit->y << 16) | blit->x );
|
||||
DMAOUTREG( MACH64_DST_WIDTH_HEIGHT, (blit->height << 16) | blit->width );
|
||||
|
||||
DRM_DEBUG( "%s: %d bytes\n", __FUNCTION__, buf->used );
|
||||
|
||||
/* Add the buffer to the queue */
|
||||
DMAADVANCEHOSTDATA( dev_priv );
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* ================================================================
|
||||
* IOCTL functions
|
||||
*/
|
||||
|
||||
int mach64_dma_clear( DRM_IOCTL_ARGS )
|
||||
{
|
||||
DRM_DEVICE;
|
||||
drm_mach64_private_t *dev_priv = dev->dev_private;
|
||||
drm_mach64_sarea_t *sarea_priv = dev_priv->sarea_priv;
|
||||
drm_mach64_clear_t clear;
|
||||
int ret;
|
||||
|
||||
DRM_DEBUG( "%s: pid=%d\n", __FUNCTION__, DRM_CURRENTPID );
|
||||
|
||||
LOCK_TEST_WITH_RETURN( dev, filp );
|
||||
|
||||
DRM_COPY_FROM_USER_IOCTL( clear, (drm_mach64_clear_t *)data,
|
||||
sizeof(clear) );
|
||||
|
||||
if ( sarea_priv->nbox > MACH64_NR_SAREA_CLIPRECTS )
|
||||
sarea_priv->nbox = MACH64_NR_SAREA_CLIPRECTS;
|
||||
|
||||
ret = mach64_dma_dispatch_clear( filp, dev, clear.flags,
|
||||
clear.x, clear.y, clear.w, clear.h,
|
||||
clear.clear_color, clear.clear_depth );
|
||||
|
||||
/* Make sure we restore the 3D state next time.
|
||||
*/
|
||||
sarea_priv->dirty |= (MACH64_UPLOAD_CONTEXT |
|
||||
MACH64_UPLOAD_MISC);
|
||||
return ret;
|
||||
}
|
||||
|
||||
int mach64_dma_swap( DRM_IOCTL_ARGS )
|
||||
{
|
||||
DRM_DEVICE;
|
||||
drm_mach64_private_t *dev_priv = dev->dev_private;
|
||||
drm_mach64_sarea_t *sarea_priv = dev_priv->sarea_priv;
|
||||
int ret;
|
||||
|
||||
DRM_DEBUG( "%s: pid=%d\n", __FUNCTION__, DRM_CURRENTPID );
|
||||
|
||||
LOCK_TEST_WITH_RETURN( dev, filp );
|
||||
|
||||
if ( sarea_priv->nbox > MACH64_NR_SAREA_CLIPRECTS )
|
||||
sarea_priv->nbox = MACH64_NR_SAREA_CLIPRECTS;
|
||||
|
||||
ret = mach64_dma_dispatch_swap( filp, dev );
|
||||
|
||||
/* Make sure we restore the 3D state next time.
|
||||
*/
|
||||
sarea_priv->dirty |= (MACH64_UPLOAD_CONTEXT |
|
||||
MACH64_UPLOAD_MISC);
|
||||
return ret;
|
||||
}
|
||||
|
||||
int mach64_dma_vertex( DRM_IOCTL_ARGS )
|
||||
{
|
||||
DRM_DEVICE;
|
||||
drm_mach64_private_t *dev_priv = dev->dev_private;
|
||||
drm_mach64_sarea_t *sarea_priv = dev_priv->sarea_priv;
|
||||
drm_mach64_vertex_t vertex;
|
||||
|
||||
LOCK_TEST_WITH_RETURN( dev, filp );
|
||||
|
||||
if ( !dev_priv ) {
|
||||
DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ );
|
||||
return DRM_ERR(EINVAL);
|
||||
}
|
||||
|
||||
DRM_COPY_FROM_USER_IOCTL( vertex, (drm_mach64_vertex_t *)data,
|
||||
sizeof(vertex) );
|
||||
|
||||
DRM_DEBUG( "%s: pid=%d buf=%p used=%lu discard=%d\n",
|
||||
__FUNCTION__, DRM_CURRENTPID,
|
||||
vertex.buf, vertex.used, vertex.discard );
|
||||
|
||||
if ( vertex.prim < 0 ||
|
||||
vertex.prim > MACH64_PRIM_POLYGON ) {
|
||||
DRM_ERROR( "buffer prim %d\n", vertex.prim );
|
||||
return DRM_ERR(EINVAL);
|
||||
}
|
||||
|
||||
if ( vertex.used > MACH64_BUFFER_SIZE || (vertex.used & 3) != 0) {
|
||||
DRM_ERROR( "Invalid vertex buffer size: %lu bytes\n", vertex.used );
|
||||
return DRM_ERR(EINVAL);
|
||||
}
|
||||
|
||||
if ( sarea_priv->nbox > MACH64_NR_SAREA_CLIPRECTS )
|
||||
sarea_priv->nbox = MACH64_NR_SAREA_CLIPRECTS;
|
||||
|
||||
return mach64_dma_dispatch_vertex( filp, dev, vertex.prim, vertex.buf,
|
||||
vertex.used, vertex.discard );
|
||||
}
|
||||
|
||||
int mach64_dma_blit( DRM_IOCTL_ARGS )
|
||||
{
|
||||
DRM_DEVICE;
|
||||
drm_device_dma_t *dma = dev->dma;
|
||||
drm_mach64_private_t *dev_priv = dev->dev_private;
|
||||
drm_mach64_sarea_t *sarea_priv = dev_priv->sarea_priv;
|
||||
drm_mach64_blit_t blit;
|
||||
int ret;
|
||||
|
||||
LOCK_TEST_WITH_RETURN( dev, filp );
|
||||
|
||||
DRM_COPY_FROM_USER_IOCTL( blit, (drm_mach64_blit_t *)data,
|
||||
sizeof(blit) );
|
||||
|
||||
DRM_DEBUG( "%s: pid=%d index=%d\n",
|
||||
__FUNCTION__, DRM_CURRENTPID, blit.idx );
|
||||
|
||||
if ( blit.idx < 0 || blit.idx >= dma->buf_count ) {
|
||||
DRM_ERROR( "buffer index %d (of %d max)\n",
|
||||
blit.idx, dma->buf_count - 1 );
|
||||
return DRM_ERR(EINVAL);
|
||||
}
|
||||
|
||||
ret = mach64_dma_dispatch_blit( filp, dev, &blit );
|
||||
|
||||
/* Make sure we restore the 3D state next time.
|
||||
*/
|
||||
sarea_priv->dirty |= (MACH64_UPLOAD_CONTEXT |
|
||||
MACH64_UPLOAD_MISC |
|
||||
MACH64_UPLOAD_CLIPRECTS);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
int mach64_get_param( DRM_IOCTL_ARGS )
|
||||
{
|
||||
DRM_DEVICE;
|
||||
drm_mach64_private_t *dev_priv = dev->dev_private;
|
||||
drm_mach64_getparam_t param;
|
||||
int value;
|
||||
|
||||
DRM_DEBUG( "%s\n", __FUNCTION__ );
|
||||
|
||||
if ( !dev_priv ) {
|
||||
DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ );
|
||||
return DRM_ERR(EINVAL);
|
||||
}
|
||||
|
||||
DRM_COPY_FROM_USER_IOCTL( param, (drm_mach64_getparam_t *)data,
|
||||
sizeof(param) );
|
||||
|
||||
switch ( param.param ) {
|
||||
case MACH64_PARAM_FRAMES_QUEUED:
|
||||
/* Needs lock since it calls mach64_ring_tick() */
|
||||
LOCK_TEST_WITH_RETURN( dev, filp );
|
||||
value = mach64_do_get_frames_queued( dev_priv );
|
||||
break;
|
||||
case MACH64_PARAM_IRQ_NR:
|
||||
value = dev->irq;
|
||||
break;
|
||||
default:
|
||||
return DRM_ERR(EINVAL);
|
||||
}
|
||||
|
||||
if ( DRM_COPY_TO_USER( param.value, &value, sizeof(int) ) ) {
|
||||
DRM_ERROR( "copy_to_user\n" );
|
||||
return DRM_ERR(EFAULT);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
Loading…
Add table
Reference in a new issue