fix type definitions, macro cleanups. Fix up VB ageing as per Radeon.

This commit is contained in:
Alan Hourihane 2001-01-22 21:06:39 +00:00
parent 93e8ee60d3
commit 826c51c084
3 changed files with 37 additions and 35 deletions

View file

@ -106,7 +106,7 @@ static u32 r128_cce_microcode[] = {
} while (0)
int R128_READ_PLL(drm_device_t *dev, int addr)
u32 R128_READ_PLL(drm_device_t *dev, int addr)
{
drm_r128_private_t *dev_priv = dev->dev_private;
@ -167,7 +167,7 @@ static int r128_do_wait_for_fifo( drm_r128_private_t *dev_priv, int entries )
int i;
for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
int slots = R128_READ( R128_GUI_STAT ) & R128_GUI_FIFOCNT_MASK;
u32 slots = R128_READ( R128_GUI_STAT ) & R128_GUI_FIFOCNT_MASK;
if ( slots >= entries ) return 0;
udelay( 1 );
}
@ -242,7 +242,7 @@ static int r128_do_cce_idle( drm_r128_private_t *dev_priv )
if ( *dev_priv->ring.head == dev_priv->ring.tail )
#endif
{
int pm4stat = R128_READ( R128_PM4_STAT );
u32 pm4stat = R128_READ( R128_PM4_STAT );
if ( ( (pm4stat & R128_PM4_FIFOCNT_MASK) >=
dev_priv->cce_fifo_size ) &&
!(pm4stat & (R128_PM4_BUSY |
@ -602,7 +602,7 @@ static int r128_do_init_cce( drm_device_t *dev, drm_r128_init_t *init )
#ifdef DEBUG_RING_AFTER_INIT
{
int last_dispatch;
u32 last_dispatch;
RING_LOCALS;
r128_do_cce_start( dev_priv );

View file

@ -268,6 +268,9 @@ extern int r128_context_switch_complete(drm_device_t *dev, int new);
#define R128_GUI_SCRATCH_REG4 0x15f0
#define R128_GUI_SCRATCH_REG5 0x15f4
#define R128_WAIT_UNTIL 0x1720
#define R128_EVENT_CRTC_OFFSET (1 << 0)
#define R128_GUI_STAT 0x1740
# define R128_GUI_FIFOCNT_MASK 0x0fff
# define R128_GUI_ACTIVE (1 << 31)
@ -408,21 +411,32 @@ extern int r128_context_switch_complete(drm_device_t *dev, int new);
#define R128_BASE(reg) ((u32)(dev_priv->mmio->handle))
#define R128_ADDR(reg) (R128_BASE(reg) + reg)
#define R128_DEREF(reg) *(__volatile__ int *)R128_ADDR(reg)
#define R128_DEREF(reg) *(__volatile__ u32 *)R128_ADDR(reg)
#define R128_READ(reg) R128_DEREF(reg)
#define R128_WRITE(reg,val) do { R128_DEREF(reg) = val; } while (0)
#define R128_DEREF8(reg) *(__volatile__ char *)R128_ADDR(reg)
#define R128_DEREF8(reg) *(__volatile__ u8 *)R128_ADDR(reg)
#define R128_READ8(reg) R128_DEREF8(reg)
#define R128_WRITE8(reg,val) do { R128_DEREF8(reg) = val; } while (0)
#define VB_AGE_CHECK_WITH_RET( dev_priv ) \
do { \
drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; \
if ( sarea_priv->last_dispatch >= R128_MAX_VB_AGE ) { \
int __ret = r128_do_cce_idle( dev_priv ); \
if ( __ret < 0 ) return __ret; \
sarea_priv->last_dispatch = 0; \
r128_freelist_reset( dev ); \
} \
} while (0)
#define R128_WRITE_PLL(addr,val) \
do { \
R128_WRITE8(R128_CLOCK_CNTL_INDEX, ((addr) & 0x1f) | R128_PLL_WR_EN); \
R128_WRITE(R128_CLOCK_CNTL_DATA, (val)); \
} while (0)
extern int R128_READ_PLL(drm_device_t *dev, int addr);
extern u32 R128_READ_PLL(drm_device_t *dev, int addr);
#define R128CCE0(p,r,n) ((p) | ((n) << 16) | ((r) >> 2))
#define R128CCE1(p,r1,r2) ((p) | (((r2) >> 2) << 11) | ((r1) >> 2))
@ -481,6 +495,12 @@ extern int R128_READ_PLL(drm_device_t *dev, int addr);
write &= tail_mask; \
} while (0)
#define R128_WAIT_UNTIL_PAGE_FLIPPED() \
do { \
OUT_RING( CCE_PACKET0( R128_WAIT_UNTIL, 0 ) ); \
OUT_RING( R128_EVENT_CRTC_OFFSET ); \
} while (0)
#define R128_PERFORMANCE_BOXES 0
#endif /* __R128_DRV_H__ */

View file

@ -578,7 +578,9 @@ static void r128_cce_dispatch_flip( drm_device_t *dev )
r128_cce_performance_boxes( dev_priv );
#endif
BEGIN_RING( 2 );
BEGIN_RING( 4 );
R128_WAIT_UNTIL_PAGE_FLIPPED();
OUT_RING( CCE_PACKET0( R128_CRTC_OFFSET, 0 ) );
@ -679,15 +681,6 @@ static void r128_cce_dispatch_vertex( drm_device_t *dev,
dev_priv->sarea_priv->last_dispatch++;
#if 0
if ( dev_priv->submit_age == R128_MAX_VB_AGE ) {
ret = r128_do_cce_idle( dev_priv );
if ( ret < 0 ) return ret;
dev_priv->submit_age = 0;
r128_freelist_reset( dev );
}
#endif
sarea_priv->dirty &= ~R128_UPLOAD_CLIPRECTS;
sarea_priv->nbox = 0;
}
@ -752,15 +745,6 @@ static void r128_cce_dispatch_indirect( drm_device_t *dev,
}
dev_priv->sarea_priv->last_dispatch++;
#if 0
if ( dev_priv->submit_age == R128_MAX_VB_AGE ) {
ret = r128_do_cce_idle( dev_priv );
if ( ret < 0 ) return ret;
dev_priv->submit_age = 0;
r128_freelist_reset( dev );
}
#endif
}
static void r128_cce_dispatch_indices( drm_device_t *dev,
@ -846,15 +830,6 @@ static void r128_cce_dispatch_indices( drm_device_t *dev,
dev_priv->sarea_priv->last_dispatch++;
#if 0
if ( dev_priv->submit_age == R128_MAX_VB_AGE ) {
ret = r128_do_cce_idle( dev_priv );
if ( ret < 0 ) return ret;
dev_priv->submit_age = 0;
r128_freelist_reset( dev );
}
#endif
sarea_priv->dirty &= ~R128_UPLOAD_CLIPRECTS;
sarea_priv->nbox = 0;
}
@ -1480,6 +1455,8 @@ int r128_cce_vertex( struct inode *inode, struct file *filp,
return -EINVAL;
}
VB_AGE_CHECK_WITH_RET( dev_priv );
buf = dma->buflist[vertex.idx];
buf_priv = buf->dev_private;
@ -1543,6 +1520,8 @@ int r128_cce_indices( struct inode *inode, struct file *filp,
return -EINVAL;
}
VB_AGE_CHECK_WITH_RET( dev_priv );
buf = dma->buflist[elts.idx];
buf_priv = buf->dev_private;
@ -1582,6 +1561,7 @@ int r128_cce_blit( struct inode *inode, struct file *filp,
{
drm_file_t *priv = filp->private_data;
drm_device_t *dev = priv->dev;
drm_r128_private_t *dev_priv = dev->dev_private;
drm_device_dma_t *dma = dev->dma;
drm_r128_blit_t blit;
@ -1604,6 +1584,8 @@ int r128_cce_blit( struct inode *inode, struct file *filp,
return -EINVAL;
}
VB_AGE_CHECK_WITH_RET( dev_priv );
return r128_cce_dispatch_blit( dev, &blit );
}