mirror of
https://gitlab.freedesktop.org/mesa/drm.git
synced 2026-05-08 08:08:05 +02:00
fix type definitions, macro cleanups. Fix up VB ageing as per Radeon.
This commit is contained in:
parent
93e8ee60d3
commit
826c51c084
3 changed files with 37 additions and 35 deletions
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@ -106,7 +106,7 @@ static u32 r128_cce_microcode[] = {
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} while (0)
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int R128_READ_PLL(drm_device_t *dev, int addr)
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u32 R128_READ_PLL(drm_device_t *dev, int addr)
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{
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drm_r128_private_t *dev_priv = dev->dev_private;
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@ -167,7 +167,7 @@ static int r128_do_wait_for_fifo( drm_r128_private_t *dev_priv, int entries )
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int i;
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for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
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int slots = R128_READ( R128_GUI_STAT ) & R128_GUI_FIFOCNT_MASK;
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u32 slots = R128_READ( R128_GUI_STAT ) & R128_GUI_FIFOCNT_MASK;
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if ( slots >= entries ) return 0;
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udelay( 1 );
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}
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@ -242,7 +242,7 @@ static int r128_do_cce_idle( drm_r128_private_t *dev_priv )
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if ( *dev_priv->ring.head == dev_priv->ring.tail )
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#endif
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{
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int pm4stat = R128_READ( R128_PM4_STAT );
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u32 pm4stat = R128_READ( R128_PM4_STAT );
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if ( ( (pm4stat & R128_PM4_FIFOCNT_MASK) >=
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dev_priv->cce_fifo_size ) &&
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!(pm4stat & (R128_PM4_BUSY |
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@ -602,7 +602,7 @@ static int r128_do_init_cce( drm_device_t *dev, drm_r128_init_t *init )
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#ifdef DEBUG_RING_AFTER_INIT
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{
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int last_dispatch;
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u32 last_dispatch;
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RING_LOCALS;
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r128_do_cce_start( dev_priv );
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@ -268,6 +268,9 @@ extern int r128_context_switch_complete(drm_device_t *dev, int new);
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#define R128_GUI_SCRATCH_REG4 0x15f0
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#define R128_GUI_SCRATCH_REG5 0x15f4
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#define R128_WAIT_UNTIL 0x1720
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#define R128_EVENT_CRTC_OFFSET (1 << 0)
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#define R128_GUI_STAT 0x1740
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# define R128_GUI_FIFOCNT_MASK 0x0fff
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# define R128_GUI_ACTIVE (1 << 31)
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@ -408,21 +411,32 @@ extern int r128_context_switch_complete(drm_device_t *dev, int new);
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#define R128_BASE(reg) ((u32)(dev_priv->mmio->handle))
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#define R128_ADDR(reg) (R128_BASE(reg) + reg)
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#define R128_DEREF(reg) *(__volatile__ int *)R128_ADDR(reg)
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#define R128_DEREF(reg) *(__volatile__ u32 *)R128_ADDR(reg)
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#define R128_READ(reg) R128_DEREF(reg)
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#define R128_WRITE(reg,val) do { R128_DEREF(reg) = val; } while (0)
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#define R128_DEREF8(reg) *(__volatile__ char *)R128_ADDR(reg)
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#define R128_DEREF8(reg) *(__volatile__ u8 *)R128_ADDR(reg)
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#define R128_READ8(reg) R128_DEREF8(reg)
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#define R128_WRITE8(reg,val) do { R128_DEREF8(reg) = val; } while (0)
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#define VB_AGE_CHECK_WITH_RET( dev_priv ) \
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do { \
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drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; \
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if ( sarea_priv->last_dispatch >= R128_MAX_VB_AGE ) { \
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int __ret = r128_do_cce_idle( dev_priv ); \
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if ( __ret < 0 ) return __ret; \
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sarea_priv->last_dispatch = 0; \
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r128_freelist_reset( dev ); \
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} \
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} while (0)
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#define R128_WRITE_PLL(addr,val) \
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do { \
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R128_WRITE8(R128_CLOCK_CNTL_INDEX, ((addr) & 0x1f) | R128_PLL_WR_EN); \
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R128_WRITE(R128_CLOCK_CNTL_DATA, (val)); \
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} while (0)
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extern int R128_READ_PLL(drm_device_t *dev, int addr);
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extern u32 R128_READ_PLL(drm_device_t *dev, int addr);
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#define R128CCE0(p,r,n) ((p) | ((n) << 16) | ((r) >> 2))
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#define R128CCE1(p,r1,r2) ((p) | (((r2) >> 2) << 11) | ((r1) >> 2))
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@ -481,6 +495,12 @@ extern int R128_READ_PLL(drm_device_t *dev, int addr);
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write &= tail_mask; \
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} while (0)
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#define R128_WAIT_UNTIL_PAGE_FLIPPED() \
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do { \
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OUT_RING( CCE_PACKET0( R128_WAIT_UNTIL, 0 ) ); \
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OUT_RING( R128_EVENT_CRTC_OFFSET ); \
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} while (0)
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#define R128_PERFORMANCE_BOXES 0
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#endif /* __R128_DRV_H__ */
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@ -578,7 +578,9 @@ static void r128_cce_dispatch_flip( drm_device_t *dev )
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r128_cce_performance_boxes( dev_priv );
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#endif
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BEGIN_RING( 2 );
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BEGIN_RING( 4 );
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R128_WAIT_UNTIL_PAGE_FLIPPED();
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OUT_RING( CCE_PACKET0( R128_CRTC_OFFSET, 0 ) );
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@ -679,15 +681,6 @@ static void r128_cce_dispatch_vertex( drm_device_t *dev,
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dev_priv->sarea_priv->last_dispatch++;
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#if 0
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if ( dev_priv->submit_age == R128_MAX_VB_AGE ) {
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ret = r128_do_cce_idle( dev_priv );
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if ( ret < 0 ) return ret;
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dev_priv->submit_age = 0;
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r128_freelist_reset( dev );
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}
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#endif
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sarea_priv->dirty &= ~R128_UPLOAD_CLIPRECTS;
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sarea_priv->nbox = 0;
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}
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@ -752,15 +745,6 @@ static void r128_cce_dispatch_indirect( drm_device_t *dev,
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}
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dev_priv->sarea_priv->last_dispatch++;
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#if 0
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if ( dev_priv->submit_age == R128_MAX_VB_AGE ) {
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ret = r128_do_cce_idle( dev_priv );
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if ( ret < 0 ) return ret;
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dev_priv->submit_age = 0;
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r128_freelist_reset( dev );
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}
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#endif
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}
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static void r128_cce_dispatch_indices( drm_device_t *dev,
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@ -846,15 +830,6 @@ static void r128_cce_dispatch_indices( drm_device_t *dev,
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dev_priv->sarea_priv->last_dispatch++;
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#if 0
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if ( dev_priv->submit_age == R128_MAX_VB_AGE ) {
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ret = r128_do_cce_idle( dev_priv );
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if ( ret < 0 ) return ret;
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dev_priv->submit_age = 0;
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r128_freelist_reset( dev );
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}
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#endif
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sarea_priv->dirty &= ~R128_UPLOAD_CLIPRECTS;
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sarea_priv->nbox = 0;
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}
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@ -1480,6 +1455,8 @@ int r128_cce_vertex( struct inode *inode, struct file *filp,
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return -EINVAL;
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}
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VB_AGE_CHECK_WITH_RET( dev_priv );
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buf = dma->buflist[vertex.idx];
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buf_priv = buf->dev_private;
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@ -1543,6 +1520,8 @@ int r128_cce_indices( struct inode *inode, struct file *filp,
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return -EINVAL;
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}
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VB_AGE_CHECK_WITH_RET( dev_priv );
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buf = dma->buflist[elts.idx];
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buf_priv = buf->dev_private;
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@ -1582,6 +1561,7 @@ int r128_cce_blit( struct inode *inode, struct file *filp,
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{
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drm_file_t *priv = filp->private_data;
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drm_device_t *dev = priv->dev;
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drm_r128_private_t *dev_priv = dev->dev_private;
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drm_device_dma_t *dma = dev->dma;
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drm_r128_blit_t blit;
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@ -1604,6 +1584,8 @@ int r128_cce_blit( struct inode *inode, struct file *filp,
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return -EINVAL;
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}
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VB_AGE_CHECK_WITH_RET( dev_priv );
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return r128_cce_dispatch_blit( dev, &blit );
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}
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