mirror of
https://gitlab.freedesktop.org/mesa/drm.git
synced 2026-05-08 02:18:06 +02:00
- Added texture support (not yet working; also texblits not implemented
yet)
- Added workaround for overwriting VB problem (does not completely solve
the problem -- Q3A, gloss among others will still demonstrate the
problem)
- Added window offsets support
- Fixed depth offset initialization
- Changed visuals to support 24bpp instead of 32bpp depth buffers to match
Mesa's depth buffer support
This commit is contained in:
Kevin E Martin
parent
56284c6b98
commit
7c7885903a
4 changed files with 74 additions and 49 deletions
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@ -709,6 +709,10 @@ static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init )
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radeon_cp_init_ring_buffer( dev );
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radeon_do_engine_reset( dev );
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#if ROTATE_BUFS
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dev_priv->last_buf = 0;
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#endif
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return 0;
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}
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@ -952,6 +956,9 @@ drm_buf_t *radeon_freelist_get( drm_device_t *dev )
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drm_radeon_buf_priv_t *buf_priv;
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drm_buf_t *buf;
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int i, t;
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#if ROTATE_BUFS
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int start;
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#endif
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/* FIXME: Optimize -- use freelist code */
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@ -962,10 +969,18 @@ drm_buf_t *radeon_freelist_get( drm_device_t *dev )
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return buf;
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}
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#if ROTATE_BUFS
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if (++dev_priv->last_buf >= dma->buf_count)
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dev_priv->last_buf = 0;
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start = dev_priv->last_buf;
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#endif
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for ( t = 0 ; t < dev_priv->usec_timeout ; t++ ) {
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u32 done_age = RADEON_READ( RADEON_LAST_DISPATCH_REG );
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#if ROTATE_BUFS
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for ( i = start ; i < dma->buf_count ; i++ ) {
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#else
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for ( i = 0 ; i < dma->buf_count ; i++ ) {
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#endif
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buf = dma->buflist[i];
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buf_priv = buf->dev_private;
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if ( buf->pending && buf_priv->age <= done_age ) {
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@ -975,6 +990,9 @@ drm_buf_t *radeon_freelist_get( drm_device_t *dev )
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buf->pending = 0;
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return buf;
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}
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#if ROTATE_BUFS
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start = 0;
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#endif
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}
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udelay( 1 );
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}
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@ -986,8 +1004,14 @@ drm_buf_t *radeon_freelist_get( drm_device_t *dev )
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void radeon_freelist_reset( drm_device_t *dev )
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{
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drm_device_dma_t *dma = dev->dma;
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#if ROTATE_BUFS
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drm_radeon_private_t *dev_priv = dev->dev_private;
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#endif
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int i;
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#if ROTATE_BUFS
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dev_priv->last_buf = 0;
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#endif
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for ( i = 0 ; i < dma->buf_count ; i++ ) {
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drm_buf_t *buf = dma->buflist[i];
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drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
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@ -187,11 +187,12 @@ typedef struct {
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unsigned int pp_txablend;
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unsigned int pp_tfactor;
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unsigned int pp_cubic_faces;
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unsigned int pp_border_color;
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#ifdef CUBIC_ENABLE
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unsigned int pp_cubic_faces;
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unsigned int pp_cubic_offset[5];
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#endif
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} drm_radeon_texture_regs_t;
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typedef struct {
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@ -65,6 +65,14 @@ typedef struct drm_radeon_private {
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drm_radeon_freelist_t *head;
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drm_radeon_freelist_t *tail;
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/* FIXME: ROTATE_BUFS is a hask to cycle through bufs until freelist
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code is used. Note this hides a problem with the scratch register
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(used to keep track of last buffer completed) being written to before
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the last buffer has actually completed rendering. */
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#define ROTATE_BUFS 1
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#if ROTATE_BUFS
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int last_buf;
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#endif
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int usec_timeout;
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int is_pci;
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@ -220,10 +228,16 @@ extern int radeon_context_switch_complete(drm_device_t *dev, int new);
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#define RADEON_MC_FB_LOCATION 0x0148
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#define RADEON_MCLK_CNTL 0x0012
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#define RADEON_PP_BORDER_COLOR_0 0x1d40
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#define RADEON_PP_BORDER_COLOR_1 0x1d44
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#define RADEON_PP_BORDER_COLOR_2 0x1d48
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#define RADEON_PP_CNTL 0x1c38
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#define RADEON_PP_LUM_MATRIX 0x1d00
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#define RADEON_PP_MISC 0x1c14
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#define RADEON_PP_ROT_MATRIX_0 0x1d58
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#define RADEON_PP_TXFILTER_0 0x1c54
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#define RADEON_PP_TXFILTER_1 0x1c6c
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#define RADEON_PP_TXFILTER_2 0x1c84
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#define RADEON_RB2D_DSTCACHE_CTLSTAT 0x342c
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# define RADEON_RB2D_DC_FLUSH_ALL 0xf
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@ -299,83 +299,71 @@ static inline void radeon_emit_misc( drm_radeon_private_t *dev_priv )
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static inline void radeon_emit_tex0( drm_radeon_private_t *dev_priv )
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{
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#if 0
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drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
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drm_radeon_context_regs_t *ctx = &sarea_priv->context_state;
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drm_radeon_texture_regs_t *tex = &sarea_priv->tex_state[0];
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int i;
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RING_LOCALS;
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DRM_DEBUG( " %s\n", __FUNCTION__ );
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BEGIN_RING( 7 + RADEON_TEX_MAXLEVELS );
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BEGIN_RING( 9 );
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OUT_RING( CP_PACKET0( RADEON_PRIM_TEX_CNTL_C,
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2 + RADEON_TEX_MAXLEVELS ) );
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OUT_RING( tex->tex_cntl );
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OUT_RING( tex->tex_combine_cntl );
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OUT_RING( ctx->tex_size_pitch_c );
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for ( i = 0 ; i < RADEON_TEX_MAXLEVELS ; i++ ) {
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OUT_RING( tex->tex_offset[i] );
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}
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OUT_RING( CP_PACKET0( RADEON_PP_TXFILTER_0, 5 ) );
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OUT_RING( tex->pp_txfilter );
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OUT_RING( tex->pp_txformat );
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OUT_RING( tex->pp_txoffset );
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OUT_RING( tex->pp_txcblend );
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OUT_RING( tex->pp_txablend );
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OUT_RING( tex->pp_tfactor );
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OUT_RING( CP_PACKET0( RADEON_CONSTANT_COLOR_C, 1 ) );
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OUT_RING( ctx->constant_color_c );
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OUT_RING( tex->tex_border_color );
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OUT_RING( CP_PACKET0( RADEON_PP_BORDER_COLOR_0, 0 ) );
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OUT_RING( tex->pp_border_color );
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ADVANCE_RING();
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#endif
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}
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static inline void radeon_emit_tex1( drm_radeon_private_t *dev_priv )
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{
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#if 0
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drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
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drm_radeon_texture_regs_t *tex = &sarea_priv->tex_state[1];
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int i;
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RING_LOCALS;
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DRM_DEBUG( " %s\n", __FUNCTION__ );
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BEGIN_RING( 5 + RADEON_TEX_MAXLEVELS );
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BEGIN_RING( 9 );
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OUT_RING( CP_PACKET0( RADEON_SEC_TEX_CNTL_C,
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1 + RADEON_TEX_MAXLEVELS ) );
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OUT_RING( tex->tex_cntl );
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OUT_RING( tex->tex_combine_cntl );
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for ( i = 0 ; i < RADEON_TEX_MAXLEVELS ; i++ ) {
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OUT_RING( tex->tex_offset[i] );
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}
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OUT_RING( CP_PACKET0( RADEON_PP_TXFILTER_1, 5 ) );
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OUT_RING( tex->pp_txfilter );
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OUT_RING( tex->pp_txformat );
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OUT_RING( tex->pp_txoffset );
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OUT_RING( tex->pp_txcblend );
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OUT_RING( tex->pp_txablend );
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OUT_RING( tex->pp_tfactor );
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OUT_RING( CP_PACKET0( RADEON_SEC_TEXTURE_BORDER_COLOR_C, 0 ) );
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OUT_RING( tex->tex_border_color );
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OUT_RING( CP_PACKET0( RADEON_PP_BORDER_COLOR_1, 0 ) );
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OUT_RING( tex->pp_border_color );
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ADVANCE_RING();
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#endif
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}
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static inline void radeon_emit_tex2( drm_radeon_private_t *dev_priv )
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{
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#if 0
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drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
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drm_radeon_texture_regs_t *tex = &sarea_priv->tex_state[2];
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int i;
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RING_LOCALS;
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DRM_DEBUG( " %s\n", __FUNCTION__ );
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BEGIN_RING( 5 + RADEON_TEX_MAXLEVELS );
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BEGIN_RING( 9 );
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OUT_RING( CP_PACKET0( RADEON_SEC_TEX_CNTL_C,
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1 + RADEON_TEX_MAXLEVELS ) );
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OUT_RING( tex->tex_cntl );
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OUT_RING( tex->tex_combine_cntl );
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for ( i = 0 ; i < RADEON_TEX_MAXLEVELS ; i++ ) {
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OUT_RING( tex->tex_offset[i] );
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}
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OUT_RING( CP_PACKET0( RADEON_PP_TXFILTER_2, 5 ) );
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OUT_RING( tex->pp_txfilter );
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OUT_RING( tex->pp_txformat );
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OUT_RING( tex->pp_txoffset );
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OUT_RING( tex->pp_txcblend );
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OUT_RING( tex->pp_txablend );
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OUT_RING( tex->pp_tfactor );
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OUT_RING( CP_PACKET0( RADEON_SEC_TEXTURE_BORDER_COLOR_C, 0 ) );
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OUT_RING( tex->tex_border_color );
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OUT_RING( CP_PACKET0( RADEON_PP_BORDER_COLOR_2, 0 ) );
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OUT_RING( tex->pp_border_color );
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ADVANCE_RING();
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#endif
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}
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static inline void radeon_emit_state( drm_radeon_private_t *dev_priv )
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@ -1083,10 +1071,7 @@ static void radeon_cp_dispatch_indices( drm_device_t *dev,
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drm_radeon_private_t *dev_priv = dev->dev_private;
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drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
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drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
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int vertsize = sarea_priv->vertsize;
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int format = sarea_priv->vc_format;
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int index = buf->idx;
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int offset = dev_priv->buffers->offset - dev->agp->base;
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int prim = buf_priv->prim;
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@ -1477,7 +1462,8 @@ int radeon_cp_indices( struct inode *inode, struct file *filp,
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return -EINVAL;
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}
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if ( (buf->offset + elts.start) & 0x3 ) {
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DRM_ERROR( "buffer start 0x%x\n", buf->offset + elts.start );
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DRM_ERROR( "buffer start 0x%x\n",
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(u32)(buf->offset + elts.start) );
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return -EINVAL;
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}
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