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synced 2025-12-27 07:00:12 +01:00
Fix another backwards compatibility bug. Clean up some tests.
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parent
84159540da
commit
62ba1e3537
2 changed files with 55 additions and 63 deletions
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@ -131,17 +131,6 @@ typedef union {
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/* Primitive types
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*/
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#define RADEON_CP_VC_CNTL_PRIM_TYPE_NONE 0x00000000
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#define RADEON_CP_VC_CNTL_PRIM_TYPE_POINT 0x00000001
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#define RADEON_CP_VC_CNTL_PRIM_TYPE_LINE 0x00000002
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#define RADEON_CP_VC_CNTL_PRIM_TYPE_LINE_STRIP 0x00000003
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#define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST 0x00000004
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#define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN 0x00000005
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#define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_STRIP 0x00000006
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#define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_TYPE_2 0x00000007
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#define RADEON_CP_VC_CNTL_PRIM_TYPE_RECT_LIST 0x00000008
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#define RADEON_CP_VC_CNTL_PRIM_TYPE_3VRT_POINT_LIST 0x00000009
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#define RADEON_CP_VC_CNTL_PRIM_TYPE_3VRT_LINE_LIST 0x0000000a
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#define RADEON_POINTS 0x1
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#define RADEON_LINES 0x2
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#define RADEON_LINE_STRIP 0x3
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@ -628,40 +628,40 @@ static void radeon_cp_dispatch_vertex( drm_device_t *dev,
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prim->numverts);
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switch (prim->prim & RADEON_PRIM_TYPE_MASK) {
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case RADEON_CP_VC_CNTL_PRIM_TYPE_NONE:
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case RADEON_CP_VC_CNTL_PRIM_TYPE_POINT:
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case RADEON_PRIM_TYPE_NONE:
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case RADEON_PRIM_TYPE_POINT:
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if (prim->numverts < 1) {
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DRM_ERROR( "Bad nr verts for line %d\n",
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prim->numverts);
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return;
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}
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break;
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case RADEON_CP_VC_CNTL_PRIM_TYPE_LINE:
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if (prim->numverts & 1) {
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case RADEON_PRIM_TYPE_LINE:
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if ((prim->numverts & 1) || prim->numverts == 0) {
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DRM_ERROR( "Bad nr verts for line %d\n",
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prim->numverts);
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return;
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}
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break;
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case RADEON_CP_VC_CNTL_PRIM_TYPE_LINE_STRIP:
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case RADEON_PRIM_TYPE_LINE_STRIP:
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if (prim->numverts < 2) {
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DRM_ERROR( "Bad nr verts for line_strip %d\n",
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prim->numverts);
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return;
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}
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break;
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case RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST:
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case RADEON_CP_VC_CNTL_PRIM_TYPE_3VRT_POINT_LIST:
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case RADEON_CP_VC_CNTL_PRIM_TYPE_3VRT_LINE_LIST:
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case RADEON_CP_VC_CNTL_PRIM_TYPE_RECT_LIST:
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if (prim->numverts % 3) {
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case RADEON_PRIM_TYPE_TRI_LIST:
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case RADEON_PRIM_TYPE_3VRT_POINT_LIST:
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case RADEON_PRIM_TYPE_3VRT_LINE_LIST:
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case RADEON_PRIM_TYPE_RECT_LIST:
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if (prim->numverts % 3 || prim->numverts == 0) {
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DRM_ERROR( "Bad nr verts for tri %d\n",
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prim->numverts);
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return;
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}
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break;
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case RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN:
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case RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_STRIP:
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case RADEON_PRIM_TYPE_TRI_FAN:
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case RADEON_PRIM_TYPE_TRI_STRIP:
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if (prim->numverts < 3) {
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DRM_ERROR( "Bad nr verts for strip/fan %d\n",
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prim->numverts);
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@ -791,39 +791,39 @@ static void radeon_cp_dispatch_indices( drm_device_t *dev,
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prim->numverts * 64);
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switch (prim->prim & RADEON_PRIM_TYPE_MASK) {
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case RADEON_CP_VC_CNTL_PRIM_TYPE_NONE:
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case RADEON_CP_VC_CNTL_PRIM_TYPE_POINT:
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case RADEON_PRIM_TYPE_NONE:
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case RADEON_PRIM_TYPE_POINT:
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if (count < 1) {
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DRM_ERROR( "Bad nr verts for line %d\n",
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count);
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return;
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}
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break;
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case RADEON_CP_VC_CNTL_PRIM_TYPE_LINE:
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if (count & 1) {
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case RADEON_PRIM_TYPE_LINE:
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if ((count & 1) || count == 0) {
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DRM_ERROR( "Bad nr verts for line %d\n",
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count);
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return;
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}
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break;
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case RADEON_CP_VC_CNTL_PRIM_TYPE_LINE_STRIP:
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case RADEON_PRIM_TYPE_LINE_STRIP:
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if (count < 2) {
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DRM_ERROR( "Bad nr verts for line_strip %d\n",
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count);
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return;
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}
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break;
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case RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST:
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case RADEON_CP_VC_CNTL_PRIM_TYPE_3VRT_POINT_LIST:
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case RADEON_CP_VC_CNTL_PRIM_TYPE_3VRT_LINE_LIST:
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case RADEON_CP_VC_CNTL_PRIM_TYPE_RECT_LIST:
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if (count % 3) {
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case RADEON_PRIM_TYPE_TRI_LIST:
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case RADEON_PRIM_TYPE_3VRT_POINT_LIST:
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case RADEON_PRIM_TYPE_3VRT_LINE_LIST:
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case RADEON_PRIM_TYPE_RECT_LIST:
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if (count % 3 || count == 0) {
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DRM_ERROR( "Bad nr verts for tri %d\n", count);
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return;
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}
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break;
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case RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN:
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case RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_STRIP:
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case RADEON_PRIM_TYPE_TRI_FAN:
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case RADEON_PRIM_TYPE_TRI_STRIP:
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if (count < 3) {
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DRM_ERROR( "Bad nr verts for strip/fan %d\n", count);
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return;
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@ -1199,33 +1199,36 @@ int radeon_cp_vertex( struct inode *inode, struct file *filp,
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return -EINVAL;
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}
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buf->used = vertex.count; /* not used? */
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if ( sarea_priv->dirty & ~RADEON_UPLOAD_CLIPRECTS ) {
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radeon_emit_state( dev_priv,
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&sarea_priv->context_state,
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sarea_priv->tex_state,
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sarea_priv->dirty );
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sarea_priv->dirty &= ~(RADEON_UPLOAD_TEX0IMAGES |
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RADEON_UPLOAD_TEX1IMAGES |
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RADEON_UPLOAD_TEX2IMAGES |
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RADEON_REQUIRE_QUIESCENCE);
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}
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/* Build up a prim_t record:
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*/
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prim.start = 0;
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prim.finish = vertex.count; /* unused */
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prim.prim = vertex.prim;
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prim.numverts = vertex.count;
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prim.vc_format = dev_priv->sarea_priv->vc_format;
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radeon_cp_dispatch_vertex( dev, buf, &prim,
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dev_priv->sarea_priv->boxes,
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dev_priv->sarea_priv->nbox );
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if (vertex.count) {
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buf->used = vertex.count; /* not used? */
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if ( sarea_priv->dirty & ~RADEON_UPLOAD_CLIPRECTS ) {
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radeon_emit_state( dev_priv,
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&sarea_priv->context_state,
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sarea_priv->tex_state,
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sarea_priv->dirty );
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sarea_priv->dirty &= ~(RADEON_UPLOAD_TEX0IMAGES |
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RADEON_UPLOAD_TEX1IMAGES |
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RADEON_UPLOAD_TEX2IMAGES |
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RADEON_REQUIRE_QUIESCENCE);
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}
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prim.start = 0;
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prim.finish = vertex.count; /* unused */
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prim.prim = vertex.prim;
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prim.numverts = vertex.count;
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prim.vc_format = dev_priv->sarea_priv->vc_format;
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radeon_cp_dispatch_vertex( dev, buf, &prim,
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dev_priv->sarea_priv->boxes,
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dev_priv->sarea_priv->nbox );
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}
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if (vertex.discard) {
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radeon_cp_discard_buffer( dev, buf );
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radeon_cp_discard_buffer( dev, buf );
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}
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return 0;
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@ -1317,16 +1320,16 @@ int radeon_cp_indices( struct inode *inode, struct file *filp,
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/* Build up a prim_t record:
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*/
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prim.start = elts.start;
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prim.finish = elts.end; /* unused */
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prim.finish = elts.end;
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prim.prim = elts.prim;
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prim.numverts = count;
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prim.numverts = 0; /* offset from start of dma buffers */
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prim.vc_format = dev_priv->sarea_priv->vc_format;
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radeon_cp_dispatch_indices( dev, buf, &prim,
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dev_priv->sarea_priv->boxes,
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dev_priv->sarea_priv->nbox );
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if (elts.discard) {
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radeon_cp_discard_buffer( dev, buf );
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radeon_cp_discard_buffer( dev, buf );
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}
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return 0;
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@ -1460,7 +1463,7 @@ int radeon_cp_indirect( struct inode *inode, struct file *filp,
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*/
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radeon_cp_dispatch_indirect( dev, buf, indirect.start, indirect.end );
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if (indirect.discard) {
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radeon_cp_discard_buffer( dev, buf );
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radeon_cp_discard_buffer( dev, buf );
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}
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