mirror of
https://gitlab.freedesktop.org/mesa/drm.git
synced 2026-05-07 20:28:04 +02:00
Checkpoint with lots of debug
This commit is contained in:
Keith Whitwell
parent
5d620c96be
commit
603e843d80
3 changed files with 29 additions and 13 deletions
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@ -117,7 +117,8 @@
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#define R200_EMIT_PP_TXOFFSET_4 46 /* tex4/1 */
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#define R200_EMIT_PP_TXOFFSET_5 47 /* tex5/1 */
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#define R200_EMIT_VTE_CNTL 48 /* vte/1 */
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#define RADEON_MAX_STATE_PACKETS 49
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#define R200_EMIT_OUTPUT_VTX_COMP_SEL 49 /* vtx/1 */
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#define RADEON_MAX_STATE_PACKETS 50
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/* Commands understood by cmd_buffer ioctl. More can be added but
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@ -299,6 +299,7 @@ extern int radeon_cp_flip( struct inode *inode, struct file *filp,
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# define RADEON_STENCIL_ENABLE (1 << 7)
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# define RADEON_Z_ENABLE (1 << 8)
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#define RADEON_RB3D_DEPTHOFFSET 0x1c24
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#define RADEON_RB3D_DEPTHPITCH 0x1c28
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#define RADEON_RB3D_PLANEMASK 0x1d84
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#define RADEON_RB3D_STENCILREFMASK 0x1d7c
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#define RADEON_RB3D_ZCACHE_MODE 0x3250
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@ -558,6 +559,7 @@ extern int radeon_cp_flip( struct inode *inode, struct file *filp,
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#define R200_PP_TXOFFSET_0 0x2d00
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#define R200_RE_AUX_SCISSOR_CNTL 0x26f0
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#define R200_SE_VTE_CNTL 0x20b0
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#define R200_SE_TCL_OUTPUT_VTX_COMP_SEL 0x2250
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#define SE_VAP_CNTL__TCL_ENA_MASK 0x00000001
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#define SE_VAP_CNTL__FORCE_W_TO_ONE_MASK 0x00010000
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@ -270,6 +270,7 @@ static struct {
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{ R200_PP_TXOFFSET_4, 1, "R200_PP_TXOFFSET_4" },
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{ R200_PP_TXOFFSET_5, 1, "R200_PP_TXOFFSET_5" },
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{ R200_SE_VTE_CNTL, 1, "R200_SE_VTE_CNTL" },
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{ R200_SE_TCL_OUTPUT_VTX_COMP_SEL, 1, "R200_SE_TCL_OUTPUT_VTX_COMP_SEL" },
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};
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@ -366,7 +367,8 @@ static void radeon_cp_dispatch_clear( drm_device_t *dev,
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if ( tmp & RADEON_BACK ) flags |= RADEON_FRONT;
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}
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if ( flags & (RADEON_FRONT | RADEON_BACK) ) {
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if ( 0 & flags & (RADEON_FRONT | RADEON_BACK) ) {
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BEGIN_RING( 4 );
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@ -442,7 +444,6 @@ static void radeon_cp_dispatch_clear( drm_device_t *dev,
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if ( dev_priv->is_r200 &&
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(flags & (RADEON_DEPTH | RADEON_STENCIL)) ) {
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#if 1
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int tempPP_CNTL;
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int tempRE_CNTL;
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int tempRB3D_CNTL;
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@ -471,7 +472,7 @@ static void radeon_cp_dispatch_clear( drm_device_t *dev,
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/* Disable TCL */
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tempSE_VAP_CNTL = (SE_VAP_CNTL__FORCE_W_TO_ONE_MASK |
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tempSE_VAP_CNTL = (/* SE_VAP_CNTL__FORCE_W_TO_ONE_MASK | */
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(0x9 << SE_VAP_CNTL__VF_MAX_VTX_NUM__SHIFT));
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tempRB3D_PLANEMASK = 0x0;
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@ -485,7 +486,7 @@ static void radeon_cp_dispatch_clear( drm_device_t *dev,
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/* Vertex format (X, Y, Z, W)*/
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tempSE_VTX_FMT_0 =
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(1 << SE_VTX_FMT_0__VTX_COLOR_0_FMT__SHIFT) |
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(1 << SE_VTX_FMT_0__VTX_COLOR_0_FMT__SHIFT) |
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SE_VTX_FMT_0__VTX_Z0_PRESENT_MASK |
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SE_VTX_FMT_0__VTX_W0_PRESENT_MASK;
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tempSE_VTX_FMT_1 = 0x0;
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@ -531,6 +532,8 @@ static void radeon_cp_dispatch_clear( drm_device_t *dev,
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OUT_RING_REG( R200_SE_VAP_CNTL, tempSE_VAP_CNTL );
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OUT_RING_REG( R200_RE_AUX_SCISSOR_CNTL,
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tempRE_AUX_SCISSOR_CNTL );
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/* OUT_RING_REG( RADEON_RB3D_DEPTHOFFSET, 0 ); */
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/* OUT_RING_REG( RADEON_RB3D_DEPTHPITCH, 0x740 ); */
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ADVANCE_RING();
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/* Make sure we restore the 3D state next time.
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@ -545,7 +548,6 @@ static void radeon_cp_dispatch_clear( drm_device_t *dev,
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radeon_emit_clip_rect( dev_priv,
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&sarea_priv->boxes[i] );
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#if 1
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BEGIN_RING( 17 );
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OUT_RING( CP_PACKET3( R200_3D_DRAW_IMMD_2, 15 ) );
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OUT_RING( (RADEON_PRIM_TYPE_RECT_LIST |
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@ -555,21 +557,19 @@ static void radeon_cp_dispatch_clear( drm_device_t *dev,
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OUT_RING( depth_boxes[i].ui[CLEAR_Y1] );
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OUT_RING( depth_boxes[i].ui[CLEAR_DEPTH] );
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OUT_RING( 0x3f800000 );
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OUT_RING( 0xFF33FF33 );
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OUT_RING( 0xFF33FF33 );
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OUT_RING( depth_boxes[i].ui[CLEAR_X1] );
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OUT_RING( depth_boxes[i].ui[CLEAR_Y2] );
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OUT_RING( depth_boxes[i].ui[CLEAR_DEPTH] );
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OUT_RING( 0x3f800000 );
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OUT_RING( 0xFF33FF33 );
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OUT_RING( 0xFF33FF33 );
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OUT_RING( depth_boxes[i].ui[CLEAR_X2] );
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OUT_RING( depth_boxes[i].ui[CLEAR_Y2] );
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OUT_RING( depth_boxes[i].ui[CLEAR_DEPTH] );
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OUT_RING( 0x3f800000 );
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OUT_RING( 0xFF33FF33 );
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OUT_RING( 0xFF33FF33 );
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ADVANCE_RING();
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#endif
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}
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#endif
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}
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else if ( (flags & (RADEON_DEPTH | RADEON_STENCIL)) ) {
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@ -1763,7 +1763,10 @@ static int radeon_emit_packets(
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int reg = packet[id].start;
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int *data = (int *)cmdbuf->buf;
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RING_LOCALS;
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printk("emit packet %s/%d\n", packet[id].name, sz );
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if (sz * sizeof(int) > cmdbuf->bufsz)
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return -EINVAL;
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@ -1934,6 +1937,8 @@ int radeon_cp_cmdbuf( struct inode *inode, struct file *filp,
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drm_radeon_cmd_buffer_t cmdbuf;
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drm_radeon_cmd_header_t header;
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printk( "%s\n", __FUNCTION__ );
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LOCK_TEST_WITH_RETURN( dev );
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if ( !dev_priv ) {
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@ -1947,7 +1952,7 @@ int radeon_cp_cmdbuf( struct inode *inode, struct file *filp,
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return -EFAULT;
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}
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DRM_DEBUG( __FUNCTION__": pid=%d\n", current->pid );
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printk( __FUNCTION__": pid=%d\n", current->pid );
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RING_SPACE_TEST_WITH_RETURN( dev_priv );
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VB_AGE_TEST_WITH_RETURN( dev_priv );
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@ -1972,6 +1977,7 @@ int radeon_cp_cmdbuf( struct inode *inode, struct file *filp,
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switch (header.header.cmd_type) {
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case RADEON_CMD_PACKET:
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printk("RADEON_CMD_PACKET\n");
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if (radeon_emit_packets( dev_priv, header, &cmdbuf )) {
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DRM_ERROR("radeon_emit_packets failed\n");
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return -EINVAL;
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@ -1979,6 +1985,7 @@ int radeon_cp_cmdbuf( struct inode *inode, struct file *filp,
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break;
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case RADEON_CMD_SCALARS:
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printk("RADEON_CMD_SCALARS\n");
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if (radeon_emit_scalars( dev_priv, header, &cmdbuf )) {
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DRM_ERROR("radeon_emit_scalars failed\n");
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return -EINVAL;
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@ -1986,6 +1993,7 @@ int radeon_cp_cmdbuf( struct inode *inode, struct file *filp,
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break;
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case RADEON_CMD_VECTORS:
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printk("RADEON_CMD_VECTORS\n");
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if (radeon_emit_vectors( dev_priv, header, &cmdbuf )) {
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DRM_ERROR("radeon_emit_vectors failed\n");
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return -EINVAL;
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@ -1993,6 +2001,7 @@ int radeon_cp_cmdbuf( struct inode *inode, struct file *filp,
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break;
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case RADEON_CMD_DMA_DISCARD:
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printk("RADEON_CMD_DMA_DISCARD\n");
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idx = header.dma.buf_idx;
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if ( idx < 0 || idx >= dma->buf_count ) {
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DRM_ERROR( "buffer index %d (of %d max)\n",
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@ -2010,6 +2019,7 @@ int radeon_cp_cmdbuf( struct inode *inode, struct file *filp,
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break;
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case RADEON_CMD_PACKET3:
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printk("RADEON_CMD_PACKET3\n");
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if (radeon_emit_packet3( dev, &cmdbuf )) {
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DRM_ERROR("radeon_emit_packet3 failed\n");
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return -EINVAL;
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@ -2017,6 +2027,7 @@ int radeon_cp_cmdbuf( struct inode *inode, struct file *filp,
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break;
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case RADEON_CMD_PACKET3_CLIP:
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printk("RADEON_CMD_PACKET3_CLIP\n");
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if (radeon_emit_packet3_cliprect( dev, &cmdbuf )) {
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DRM_ERROR("radeon_emit_packet3_clip failed\n");
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return -EINVAL;
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@ -2024,6 +2035,7 @@ int radeon_cp_cmdbuf( struct inode *inode, struct file *filp,
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break;
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case RADEON_CMD_SCALARS2:
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printk("RADEON_CMD_SCALARS2\n");
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if (radeon_emit_scalars2( dev_priv, header, &cmdbuf )) {
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DRM_ERROR("radeon_emit_scalars2 failed\n");
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return -EINVAL;
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@ -2038,6 +2050,7 @@ int radeon_cp_cmdbuf( struct inode *inode, struct file *filp,
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}
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printk("DONE\n");
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COMMIT_RING();
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return 0;
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}
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