From 561dded640c3452c498e95889c3b37d32d659a01 Mon Sep 17 00:00:00 2001
From: Doug Rabson <dfr@freebsd.org>
Date: Tue, 30 May 2000 10:44:02 +0000
Subject: [PATCH] Change to latest MGA kernel api.

---
 bsd-core/drmP.h | 41 ++++++++++++++++++++++++++++++++----
 bsd/drm.h       |  1 +
 bsd/drmP.h      | 41 ++++++++++++++++++++++++++++++++----
 bsd/mga_drm.h   | 56 ++++++++++++++++++++++++++++---------------------
 4 files changed, 107 insertions(+), 32 deletions(-)

diff --git a/bsd-core/drmP.h b/bsd-core/drmP.h
index c5951ff7..863836a6 100644
--- a/bsd-core/drmP.h
+++ b/bsd-core/drmP.h
@@ -77,9 +77,40 @@ test_and_set_bit(int b, volatile u_int32_t *p)
 	return r;
 }
 
-#define clear_bit(b, p)		atomic_clear_int(p, 1<<(b))
-#define set_bit(b, p)		atomic_set_int(p, 1<<(b))
-#define test_bit(b, p)		(*(u_int32_t*)p & (1<<(b)))
+static __inline void
+clear_bit(int b, volatile u_int32_t *p)
+{
+    atomic_clear_int(p + (b >> 5), 1 << (b & 0x1f));
+}
+
+static __inline void
+set_bit(int b, volatile u_int32_t *p)
+{
+    atomic_set_int(p + (b >> 5), 1 << (b & 0x1f));
+}
+
+static __inline int
+test_bit(int b, volatile u_int32_t *p)
+{
+    return p[b >> 5] & (1 << (b & 0x1f));
+}
+
+static __inline int
+find_first_zero_bit(volatile u_int32_t *p, int max)
+{
+    int b;
+
+    for (b = 0; b < max; b += 32) {
+	if (p[b >> 5]) {
+	    for (;;) {
+		if (p[b >> 5] & (1 << (b & 0x1f)))
+		    return b;
+		b++;
+	    }
+	}
+    }
+    return max;
+}
 
 #define spldrm()		spltty()
 
@@ -126,6 +157,8 @@ test_and_set_bit(int b, volatile u_int32_t *p)
 #define DRM_MEM_BOUNDAGP  17
 #define DRM_MEM_CTXBITMAP 18
 
+#define DRM_MAX_CTXBITMAP (PAGE_SIZE * 8)
+
 				/* Backward compatibility section */
 #ifndef _PAGE_PWT
 				/* The name of _PAGE_WT was changed to
@@ -496,7 +529,7 @@ typedef struct drm_device {
 #ifdef DRM_AGP
 	drm_agp_head_t    *agp;
 #endif
-	unsigned long     *ctx_bitmap;
+	u_int32_t	  *ctx_bitmap;
 	void		  *dev_private;
 } drm_device_t;
 
diff --git a/bsd/drm.h b/bsd/drm.h
index d2a0ab43..f61a70eb 100644
--- a/bsd/drm.h
+++ b/bsd/drm.h
@@ -336,6 +336,7 @@ typedef struct drm_agp_info {
 #define DRM_IOCTL_MGA_ILOAD   DRM_IOW( 0x43, drm_mga_iload_t)
 #define DRM_IOCTL_MGA_VERTEX  DRM_IOW( 0x44, drm_mga_vertex_t)
 #define DRM_IOCTL_MGA_FLUSH   DRM_IOW( 0x45, drm_lock_t )
+#define DRM_IOCTL_MGA_INDICES DRM_IOW( 0x46, drm_mga_indices_t)
 
 /* I810 specific ioctls */
 #define DRM_IOCTL_I810_INIT    DRM_IOW( 0x40, drm_i810_init_t)
diff --git a/bsd/drmP.h b/bsd/drmP.h
index c5951ff7..863836a6 100644
--- a/bsd/drmP.h
+++ b/bsd/drmP.h
@@ -77,9 +77,40 @@ test_and_set_bit(int b, volatile u_int32_t *p)
 	return r;
 }
 
-#define clear_bit(b, p)		atomic_clear_int(p, 1<<(b))
-#define set_bit(b, p)		atomic_set_int(p, 1<<(b))
-#define test_bit(b, p)		(*(u_int32_t*)p & (1<<(b)))
+static __inline void
+clear_bit(int b, volatile u_int32_t *p)
+{
+    atomic_clear_int(p + (b >> 5), 1 << (b & 0x1f));
+}
+
+static __inline void
+set_bit(int b, volatile u_int32_t *p)
+{
+    atomic_set_int(p + (b >> 5), 1 << (b & 0x1f));
+}
+
+static __inline int
+test_bit(int b, volatile u_int32_t *p)
+{
+    return p[b >> 5] & (1 << (b & 0x1f));
+}
+
+static __inline int
+find_first_zero_bit(volatile u_int32_t *p, int max)
+{
+    int b;
+
+    for (b = 0; b < max; b += 32) {
+	if (p[b >> 5]) {
+	    for (;;) {
+		if (p[b >> 5] & (1 << (b & 0x1f)))
+		    return b;
+		b++;
+	    }
+	}
+    }
+    return max;
+}
 
 #define spldrm()		spltty()
 
@@ -126,6 +157,8 @@ test_and_set_bit(int b, volatile u_int32_t *p)
 #define DRM_MEM_BOUNDAGP  17
 #define DRM_MEM_CTXBITMAP 18
 
+#define DRM_MAX_CTXBITMAP (PAGE_SIZE * 8)
+
 				/* Backward compatibility section */
 #ifndef _PAGE_PWT
 				/* The name of _PAGE_WT was changed to
@@ -496,7 +529,7 @@ typedef struct drm_device {
 #ifdef DRM_AGP
 	drm_agp_head_t    *agp;
 #endif
-	unsigned long     *ctx_bitmap;
+	u_int32_t	  *ctx_bitmap;
 	void		  *dev_private;
 } drm_device_t;
 
diff --git a/bsd/mga_drm.h b/bsd/mga_drm.h
index 12a858e7..8bfa2b97 100644
--- a/bsd/mga_drm.h
+++ b/bsd/mga_drm.h
@@ -1,4 +1,4 @@
-/* mga_drm.h -- Public header for the Matrox g200/g400 driver -*- linux-c -*-
+/* mga_drm.h -- Public header for the Matrox g200/g400 driver
  * Created: Tue Jan 25 01:50:01 1999 by jhartmann@precisioninsight.com
  *
  * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
@@ -37,6 +37,7 @@
  */
 #ifndef _MGA_DEFINES_
 #define _MGA_DEFINES_
+
 #define MGA_F  0x1		/* fog */
 #define MGA_A  0x2		/* alpha */
 #define MGA_S  0x4		/* specular */
@@ -61,11 +62,11 @@
 
 #define MGA_MAX_G400_PIPES 16
 #define MGA_MAX_G200_PIPES  8	/* no multitex */
-
 #define MGA_MAX_WARP_PIPES MGA_MAX_G400_PIPES
 
 #define MGA_CARD_TYPE_G200 1
 #define MGA_CARD_TYPE_G400 2
+
 #define MGA_FRONT   0x1
 #define MGA_BACK    0x2
 #define MGA_DEPTH   0x4
@@ -110,19 +111,19 @@
 #define MGA_UPLOAD_TEX0       0x2
 #define MGA_UPLOAD_TEX1       0x4
 #define MGA_UPLOAD_PIPE       0x8
-#define MGA_UPLOAD_TEX0IMAGE  0x10
-#define MGA_UPLOAD_TEX1IMAGE  0x20
+#define MGA_UPLOAD_TEX0IMAGE  0x10 /* handled client-side */
+#define MGA_UPLOAD_TEX1IMAGE  0x20 /* handled client-side */
 #define MGA_UPLOAD_2D 	      0x40
 #define MGA_WAIT_AGE          0x80 /* handled client-side */
 #define MGA_UPLOAD_CLIPRECTS  0x100 /* handled client-side */
 #define MGA_DMA_FLUSH	      0x200 /* set when someone gets the lock
                                        quiescent */
 
-/* 64 buffers of 16k each, total 1 meg.
+/* 32 buffers of 64k each, total 2 meg.
  */
-#define MGA_DMA_BUF_ORDER     14
+#define MGA_DMA_BUF_ORDER     16
 #define MGA_DMA_BUF_SZ        (1<<MGA_DMA_BUF_ORDER)
-#define MGA_DMA_BUF_NR        63
+#define MGA_DMA_BUF_NR        31
 
 /* Keep these small for testing.
  */
@@ -159,19 +160,19 @@ typedef struct drm_mga_init {
    	int sarea_priv_offset;
    	int primary_size;
    	int warp_ucode_size;
-   	int frontOffset;
-   	int backOffset;
-   	int depthOffset;
-   	int textureOffset;
-   	int textureSize;
-        int agpTextureOffset;
-        int agpTextureSize;
-   	int cpp;
-   	int stride;
+   	unsigned int frontOffset;
+   	unsigned int backOffset;
+   	unsigned int depthOffset;
+   	unsigned int textureOffset;
+   	unsigned int textureSize;
+        unsigned int agpTextureOffset;
+        unsigned int agpTextureSize;
+   	unsigned int cpp;
+   	unsigned int stride;
    	int sgram;
 	int chipset;
    	drm_mga_warp_index_t WarpIndex[MGA_MAX_WARP_PIPES];
-	int mAccess;
+	unsigned int mAccess;
 } drm_mga_init_t;
 
 /* Warning: if you change the sarea structure, you must change the Xserver
@@ -180,7 +181,7 @@ typedef struct drm_mga_init {
 typedef struct _drm_mga_tex_region {
 	unsigned char next, prev;	
 	unsigned char in_use;	
-	int age;			
+	unsigned int age;			
 } drm_mga_tex_region_t;
 
 typedef struct _drm_mga_sarea {
@@ -219,9 +220,9 @@ typedef struct _drm_mga_sarea {
    
 	/* Counters for aging textures and for client-side throttling.
 	 */
-        int last_enqueue;	/* last time a buffer was enqueued */
-	int last_dispatch;	/* age of the most recently dispatched buffer */
-	int last_quiescent;     /*  */
+        unsigned int last_enqueue;	/* last time a buffer was enqueued */
+	unsigned int last_dispatch;	/* age of the most recently dispatched buffer */
+	unsigned int last_quiescent;     /*  */
 
 
 	/* LRU lists for texture memory in agp space and on the card
@@ -237,9 +238,9 @@ typedef struct _drm_mga_sarea {
 /* Device specific ioctls:
  */
 typedef struct _drm_mga_clear {
-	int clear_color;
-	int clear_depth;
-	int flags;
+	unsigned int clear_color;
+	unsigned int clear_depth;
+	unsigned int flags;
 } drm_mga_clear_t;
 
 typedef struct _drm_mga_swap {
@@ -258,4 +259,11 @@ typedef struct _drm_mga_vertex {
 	int discard;		/* client finished with buffer?  */
 } drm_mga_vertex_t;
 
+typedef struct _drm_mga_indices {
+   	int idx;		/* buffer to queue */
+	unsigned int start;		
+	unsigned int end;		
+	int discard;		/* client finished with buffer?  */
+} drm_mga_indices_t;
+
 #endif