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RADEON: Initial DRM support for r6xx/r7xx hw

Browse source 
- Initial support written by Dave Airlie
- Bug fixes, gfx init, and r7xx support by me
This commit is contained in:
Alex Deucher 2008-12-29 15:35:37 -05:00
parent 58d557c73b
commit 52990ecb36
10 changed files with 11899 additions and 34 deletions
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2
linux-core/Makefile.kernel
View file

@ -29,7 +29,7 @@ nouveau-objs := nouveau_drv.o nouveau_state.o nouveau_fifo.o nouveau_mem.o \
nv04_graph.o nv10_graph.o nv20_graph.o \
nv40_graph.o nv50_graph.o \
nv04_instmem.o nv50_instmem.o
radeon-objs := radeon_drv.o radeon_cp.o radeon_state.o radeon_mem.o radeon_irq.o r300_cmdbuf.o
radeon-objs := radeon_drv.o radeon_cp.o radeon_state.o radeon_mem.o radeon_irq.o r300_cmdbuf.o r600_cp.o
sis-objs := sis_drv.o sis_mm.o
ffb-objs := ffb_drv.o ffb_context.o
savage-objs := savage_drv.o savage_bci.o savage_state.o

1
linux-core/r600_cp.c Symbolic link
View file

@ -0,0 +1 @@
../shared-core/r600_cp.c

1
linux-core/r600_microcode.h Symbolic link
View file

@ -0,0 +1 @@
../shared-core/r600_microcode.h

85
shared-core/drm_pciids.txt
View file

@ -239,6 +239,91 @@
0x1002 0x796d CHIP_RS740|RADEON_IS_IGP|RADEON_NEW_MEMMAP|RADEON_IS_IGPGART "ATI Radeon RS740 HD2100 IGP"
0x1002 0x796e CHIP_RS740|RADEON_IS_IGP|RADEON_NEW_MEMMAP|RADEON_IS_IGPGART "ATI Radeon RS740 HD2100 IGP"
0x1002 0x796f CHIP_RS740|RADEON_IS_IGP|RADEON_NEW_MEMMAP|RADEON_IS_IGPGART "ATI Radeon RS740 HD2100 IGP"
0x1002 0x9400 CHIP_R600|RADEON_NEW_MEMMAP "ATI Radeon HD 2900 XT"
0x1002 0x9401 CHIP_R600|RADEON_NEW_MEMMAP "ATI Radeon HD 2900 XT"
0x1002 0x9402 CHIP_R600|RADEON_NEW_MEMMAP "ATI Radeon HD 2900 XT"
0x1002 0x9403 CHIP_R600|RADEON_NEW_MEMMAP "ATI Radeon HD 2900 Pro"
0x1002 0x9405 CHIP_R600|RADEON_NEW_MEMMAP "ATI Radeon HD 2900 GT"
0x1002 0x940A CHIP_R600|RADEON_NEW_MEMMAP "ATI FireGL V8650"
0x1002 0x940B CHIP_R600|RADEON_NEW_MEMMAP "ATI FireGL V8600"
0x1002 0x940F CHIP_R600|RADEON_NEW_MEMMAP "ATI FireGL V7600"
0x1002 0x94C0 CHIP_RV610|RADEON_NEW_MEMMAP "RV610"
0x1002 0x94C1 CHIP_RV610|RADEON_NEW_MEMMAP "Radeon HD 2400 XT"
0x1002 0x94C3 CHIP_RV610|RADEON_NEW_MEMMAP "Radeon HD 2400 Pro"
0x1002 0x94C4 CHIP_RV610|RADEON_NEW_MEMMAP "Radeon HD 2400 PRO AGP"
0x1002 0x94C5 CHIP_RV610|RADEON_NEW_MEMMAP "FireGL V4000"
0x1002 0x94C6 CHIP_RV610|RADEON_NEW_MEMMAP "RV610"
0x1002 0x94C7 CHIP_RV610|RADEON_NEW_MEMMAP "ATI Radeon HD 2350"
0x1002 0x94C8 CHIP_RV610|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP "ATI Mobility Radeon HD 2400 XT"
0x1002 0x94C9 CHIP_RV610|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP "ATI Mobility Radeon HD 2400"
0x1002 0x94CB CHIP_RV610|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP "ATI RADEON E2400"
0x1002 0x94CC CHIP_RV610|RADEON_NEW_MEMMAP "ATI RV610"
0x1002 0x9500 CHIP_RV670|RADEON_NEW_MEMMAP "ATI RV670"
0x1002 0x9501 CHIP_RV670|RADEON_NEW_MEMMAP "ATI Radeon HD3870"
0x1002 0x9505 CHIP_RV670|RADEON_NEW_MEMMAP "ATI Radeon HD3850"
0x1002 0x9507 CHIP_RV670|RADEON_NEW_MEMMAP "ATI RV670"
0x1002 0x950F CHIP_RV670|RADEON_NEW_MEMMAP "ATI Radeon HD3870 X2"
0x1002 0x9511 CHIP_RV670|RADEON_NEW_MEMMAP "ATI FireGL V7700"
0x1002 0x9581 CHIP_RV630|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP "ATI Mobility Radeon HD 2600"
0x1002 0x9583 CHIP_RV630|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP "ATI Mobility Radeon HD 2600 XT"
0x1002 0x9586 CHIP_RV630|RADEON_NEW_MEMMAP "ATI Radeon HD 2600 XT AGP"
0x1002 0x9587 CHIP_RV630|RADEON_NEW_MEMMAP "ATI Radeon HD 2600 Pro AGP"
0x1002 0x9588 CHIP_RV630|RADEON_NEW_MEMMAP "ATI Radeon HD 2600 XT"
0x1002 0x9589 CHIP_RV630|RADEON_NEW_MEMMAP "ATI Radeon HD 2600 Pro"
0x1002 0x958A CHIP_RV630|RADEON_NEW_MEMMAP "ATI Gemini RV630"
0x1002 0x958B CHIP_RV630|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP "ATI Gemini Mobility Radeon HD 2600 XT"
0x1002 0x958C CHIP_RV630|RADEON_NEW_MEMMAP "ATI FireGL V5600"
0x1002 0x958D CHIP_RV630|RADEON_NEW_MEMMAP "ATI FireGL V3600"
0x1002 0x958E CHIP_RV630|RADEON_NEW_MEMMAP "ATI Radeon HD 2600 LE"
0x1002 0x95C0 CHIP_RV620|RADEON_NEW_MEMMAP "ATI Radeon HD 3470"
0x1002 0x95C5 CHIP_RV620|RADEON_NEW_MEMMAP "ATI Radeon HD 3450"
0x1002 0x95C7 CHIP_RV620|RADEON_NEW_MEMMAP "ATI Radeon HD 3430"
0x1002 0x95C2 CHIP_RV620|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP "ATI Mobility Radeon HD 3430"
0x1002 0x95C4 CHIP_RV620|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP "ATI Mobility Radeon HD 3400 Series"
0x1002 0x95CD CHIP_RV620|RADEON_NEW_MEMMAP "ATI FireMV 2450"
0x1002 0x95CE CHIP_RV620|RADEON_NEW_MEMMAP "ATI FireMV 2260"
0x1002 0x95CF CHIP_RV620|RADEON_NEW_MEMMAP "ATI FireMV 2260"
0x1002 0x9590 CHIP_RV635|RADEON_NEW_MEMMAP "ATI ATI Radeon HD 3600 Series"
0x1002 0x9596 CHIP_RV635|RADEON_NEW_MEMMAP "ATI ATI Radeon HD 3650 AGP"
0x1002 0x9597 CHIP_RV635|RADEON_NEW_MEMMAP "ATI ATI Radeon HD 3600 PRO"
0x1002 0x9598 CHIP_RV635|RADEON_NEW_MEMMAP "ATI ATI Radeon HD 3600 XT"
0x1002 0x9599 CHIP_RV635|RADEON_NEW_MEMMAP "ATI ATI Radeon HD 3600 PRO"
0x1002 0x9591 CHIP_RV635|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP "ATI Mobility Radeon HD 3650"
0x1002 0x9593 CHIP_RV635|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP "ATI Mobility Radeon HD 3670"
0x1002 0x9610 CHIP_RS780|RADEON_NEW_MEMMAP|RADEON_IS_IGP "ATI Radeon HD 3200 Graphics"
0x1002 0x9611 CHIP_RS780|RADEON_NEW_MEMMAP|RADEON_IS_IGP "ATI Radeon 3100 Graphics"
0x1002 0x9612 CHIP_RS780|RADEON_NEW_MEMMAP|RADEON_IS_IGP "ATI Radeon HD 3200 Graphics"
0x1002 0x9613 CHIP_RS780|RADEON_NEW_MEMMAP|RADEON_IS_IGP "ATI Radeon 3100 Graphics"
0x1002 0x9440 CHIP_RV770|RADEON_NEW_MEMMAP "ATI Radeon 4800 Series"
0x1002 0x9441 CHIP_RV770|RADEON_NEW_MEMMAP "ATI Radeon 4870 X2"
0x1002 0x9442 CHIP_RV770|RADEON_NEW_MEMMAP "ATI Radeon 4800 Series"
0x1002 0x944C CHIP_RV770|RADEON_NEW_MEMMAP "ATI Radeon 4800 Series"
0x1002 0x9450 CHIP_RV770|RADEON_NEW_MEMMAP "AMD FireStream 9270"
0x1002 0x9452 CHIP_RV770|RADEON_NEW_MEMMAP "AMD FireStream 9250"
0x1002 0x9444 CHIP_RV770|RADEON_NEW_MEMMAP "ATI FirePro V8750 (FireGL)"
0x1002 0x9446 CHIP_RV770|RADEON_NEW_MEMMAP "ATI FirePro V7760 (FireGL)"
0x1002 0x9456 CHIP_RV770|RADEON_NEW_MEMMAP "ATI FirePro V8700 (FireGL)"
0x1002 0x944E CHIP_RV770|RADEON_NEW_MEMMAP "ATI FirePro RV770"
0x1002 0x944A CHIP_RV770|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP "ATI Mobility Radeon HD 4850"
0x1002 0x944B CHIP_RV770|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP "ATI Mobility Radeon HD 4850 X2"
0x1002 0x945A CHIP_RV770|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP "ATI Mobility Radeon HD 4870"
0x1002 0x945B CHIP_RV770|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP "ATI Mobility Radeon M98"
0x1002 0x9487 CHIP_RV730|RADEON_NEW_MEMMAP "ATI Radeon RV730 (AGP)"
0x1002 0x948F CHIP_RV730|RADEON_NEW_MEMMAP "ATI Radeon RV730 (AGP)"
0x1002 0x9490 CHIP_RV730|RADEON_NEW_MEMMAP "ATI Radeon HD 4670"
0x1002 0x9498 CHIP_RV730|RADEON_NEW_MEMMAP "ATI Radeon HD 4650"
0x1002 0x9480 CHIP_RV730|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP "ATI Mobility Radeon HD 4650"
0x1002 0x9488 CHIP_RV730|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP "ATI Mobility Radeon HD 4670"
0x1002 0x949c CHIP_RV730|RADEON_NEW_MEMMAP "ATI FirePro V7750 (FireGL)"
0x1002 0x949e CHIP_RV730|RADEON_NEW_MEMMAP "ATI FirePro V5700 (FireGL)"
0x1002 0x949f CHIP_RV730|RADEON_NEW_MEMMAP "ATI FirePro V3750 (FireGL)"
0x1002 0x9540 CHIP_RV710|RADEON_NEW_MEMMAP "ATI Radeon HD 4550"
0x1002 0x9541 CHIP_RV710|RADEON_NEW_MEMMAP "ATI Radeon RV710"
0x1002 0x9592 CHIP_RV710|RADEON_NEW_MEMMAP "ATI Radeon RV710"
0x1002 0x954E CHIP_RV710|RADEON_NEW_MEMMAP "ATI Radeon RV710"
0x1002 0x954F CHIP_RV710|RADEON_NEW_MEMMAP "ATI Radeon HD 4350"
0x1002 0x9552 CHIP_RV710|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP "ATI Mobility Radeon 4300 Series"
0x1002 0x9553 CHIP_RV710|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP "ATI Mobility Radeon 4500 Series"
[r128]
0x1002 0x4c45 0 "ATI Rage 128 Mobility LE (PCI)"

2516
shared-core/r600_cp.c Normal file
View file

File diff suppressed because it is too large Load diff

9025
shared-core/r600_microcode.h
View file

File diff suppressed because it is too large Load diff

95
shared-core/radeon_cp.c
View file

@ -41,6 +41,20 @@
static int radeon_do_cleanup_cp(struct drm_device * dev);
static void radeon_do_cp_start(drm_radeon_private_t * dev_priv);
u32 RADEON_READ_MM(drm_radeon_private_t *dev_priv, int addr)
{
u32 ret;
if (addr < 0x10000)
ret = DRM_READ32( dev_priv->mmio, addr );
else {
DRM_WRITE32( dev_priv->mmio, RADEON_MM_INDEX, addr );
ret = DRM_READ32( dev_priv->mmio, RADEON_MM_DATA );
}
return ret;
}
static u32 R500_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
{
u32 ret;
@ -79,8 +93,11 @@ static u32 IGP_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv)
{
if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
return RADEON_READ(R700_MC_VM_FB_LOCATION);
else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
return RADEON_READ(R600_MC_VM_FB_LOCATION);
else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
return R500_READ_MCIND(dev_priv, RV515_MC_FB_LOCATION);
else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
@ -91,9 +108,13 @@ u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv)
return RADEON_READ(RADEON_MC_FB_LOCATION);
}
static void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc)
void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc)
{
if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
RADEON_WRITE(R700_MC_VM_FB_LOCATION, fb_loc);
else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
RADEON_WRITE(R600_MC_VM_FB_LOCATION, fb_loc);
else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
R500_WRITE_MCIND(RV515_MC_FB_LOCATION, fb_loc);
else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
@ -104,9 +125,15 @@ static void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc)
RADEON_WRITE(RADEON_MC_FB_LOCATION, fb_loc);
}
static void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc)
void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc)
{
if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) {
RADEON_WRITE(R700_MC_VM_AGP_BOT, agp_loc); /* FIX ME */
RADEON_WRITE(R700_MC_VM_AGP_TOP, 0);
} else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
RADEON_WRITE(R600_MC_VM_AGP_BOT, agp_loc); /* FIX ME */
RADEON_WRITE(R600_MC_VM_AGP_TOP, 0);
} else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
R500_WRITE_MCIND(RV515_MC_AGP_LOCATION, agp_loc);
else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
@ -122,7 +149,11 @@ static void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base)
u32 agp_base_hi = upper_32_bits(agp_base);
u32 agp_base_lo = agp_base & 0xffffffff;
if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) {
if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
RADEON_WRITE(R700_MC_VM_AGP_BASE, 0); /* FIX ME */
else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
RADEON_WRITE(R600_MC_VM_AGP_BASE, 0); /* FIX ME */
else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) {
R500_WRITE_MCIND(RV515_MC_AGP_BASE, agp_base_lo);
R500_WRITE_MCIND(RV515_MC_AGP_BASE_2, agp_base_hi);
} else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
@ -316,6 +347,7 @@ static void radeon_init_pipes(drm_radeon_private_t * dev_priv)
* CP control, initialization
*/
/* Load the microcode for the CP */
static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv)
{
@ -394,9 +426,12 @@ static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv)
RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
R520_cp_microcode[i][0]);
}
}
}
}
/* Flush any pending commands to the CP. This should only be used just
* prior to a wait for idle, as it informs the engine that the command
* stream is ending.
@ -419,6 +454,10 @@ int radeon_do_cp_idle(drm_radeon_private_t * dev_priv)
RING_LOCALS;
DRM_DEBUG("\n");
/* XXX fixme */
if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
return 0;
BEGIN_RING(6);
RADEON_PURGE_CACHE();
@ -1321,6 +1360,8 @@ int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_pri
case RADEON_INIT_R200_CP:
case RADEON_INIT_R300_CP:
return radeon_do_init_cp(dev, init);
case RADEON_INIT_R600_CP:
return r600_do_init_cp(dev, init);
case RADEON_CLEANUP_CP:
return radeon_do_cleanup_cp(dev);
}
@ -1345,7 +1386,10 @@ int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_pr
return 0;
}
radeon_do_cp_start(dev_priv);
if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
r600_do_cp_start(dev_priv);
else
radeon_do_cp_start(dev_priv);
return 0;
}
@ -1385,10 +1429,15 @@ int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_pri
* we will get some dropped triangles as they won't be fully
* rendered before the CP is shut down.
*/
radeon_do_cp_stop(dev_priv);
if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
r600_do_cp_stop(dev_priv);
else
radeon_do_cp_stop(dev_priv);
/* Reset the engine */
radeon_do_engine_reset(dev);
/* XXX: fix me for r6xx */
if ((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_R600)
radeon_do_engine_reset(dev);
return 0;
}
@ -1477,6 +1526,10 @@ int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_pri
*/
int radeon_cp_resume(struct drm_device *dev, void *data, struct drm_file *file_priv)
{
drm_radeon_private_t *dev_priv = dev->dev_private;
if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
return r600_do_resume_cp(dev);
return radeon_do_resume_cp(dev);
}
@ -1537,7 +1590,11 @@ struct drm_buf *radeon_freelist_get(struct drm_device * dev)
start = dev_priv->last_buf;
for (t = 0; t < dev_priv->usec_timeout; t++) {
u32 done_age = GET_SCRATCH(1);
u32 done_age;
if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
done_age = GET_R600_SCRATCH(1);
else
done_age = GET_SCRATCH(1);
DRM_DEBUG("done_age = %d\n", done_age);
for (i = start; i < dma->buf_count; i++) {
buf = dma->buflist[i];
@ -1620,10 +1677,20 @@ int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n)
{
drm_radeon_ring_buffer_t *ring = &dev_priv->ring;
int i;
u32 last_head = GET_RING_HEAD(dev_priv);
u32 last_head;
if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
last_head = R600_GET_RING_HEAD(dev_priv);
else
last_head = GET_RING_HEAD(dev_priv);
for (i = 0; i < dev_priv->usec_timeout; i++) {
u32 head = GET_RING_HEAD(dev_priv);
u32 head;
if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
head = R600_GET_RING_HEAD(dev_priv);
else
head = GET_RING_HEAD(dev_priv);
ring->space = (head - ring->tail) * sizeof(u32);
if (ring->space <= 0)

7
shared-core/radeon_drm.h
View file

@ -303,6 +303,7 @@ typedef union {
#define RADEON_INDEX_PRIM_OFFSET 20
#define RADEON_SCRATCH_REG_OFFSET 32
#define R600_SCRATCH_REG_OFFSET 256
#define RADEON_NR_SAREA_CLIPRECTS 12
@ -526,7 +527,8 @@ typedef struct drm_radeon_init {
RADEON_INIT_CP = 0x01,
RADEON_CLEANUP_CP = 0x02,
RADEON_INIT_R200_CP = 0x03,
RADEON_INIT_R300_CP = 0x04
RADEON_INIT_R300_CP = 0x04,
RADEON_INIT_R600_CP = 0x05,
} func;
unsigned long sarea_priv_offset;
int is_pci; /* for overriding only */
@ -652,6 +654,9 @@ typedef struct drm_radeon_indirect {
int discard;
} drm_radeon_indirect_t;
#define RADEON_INDIRECT_DISCARD (1 << 0)
#define RADEON_INDIRECT_NOFLUSH (1 << 1)
/* enum for card type parameters */
#define RADEON_CARD_PCI 0
#define RADEON_CARD_AGP 1

177
shared-core/radeon_drv.h
View file

@ -135,6 +135,16 @@ enum radeon_family {
CHIP_RV560,
CHIP_RV570,
CHIP_R580,
CHIP_R600,
CHIP_RV610,
CHIP_RV630,
CHIP_RV620,
CHIP_RV635,
CHIP_RV670,
CHIP_RS780,
CHIP_RV770,
CHIP_RV730,
CHIP_RV710,
CHIP_LAST,
};
@ -159,6 +169,9 @@ enum radeon_chip_flags {
DRM_READ32( (dev_priv)->ring_rptr, 0 ) : RADEON_READ(RADEON_CP_RB_RPTR))
#define SET_RING_HEAD(dev_priv,val) DRM_WRITE32( (dev_priv)->ring_rptr, 0, (val) )
#define R600_GET_RING_HEAD(dev_priv) (dev_priv->writeback_works ? \
DRM_READ32( (dev_priv)->ring_rptr, 0 ) : RADEON_READ(R600_CP_RB_RPTR))
typedef struct drm_radeon_freelist {
unsigned int age;
struct drm_buf *buf;
@ -316,6 +329,26 @@ typedef struct drm_radeon_private {
int num_gb_pipes;
int track_flush;
uint32_t chip_family; /* extract from flags */
/* r6xx/r7xx pipe/shader config */
int r600_max_pipes;
int r600_max_tile_pipes;
int r600_max_simds;
int r600_max_backends;
int r600_max_gprs;
int r600_max_threads;
int r600_max_stack_entries;
int r600_max_hw_contexts;
int r600_max_gs_threads;
int r600_sx_max_export_size;
int r600_sx_max_export_pos_size;
int r600_sx_max_export_smx_size;
int r600_sq_num_cf_insts;
int r700_sx_num_of_sets;
int r700_sc_prim_fifo_size;
int r700_sc_hiz_tile_fifo_size;
int r700_sc_earlyz_tile_fifo_fize;
} drm_radeon_private_t;
typedef struct drm_radeon_buf_priv {
@ -359,6 +392,7 @@ extern int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_fi
extern int radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv);
extern int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv);
extern u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv);
extern u32 RADEON_READ_MM(drm_radeon_private_t *dev_priv, int addr);
extern void radeon_freelist_reset(struct drm_device * dev);
extern struct drm_buf *radeon_freelist_get(struct drm_device * dev);
@ -403,6 +437,8 @@ extern int radeon_driver_open(struct drm_device * dev,
extern long radeon_compat_ioctl(struct file *filp, unsigned int cmd,
unsigned long arg);
void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc);
void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc);
/* r300_cmdbuf.c */
extern void r300_init_reg_flags(struct drm_device *dev);
@ -410,6 +446,12 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
struct drm_file *file_priv,
drm_radeon_kcmd_buffer_t *cmdbuf);
/* r600 cp */
int r600_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init);
int r600_do_resume_cp(struct drm_device * dev);
void r600_do_cp_start(drm_radeon_private_t * dev_priv);
int r600_cp_indirect(struct drm_device *dev, struct drm_buf *buf, drm_radeon_indirect_t *indirect);
void r600_do_cp_stop(drm_radeon_private_t * dev_priv);
/* Flags for stats.boxes
*/
#define RADEON_BOX_DMA_IDLE 0x1
@ -421,6 +463,9 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
/* Register definitions, register access macros and drmAddMap constants
* for Radeon kernel driver.
*/
#define RADEON_MM_INDEX 0x0000
#define RADEON_MM_DATA 0x0004
#define RADEON_AGP_COMMAND 0x0f60
#define RADEON_AGP_COMMAND_PCI_CONFIG 0x0060 /* offset in PCI config */
# define RADEON_AGP_ENABLE (1<<8)
@ -623,12 +668,29 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
#define RADEON_SCRATCH_UMSK 0x0770
#define RADEON_SCRATCH_ADDR 0x0774
#define R600_SCRATCH_REG0 0x8500
#define R600_SCRATCH_REG1 0x8504
#define R600_SCRATCH_REG2 0x8508
#define R600_SCRATCH_REG3 0x850c
#define R600_SCRATCH_REG4 0x8510
#define R600_SCRATCH_REG5 0x8514
#define R600_SCRATCH_REG6 0x8518
#define R600_SCRATCH_REG7 0x851c
#define R600_SCRATCH_UMSK 0x8540
#define R600_SCRATCH_ADDR 0x8544
#define RADEON_SCRATCHOFF( x ) (RADEON_SCRATCH_REG_OFFSET + 4*(x))
#define R600_SCRATCHOFF( x ) (R600_SCRATCH_REG_OFFSET + 4*(x))
#define GET_SCRATCH( x ) (dev_priv->writeback_works \
? DRM_READ32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(x) ) \
: RADEON_READ( RADEON_SCRATCH_REG0 + 4*(x) ) )
#define GET_R600_SCRATCH( x ) (dev_priv->writeback_works \
? DRM_READ32( dev_priv->ring_rptr, R600_SCRATCHOFF(x) ) \
: RADEON_READ( R600_SCRATCH_REG0 + 4*(x) ) )
#define RADEON_CRTC_CRNT_FRAME 0x0214
#define RADEON_CRTC2_CRNT_FRAME 0x0314
@ -893,6 +955,7 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
#define RADEON_SW_SEMAPHORE 0x013c
#define RADEON_WAIT_UNTIL 0x1720
#define R600_WAIT_UNTIL 0x8040
# define RADEON_WAIT_CRTC_PFLIP (1 << 0)
# define RADEON_WAIT_2D_IDLE (1 << 14)
# define RADEON_WAIT_3D_IDLE (1 << 15)
@ -915,6 +978,7 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
#define RADEON_CP_RB_CNTL 0x0704
# define RADEON_BUF_SWAP_32BIT (2 << 16)
# define RADEON_RB_NO_UPDATE (1 << 27)
# define RADEON_RB_RPTR_WR_ENA (1 << 31)
#define RADEON_CP_RB_RPTR_ADDR 0x070c
#define RADEON_CP_RB_RPTR 0x0710
#define RADEON_CP_RB_WPTR 0x0714
@ -976,6 +1040,10 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
# define RADEON_CNTL_BITBLT_MULTI 0x00009B00
# define RADEON_CNTL_SET_SCISSORS 0xC0001E00
# define R600_IT_INDIRECT_BUFFER 0x00003200
# define R600_IT_ME_INITIALIZE 0x00004400
# define R600_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16)
#define RADEON_CP_PACKET_MASK 0xC0000000
#define RADEON_CP_PACKET_COUNT_MASK 0x3fff0000
#define RADEON_CP_PACKET0_REG_MASK 0x000007ff
@ -1199,6 +1267,47 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
#define R500_D1_VBLANK_INTERRUPT (1 << 4)
#define R500_D2_VBLANK_INTERRUPT (1 << 5)
#define R600_BUS_CNTL 0x5420
#define R600_BUS_MASTER_DIS (1 << 4)
#define R600_MC_VM_FB_LOCATION 0x2180
#define R600_MC_VM_AGP_TOP 0x2184
#define R600_MC_VM_AGP_BOT 0x2188
#define R600_MC_VM_AGP_BASE 0x218c
#define R600_MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2190
#define R600_MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2194
#define R600_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x2198
#define R700_MC_VM_FB_LOCATION 0x2024
#define R700_MC_VM_AGP_TOP 0x2028
#define R700_MC_VM_AGP_BOT 0x202c
#define R700_MC_VM_AGP_BASE 0x2030
#define R700_MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034
#define R700_MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038
#define R700_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203c
#define R600_CP_RB_BASE 0xc100
#define R600_CP_RB_CNTL 0xc104
# define R600_RB_NO_UPDATE (1 << 27)
# define R600_RB_RPTR_WR_ENA (1 << 31)
#define R600_CP_RB_RPTR_WR 0xc108
#define R600_CP_RB_RPTR_ADDR 0xc10c
#define R600_CP_RB_RPTR_ADDR_HI 0xc110
#define R600_CP_RB_WPTR 0xc114
#define R600_CP_RB_WPTR_ADDR 0xc118
#define R600_CP_RB_WPTR_ADDR_HI 0xc11c
#define R600_CP_RB_RPTR 0x8700
#define R600_CP_RB_WPTR_DELAY 0x8704
#define R600_CP_PFP_UCODE_ADDR 0xc150
#define R600_CP_PFP_UCODE_DATA 0xc154
#define R600_CP_ME_RAM_RADDR 0xc158
#define R600_CP_ME_RAM_WADDR 0xc15c
#define R600_CP_ME_RAM_DATA 0xc160
/* Constants */
#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
@ -1208,6 +1317,12 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
#define RADEON_LAST_SWI_REG RADEON_SCRATCH_REG3
#define RADEON_LAST_DISPATCH 1
#define R600_LAST_FRAME_REG R600_SCRATCH_REG0
#define R600_LAST_DISPATCH_REG R600_SCRATCH_REG1
#define R600_LAST_CLEAR_REG R600_SCRATCH_REG2
#define R600_LAST_SWI_REG R600_SCRATCH_REG3
#define RADEON_MAX_VB_AGE 0x7fffffff
#define RADEON_MAX_VB_VERTS (0xffff)
@ -1215,8 +1330,16 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
#define RADEON_PCIGART_TABLE_SIZE (32*1024)
#define RADEON_READ(reg) DRM_READ32( dev_priv->mmio, (reg) )
#define RADEON_WRITE(reg,val) DRM_WRITE32( dev_priv->mmio, (reg), (val) )
#define RADEON_READ(reg) RADEON_READ_MM(dev_priv, reg)
#define RADEON_WRITE(reg,val) \
do { \
if (reg < 0x10000) { \
DRM_WRITE32( dev_priv->mmio, (reg), (val) ); \
} else { \
DRM_WRITE32( dev_priv->mmio, RADEON_MM_INDEX, (reg) ); \
DRM_WRITE32( dev_priv->mmio, RADEON_MM_DATA, (val) ); \
} \
} while (0)
#define RADEON_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) )
#define RADEON_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, (reg), (val) )
@ -1281,26 +1404,38 @@ do { \
*/
#define RADEON_WAIT_UNTIL_2D_IDLE() do { \
OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) \
OUT_RING( CP_PACKET0( R600_WAIT_UNTIL, 0 ) ); \
else \
OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \
RADEON_WAIT_HOST_IDLECLEAN) ); \
} while (0)
#define RADEON_WAIT_UNTIL_3D_IDLE() do { \
OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) \
OUT_RING( CP_PACKET0( R600_WAIT_UNTIL, 0 ) ); \
else \
OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
OUT_RING( (RADEON_WAIT_3D_IDLECLEAN | \
RADEON_WAIT_HOST_IDLECLEAN) ); \
} while (0)
#define RADEON_WAIT_UNTIL_IDLE() do { \
OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) \
OUT_RING( CP_PACKET0( R600_WAIT_UNTIL, 0 ) ); \
else \
OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \
RADEON_WAIT_3D_IDLECLEAN | \
RADEON_WAIT_HOST_IDLECLEAN) ); \
} while (0)
#define RADEON_WAIT_UNTIL_PAGE_FLIPPED() do { \
OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) \
OUT_RING( CP_PACKET0( R600_WAIT_UNTIL, 0 ) ); \
else \
OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
OUT_RING( RADEON_WAIT_CRTC_PFLIP ); \
} while (0)
@ -1375,6 +1510,13 @@ do { \
OUT_RING( age ); \
} while (0)
#define R600_DISPATCH_AGE( age ) do { \
OUT_RING( CP_PACKET0( R600_LAST_DISPATCH_REG, 0 ) ); \
OUT_RING( age ); \
} while (0)
#define RADEON_FRAME_AGE( age ) do { \
OUT_RING( CP_PACKET0( RADEON_LAST_FRAME_REG, 0 ) ); \
OUT_RING( age ); \
@ -1421,13 +1563,28 @@ do { \
dev_priv->ring.tail = write; \
} while (0)
#define COMMIT_RING() do { \
#define R600_COMMIT_RING() do { \
DRM_MEMORYBARRIER(); \
R600_GET_RING_HEAD( dev_priv ); \
RADEON_WRITE( R600_CP_RB_WPTR, dev_priv->ring.tail ); \
RADEON_READ( R600_CP_RB_RPTR); \
} while (0)
#define RADEON_COMMIT_RING() do { \
/* Flush writes to ring */ \
DRM_MEMORYBARRIER(); \
GET_RING_HEAD( dev_priv ); \
RADEON_WRITE( RADEON_CP_RB_WPTR, dev_priv->ring.tail ); \
/* read from PCI bus to ensure correct posting */ \
RADEON_READ( RADEON_CP_RB_RPTR ); \
RADEON_WRITE( RADEON_CP_RB_WPTR, dev_priv->ring.tail ); \
/* read from PCI bus to ensure correct posting */ \
RADEON_READ( RADEON_CP_RB_RPTR ); \
} while (0)
#define COMMIT_RING() do { \
if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) { \
R600_COMMIT_RING(); \
} else { \
RADEON_COMMIT_RING(); \
} \
} while (0)
#define OUT_RING( x ) do { \

24
shared-core/radeon_state.c
View file

@ -2482,6 +2482,10 @@ static int radeon_cp_indirect(struct drm_device *dev, void *data, struct drm_fil
return -EINVAL;
}
if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
return r600_cp_indirect(dev, buf, indirect);
}
RING_SPACE_TEST_WITH_RETURN(dev_priv);
VB_AGE_TEST_WITH_RETURN(dev_priv);
@ -3038,14 +3042,23 @@ static int radeon_cp_getparam(struct drm_device *dev, void *data, struct drm_fil
break;
case RADEON_PARAM_LAST_FRAME:
dev_priv->stats.last_frame_reads++;
value = GET_SCRATCH(0);
if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
value = GET_R600_SCRATCH(0);
else
value = GET_SCRATCH(0);
break;
case RADEON_PARAM_LAST_DISPATCH:
value = GET_SCRATCH(1);
if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
value = GET_R600_SCRATCH(1);
else
value = GET_SCRATCH(1);
break;
case RADEON_PARAM_LAST_CLEAR:
dev_priv->stats.last_clear_reads++;
value = GET_SCRATCH(2);
if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
value = GET_R600_SCRATCH(2);
else
value = GET_SCRATCH(2);
break;
case RADEON_PARAM_IRQ_NR:
value = dev->irq;
@ -3080,7 +3093,10 @@ static int radeon_cp_getparam(struct drm_device *dev, void *data, struct drm_fil
case RADEON_PARAM_SCRATCH_OFFSET:
if (!dev_priv->writeback_works)
return -EINVAL;
value = RADEON_SCRATCH_REG_OFFSET;
if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
value = R600_SCRATCH_REG_OFFSET;
else
value = RADEON_SCRATCH_REG_OFFSET;
break;
case RADEON_PARAM_CARD_TYPE: