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https://gitlab.freedesktop.org/mesa/drm.git
synced 2025-12-20 05:50:12 +01:00
xf86drm: print AMD modifiers properly
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
This commit is contained in:
Marek Olšák
parent
c0a08f06ae
commit
50da61eebd
1 changed files with 127 additions and 138 deletions
281
xf86drm.c
281
xf86drm.c
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@ -201,18 +201,6 @@ static const struct drmFormatVendorModifierInfo arm_mode_value_table[] = {
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{ AFBC_FORMAT_MOD_USM, "USM" },
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};
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static bool is_x_t_amd_gfx9_tile(uint64_t tile)
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{
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switch (tile) {
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case AMD_FMT_MOD_TILE_GFX9_64K_S_X:
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case AMD_FMT_MOD_TILE_GFX9_64K_D_X:
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case AMD_FMT_MOD_TILE_GFX9_64K_R_X:
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return true;
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}
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return false;
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}
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static bool
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drmGetAfbcFormatModifierNameFromArm(uint64_t modifier, FILE *fp)
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{
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@ -368,22 +356,142 @@ drmGetFormatModifierNameFromNvidia(uint64_t modifier)
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return NULL;
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}
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static void
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drmGetFormatModifierNameFromAmdDcc(uint64_t modifier, FILE *fp)
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static char *
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drmGetFormatModifierNameFromAmd(uint64_t modifier)
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{
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uint64_t dcc_max_compressed_block =
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AMD_FMT_MOD_GET(DCC_MAX_COMPRESSED_BLOCK, modifier);
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uint64_t dcc_retile = AMD_FMT_MOD_GET(DCC_RETILE, modifier);
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static const char *gfx9_gfx11_tile_strings[32] = {
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"LINEAR",
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"256B_S",
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"256B_D",
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"256B_R",
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"4KB_Z",
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"4KB_S",
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"4KB_D",
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"4KB_R",
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"64KB_Z",
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"64KB_S",
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"64KB_D",
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"64KB_R",
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"INVALID12",
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"INVALID13",
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"INVALID14",
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"INVALID15",
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"64KB_Z_T",
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"64KB_S_T",
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"64KB_D_T",
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"64KB_R_T",
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"4KB_Z_X",
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"4KB_S_X",
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"4KB_D_X",
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"4KB_R_X",
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"64KB_Z_X",
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"64KB_S_X",
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"64KB_D_X",
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"64KB_R_X",
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"256KB_Z_X",
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"256KB_S_X",
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"256KB_D_X",
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"256KB_R_X",
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};
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static const char *gfx12_tile_strings[32] = {
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"LINEAR",
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"256B_2D",
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"4KB_2D",
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"64KB_2D",
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"256KB_2D",
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"4KB_3D",
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"64KB_3D",
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"256KB_3D",
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/* other values are unused */
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};
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uint64_t tile_version = AMD_FMT_MOD_GET(TILE_VERSION, modifier);
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FILE *fp;
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char *mod_amd = NULL;
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size_t size = 0;
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const char *dcc_max_compressed_block_str = NULL;
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fp = open_memstream(&mod_amd, &size);
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if (!fp)
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return NULL;
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fprintf(fp, ",DCC");
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switch (tile_version) {
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case AMD_FMT_MOD_TILE_VER_GFX9:
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fprintf(fp, "GFX9");
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break;
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case AMD_FMT_MOD_TILE_VER_GFX10:
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fprintf(fp, "GFX10");
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break;
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case AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS:
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fprintf(fp, "GFX10_RBPLUS");
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break;
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case AMD_FMT_MOD_TILE_VER_GFX11:
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fprintf(fp, "GFX11");
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break;
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case AMD_FMT_MOD_TILE_VER_GFX12:
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fprintf(fp, "GFX12");
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break;
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default:
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fclose(fp);
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free(mod_amd);
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return NULL;
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}
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if (dcc_retile)
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fprintf(fp, ",DCC_RETILE");
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if (tile_version >= AMD_FMT_MOD_TILE_VER_GFX12) {
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unsigned tile = AMD_FMT_MOD_GET(TILE, modifier);
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if (!dcc_retile && AMD_FMT_MOD_GET(DCC_PIPE_ALIGN, modifier))
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fprintf(fp, ",DCC_PIPE_ALIGN");
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fprintf(fp, ",%s", gfx12_tile_strings[tile]);
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if (AMD_FMT_MOD_GET(DCC, modifier)) {
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fprintf(fp, ",DCC,DCC_MAX_COMPRESSED_BLOCK=%uB",
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64 << AMD_FMT_MOD_GET(DCC_MAX_COMPRESSED_BLOCK, modifier));
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/* Other DCC fields are unused by GFX12. */
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}
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} else {
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unsigned tile = AMD_FMT_MOD_GET(TILE, modifier);
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fprintf(fp, ",%s", gfx9_gfx11_tile_strings[tile]);
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/* All *_T and *_X modes are affected by chip-specific fields. */
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if (tile >= 16) {
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fprintf(fp, ",PIPE_XOR_BITS=%u",
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(unsigned)AMD_FMT_MOD_GET(PIPE_XOR_BITS, modifier));
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switch (tile_version) {
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case AMD_FMT_MOD_TILE_VER_GFX9:
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fprintf(fp, ",BANK_XOR_BITS=%u",
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(unsigned)AMD_FMT_MOD_GET(BANK_XOR_BITS, modifier));
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break;
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case AMD_FMT_MOD_TILE_VER_GFX10:
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/* Nothing else for GFX10. */
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break;
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case AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS:
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case AMD_FMT_MOD_TILE_VER_GFX11:
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/* This also determines the DCC layout, but DCC is only legal
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* with tile=27 and tile=31 (*_R_X modes).
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*/
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fprintf(fp, ",PACKERS=%u",
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(unsigned)AMD_FMT_MOD_GET(PACKERS, modifier));
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break;
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}
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}
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if (AMD_FMT_MOD_GET(DCC, modifier)) {
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if (tile_version == AMD_FMT_MOD_TILE_VER_GFX9 &&
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(AMD_FMT_MOD_GET(DCC_PIPE_ALIGN, modifier) ||
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AMD_FMT_MOD_GET(DCC_RETILE, modifier))) {
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/* These two only determine the layout of
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* the non-displayable DCC plane.
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*/
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fprintf(fp, ",RB=%u",
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(unsigned)AMD_FMT_MOD_GET(RB, modifier));
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fprintf(fp, ",PIPE=%u",
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(unsigned)AMD_FMT_MOD_GET(PIPE, modifier));
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}
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fprintf(fp, ",DCC,DCC_MAX_COMPRESSED_BLOCK=%uB",
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64 << AMD_FMT_MOD_GET(DCC_MAX_COMPRESSED_BLOCK, modifier));
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if (AMD_FMT_MOD_GET(DCC_INDEPENDENT_64B, modifier))
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fprintf(fp, ",DCC_INDEPENDENT_64B");
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@ -391,136 +499,17 @@ drmGetFormatModifierNameFromAmdDcc(uint64_t modifier, FILE *fp)
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if (AMD_FMT_MOD_GET(DCC_INDEPENDENT_128B, modifier))
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fprintf(fp, ",DCC_INDEPENDENT_128B");
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switch (dcc_max_compressed_block) {
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case AMD_FMT_MOD_DCC_BLOCK_64B:
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dcc_max_compressed_block_str = "64B";
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break;
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case AMD_FMT_MOD_DCC_BLOCK_128B:
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dcc_max_compressed_block_str = "128B";
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break;
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case AMD_FMT_MOD_DCC_BLOCK_256B:
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dcc_max_compressed_block_str = "256B";
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break;
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}
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if (dcc_max_compressed_block_str)
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fprintf(fp, ",DCC_MAX_COMPRESSED_BLOCK=%s",
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dcc_max_compressed_block_str);
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if (AMD_FMT_MOD_GET(DCC_CONSTANT_ENCODE, modifier))
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fprintf(fp, ",DCC_CONSTANT_ENCODE");
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}
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static void
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drmGetFormatModifierNameFromAmdTile(uint64_t modifier, FILE *fp)
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{
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uint64_t pipe_xor_bits, bank_xor_bits, packers, rb;
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uint64_t pipe, pipe_align, dcc, dcc_retile, tile_version;
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if (AMD_FMT_MOD_GET(DCC_PIPE_ALIGN, modifier))
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fprintf(fp, ",DCC_PIPE_ALIGN");
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pipe_align = AMD_FMT_MOD_GET(DCC_PIPE_ALIGN, modifier);
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pipe_xor_bits = AMD_FMT_MOD_GET(PIPE_XOR_BITS, modifier);
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dcc = AMD_FMT_MOD_GET(DCC, modifier);
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dcc_retile = AMD_FMT_MOD_GET(DCC_RETILE, modifier);
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tile_version = AMD_FMT_MOD_GET(TILE_VERSION, modifier);
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fprintf(fp, ",PIPE_XOR_BITS=%"PRIu64, pipe_xor_bits);
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if (tile_version == AMD_FMT_MOD_TILE_VER_GFX9) {
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bank_xor_bits = AMD_FMT_MOD_GET(BANK_XOR_BITS, modifier);
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fprintf(fp, ",BANK_XOR_BITS=%"PRIu64, bank_xor_bits);
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}
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if (tile_version == AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) {
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packers = AMD_FMT_MOD_GET(PACKERS, modifier);
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fprintf(fp, ",PACKERS=%"PRIu64, packers);
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}
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if (dcc && tile_version == AMD_FMT_MOD_TILE_VER_GFX9) {
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rb = AMD_FMT_MOD_GET(RB, modifier);
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fprintf(fp, ",RB=%"PRIu64, rb);
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}
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if (dcc && tile_version == AMD_FMT_MOD_TILE_VER_GFX9 &&
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(dcc_retile || pipe_align)) {
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pipe = AMD_FMT_MOD_GET(PIPE, modifier);
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fprintf(fp, ",PIPE_%"PRIu64, pipe);
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if (AMD_FMT_MOD_GET(DCC_RETILE, modifier))
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fprintf(fp, ",DCC_RETILE");
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}
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}
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static char *
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drmGetFormatModifierNameFromAmd(uint64_t modifier)
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{
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uint64_t tile, tile_version, dcc;
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FILE *fp;
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char *mod_amd = NULL;
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size_t size = 0;
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const char *str_tile = NULL;
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const char *str_tile_version = NULL;
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tile = AMD_FMT_MOD_GET(TILE, modifier);
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tile_version = AMD_FMT_MOD_GET(TILE_VERSION, modifier);
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dcc = AMD_FMT_MOD_GET(DCC, modifier);
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fp = open_memstream(&mod_amd, &size);
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if (!fp)
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return NULL;
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/* add tile */
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switch (tile_version) {
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case AMD_FMT_MOD_TILE_VER_GFX9:
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str_tile_version = "GFX9";
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break;
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case AMD_FMT_MOD_TILE_VER_GFX10:
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str_tile_version = "GFX10";
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break;
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case AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS:
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str_tile_version = "GFX10_RBPLUS";
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break;
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case AMD_FMT_MOD_TILE_VER_GFX11:
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str_tile_version = "GFX11";
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break;
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}
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if (str_tile_version) {
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fprintf(fp, "%s", str_tile_version);
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} else {
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fclose(fp);
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free(mod_amd);
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return NULL;
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}
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/* add tile str */
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switch (tile) {
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case AMD_FMT_MOD_TILE_GFX9_64K_S:
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str_tile = "GFX9_64K_S";
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break;
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case AMD_FMT_MOD_TILE_GFX9_64K_D:
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str_tile = "GFX9_64K_D";
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break;
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case AMD_FMT_MOD_TILE_GFX9_64K_S_X:
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str_tile = "GFX9_64K_S_X";
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break;
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case AMD_FMT_MOD_TILE_GFX9_64K_D_X:
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str_tile = "GFX9_64K_D_X";
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break;
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case AMD_FMT_MOD_TILE_GFX9_64K_R_X:
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str_tile = "GFX9_64K_R_X";
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break;
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case AMD_FMT_MOD_TILE_GFX11_256K_R_X:
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str_tile = "GFX11_256K_R_X";
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break;
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}
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if (str_tile)
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fprintf(fp, ",%s", str_tile);
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if (dcc)
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drmGetFormatModifierNameFromAmdDcc(modifier, fp);
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if (tile_version >= AMD_FMT_MOD_TILE_VER_GFX9 && is_x_t_amd_gfx9_tile(tile))
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drmGetFormatModifierNameFromAmdTile(modifier, fp);
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fclose(fp);
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return mod_amd;
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}
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