diff --git a/bsd-core/drmP.h b/bsd-core/drmP.h index ad23fc6f..5c3cb92c 100644 --- a/bsd-core/drmP.h +++ b/bsd-core/drmP.h @@ -377,7 +377,6 @@ typedef struct drm_sg_mem { unsigned long handle; void *virtual; int pages; - struct page **pagelist; dma_addr_t *busaddr; } drm_sg_mem_t; diff --git a/bsd-core/drm_os_freebsd.h b/bsd-core/drm_os_freebsd.h index 00136962..00f5c434 100644 --- a/bsd-core/drm_os_freebsd.h +++ b/bsd-core/drm_os_freebsd.h @@ -102,15 +102,17 @@ #define DRM_MALLOC(size) malloc( size, DRM(M_DRM), M_NOWAIT ) #define DRM_FREE(pt) free( pt, DRM(M_DRM) ) #define DRM_VTOPHYS(addr) vtophys(addr) -#define DRM_READ8(addr) *((volatile char *)(addr)) -#define DRM_READ32(addr) *((volatile long *)(addr)) -#define DRM_WRITE8(addr, val) *((volatile char *)(addr)) = (val) -#define DRM_WRITE32(addr, val) *((volatile long *)(addr)) = (val) + +/* Read/write from bus space, with byteswapping to le if necessary */ +#define DRM_READ8(map, offset) *(volatile u_int8_t *) (((unsigned long)(map)->handle) + (offset)) +#define DRM_READ32(map, offset) *(volatile u_int32_t *)(((unsigned long)(map)->handle) + (offset)) +#define DRM_WRITE8(map, offset, val) *(volatile u_int8_t *) (((unsigned long)(map)->handle) + (offset)) = val +#define DRM_WRITE32(map, offset, val) *(volatile u_int32_t *)(((unsigned long)(map)->handle) + (offset)) = val /* -#define DRM_READ8(map, offset) *(volatile u_int8_t *)(((unsigned long)map->handle) + offset) -#define DRM_READ32(map, offset) *(volatile u_int32_t *)(((unsigned long)map->handle) + offset) -#define DRM_WRITE8(map, offset, val) *(volatile u_int8_t *)(((unsigned long)map->handle) + offset) = val -#define DRM_WRITE32(map, offset, val) *(volatile u_int32_t *)(((unsigned long)map->handle) + offset) = val +#define DRM_READ8(map, offset) bus_space_read_1( (map)->iot, (map)->ioh, (offset) ) +#define DRM_READ32(map, offset) bus_space_read_4( (map)->iot, (map)->ioh, (offset) ) +#define DRM_WRITE8(map, offset, val) bus_space_write_1( (map)->iot, (map)->ioh, (offset), (val) ) +#define DRM_WRITE32(map, offset, val) bus_space_write_4( (map)->iot, (map)->ioh, (offset), (val) ) */ #define DRM_AGP_FIND_DEVICE() agp_find_device() #define DRM_ERR(v) v @@ -172,7 +174,7 @@ while (!condition) { \ copyin(user, kern, size) /* Macros for userspace access with checking readability once */ /* FIXME: can't find equivalent functionality for nocheck yet. - * It's be slower than linux, but should be correct. + * It'll be slower than linux, but should be correct. */ #define DRM_VERIFYAREA_READ( uaddr, size ) \ (!useracc((caddr_t)uaddr, size, VM_PROT_READ)) @@ -181,17 +183,10 @@ while (!condition) { \ #define DRM_GET_USER_UNCHECKED(val, uaddr) \ ((val) = fuword(uaddr), 0) -/* From machine/bus_at386.h on i386 */ -#define DRM_READMEMORYBARRIER() \ -do { \ - __asm __volatile("lock; addl $0,0(%%esp)" : : : "memory"); \ -} while (0) - -#define DRM_WRITEMEMORYBARRIER() \ -do { \ - __asm __volatile("" : : : "memory"); \ -} while (0) - +#define DRM_WRITEMEMORYBARRIER( map ) \ + bus_space_barrier((map)->iot, (map)->ioh, 0, (map)->size, 0); +#define DRM_READMEMORYBARRIER( map ) \ + bus_space_barrier((map)->iot, (map)->ioh, 0, (map)->size, BUS_SPACE_BARRIER_READ); #define PAGE_ALIGN(addr) round_page(addr) diff --git a/bsd-core/drm_os_netbsd.h b/bsd-core/drm_os_netbsd.h index b14ed74b..07704afd 100644 --- a/bsd-core/drm_os_netbsd.h +++ b/bsd-core/drm_os_netbsd.h @@ -78,16 +78,12 @@ extern drm_device_t *DRM(devs)[16]; #define DRM_MALLOC(size) malloc( size, DRM(M_DRM), M_NOWAIT ) #define DRM_FREE(pt) free( pt, DRM(M_DRM) ) #define DRM_VTOPHYS(addr) vtophys(addr) -#define DRM_READ8(addr) *((volatile char *)(addr)) -#define DRM_READ32(addr) *((volatile long *)(addr)) -#define DRM_WRITE8(addr, val) *((volatile char *)(addr)) = (val) -#define DRM_WRITE32(addr, val) *((volatile long *)(addr)) = (val) -/* -#define DRM_READ8(map, offset) bus_space_read_1( map->iot, map->ioh, offset, val ); -#define DRM_READ32(map, offset) bus_space_read_4( map->iot, map->ioh, offset, val ); -#define DRM_WRITE8(map, offset, val) bus_space_write_1( map->iot, map->ioh, offset, val ); -#define DRM_WRITE32(map, offset, val) bus_space_write_4( map->iot, map->ioh, offset, val ); -*/ + +#define DRM_READ8(map, offset) bus_space_read_1( (map)->iot, (map)->ioh, (offset) ) +#define DRM_READ32(map, offset) bus_space_read_4( (map)->iot, (map)->ioh, (offset) ) +#define DRM_WRITE8(map, offset, val) bus_space_write_1( (map)->iot, (map)->ioh, (offset), (val) ) +#define DRM_WRITE32(map, offset, val) bus_space_write_4( (map)->iot, (map)->ioh, (offset), (val) ) + #define DRM_AGP_FIND_DEVICE() agp_find_device(0) #define DRM_PRIV \ @@ -131,17 +127,10 @@ do { \ #define DRM_COPY_FROM_USER(arg1, arg2, arg3) \ copyin(arg2, arg1, arg3) -#define DRM_READMEMORYBARRIER() \ -{ \ - int xchangeDummy; \ - DRM_DEBUG("%s\n", __FUNCTION__); \ - __asm__ volatile(" push %%eax ; xchg %%eax, %0 ; pop %%eax" : : "m" (xchangeDummy)); \ - __asm__ volatile(" push %%eax ; push %%ebx ; push %%ecx ; push %%edx ;" \ - " movl $0,%%eax ; cpuid ; pop %%edx ; pop %%ecx ; pop %%ebx ;" \ - " pop %%eax" : /* no outputs */ : /* no inputs */ ); \ -} while (0); - -#define DRM_WRITEMEMORYBARRIER() DRM_READMEMORYBARRIER() +#define DRM_WRITEMEMORYBARRIER( map ) \ + bus_space_barrier((map)->iot, (map)->ioh, 0, (map)->size, 0); +#define DRM_READMEMORYBARRIER( map ) \ + bus_space_barrier((map)->iot, (map)->ioh, 0, (map)->size, BUS_SPACE_BARRIER_READ); #define DRM_WAKEUP(w) wakeup(w) #define DRM_WAKEUP_INT(w) wakeup(w) diff --git a/bsd/drmP.h b/bsd/drmP.h index ad23fc6f..5c3cb92c 100644 --- a/bsd/drmP.h +++ b/bsd/drmP.h @@ -377,7 +377,6 @@ typedef struct drm_sg_mem { unsigned long handle; void *virtual; int pages; - struct page **pagelist; dma_addr_t *busaddr; } drm_sg_mem_t; diff --git a/bsd/drm_os_freebsd.h b/bsd/drm_os_freebsd.h index 00136962..00f5c434 100644 --- a/bsd/drm_os_freebsd.h +++ b/bsd/drm_os_freebsd.h @@ -102,15 +102,17 @@ #define DRM_MALLOC(size) malloc( size, DRM(M_DRM), M_NOWAIT ) #define DRM_FREE(pt) free( pt, DRM(M_DRM) ) #define DRM_VTOPHYS(addr) vtophys(addr) -#define DRM_READ8(addr) *((volatile char *)(addr)) -#define DRM_READ32(addr) *((volatile long *)(addr)) -#define DRM_WRITE8(addr, val) *((volatile char *)(addr)) = (val) -#define DRM_WRITE32(addr, val) *((volatile long *)(addr)) = (val) + +/* Read/write from bus space, with byteswapping to le if necessary */ +#define DRM_READ8(map, offset) *(volatile u_int8_t *) (((unsigned long)(map)->handle) + (offset)) +#define DRM_READ32(map, offset) *(volatile u_int32_t *)(((unsigned long)(map)->handle) + (offset)) +#define DRM_WRITE8(map, offset, val) *(volatile u_int8_t *) (((unsigned long)(map)->handle) + (offset)) = val +#define DRM_WRITE32(map, offset, val) *(volatile u_int32_t *)(((unsigned long)(map)->handle) + (offset)) = val /* -#define DRM_READ8(map, offset) *(volatile u_int8_t *)(((unsigned long)map->handle) + offset) -#define DRM_READ32(map, offset) *(volatile u_int32_t *)(((unsigned long)map->handle) + offset) -#define DRM_WRITE8(map, offset, val) *(volatile u_int8_t *)(((unsigned long)map->handle) + offset) = val -#define DRM_WRITE32(map, offset, val) *(volatile u_int32_t *)(((unsigned long)map->handle) + offset) = val +#define DRM_READ8(map, offset) bus_space_read_1( (map)->iot, (map)->ioh, (offset) ) +#define DRM_READ32(map, offset) bus_space_read_4( (map)->iot, (map)->ioh, (offset) ) +#define DRM_WRITE8(map, offset, val) bus_space_write_1( (map)->iot, (map)->ioh, (offset), (val) ) +#define DRM_WRITE32(map, offset, val) bus_space_write_4( (map)->iot, (map)->ioh, (offset), (val) ) */ #define DRM_AGP_FIND_DEVICE() agp_find_device() #define DRM_ERR(v) v @@ -172,7 +174,7 @@ while (!condition) { \ copyin(user, kern, size) /* Macros for userspace access with checking readability once */ /* FIXME: can't find equivalent functionality for nocheck yet. - * It's be slower than linux, but should be correct. + * It'll be slower than linux, but should be correct. */ #define DRM_VERIFYAREA_READ( uaddr, size ) \ (!useracc((caddr_t)uaddr, size, VM_PROT_READ)) @@ -181,17 +183,10 @@ while (!condition) { \ #define DRM_GET_USER_UNCHECKED(val, uaddr) \ ((val) = fuword(uaddr), 0) -/* From machine/bus_at386.h on i386 */ -#define DRM_READMEMORYBARRIER() \ -do { \ - __asm __volatile("lock; addl $0,0(%%esp)" : : : "memory"); \ -} while (0) - -#define DRM_WRITEMEMORYBARRIER() \ -do { \ - __asm __volatile("" : : : "memory"); \ -} while (0) - +#define DRM_WRITEMEMORYBARRIER( map ) \ + bus_space_barrier((map)->iot, (map)->ioh, 0, (map)->size, 0); +#define DRM_READMEMORYBARRIER( map ) \ + bus_space_barrier((map)->iot, (map)->ioh, 0, (map)->size, BUS_SPACE_BARRIER_READ); #define PAGE_ALIGN(addr) round_page(addr) diff --git a/bsd/drm_os_netbsd.h b/bsd/drm_os_netbsd.h index b14ed74b..07704afd 100644 --- a/bsd/drm_os_netbsd.h +++ b/bsd/drm_os_netbsd.h @@ -78,16 +78,12 @@ extern drm_device_t *DRM(devs)[16]; #define DRM_MALLOC(size) malloc( size, DRM(M_DRM), M_NOWAIT ) #define DRM_FREE(pt) free( pt, DRM(M_DRM) ) #define DRM_VTOPHYS(addr) vtophys(addr) -#define DRM_READ8(addr) *((volatile char *)(addr)) -#define DRM_READ32(addr) *((volatile long *)(addr)) -#define DRM_WRITE8(addr, val) *((volatile char *)(addr)) = (val) -#define DRM_WRITE32(addr, val) *((volatile long *)(addr)) = (val) -/* -#define DRM_READ8(map, offset) bus_space_read_1( map->iot, map->ioh, offset, val ); -#define DRM_READ32(map, offset) bus_space_read_4( map->iot, map->ioh, offset, val ); -#define DRM_WRITE8(map, offset, val) bus_space_write_1( map->iot, map->ioh, offset, val ); -#define DRM_WRITE32(map, offset, val) bus_space_write_4( map->iot, map->ioh, offset, val ); -*/ + +#define DRM_READ8(map, offset) bus_space_read_1( (map)->iot, (map)->ioh, (offset) ) +#define DRM_READ32(map, offset) bus_space_read_4( (map)->iot, (map)->ioh, (offset) ) +#define DRM_WRITE8(map, offset, val) bus_space_write_1( (map)->iot, (map)->ioh, (offset), (val) ) +#define DRM_WRITE32(map, offset, val) bus_space_write_4( (map)->iot, (map)->ioh, (offset), (val) ) + #define DRM_AGP_FIND_DEVICE() agp_find_device(0) #define DRM_PRIV \ @@ -131,17 +127,10 @@ do { \ #define DRM_COPY_FROM_USER(arg1, arg2, arg3) \ copyin(arg2, arg1, arg3) -#define DRM_READMEMORYBARRIER() \ -{ \ - int xchangeDummy; \ - DRM_DEBUG("%s\n", __FUNCTION__); \ - __asm__ volatile(" push %%eax ; xchg %%eax, %0 ; pop %%eax" : : "m" (xchangeDummy)); \ - __asm__ volatile(" push %%eax ; push %%ebx ; push %%ecx ; push %%edx ;" \ - " movl $0,%%eax ; cpuid ; pop %%edx ; pop %%ecx ; pop %%ebx ;" \ - " pop %%eax" : /* no outputs */ : /* no inputs */ ); \ -} while (0); - -#define DRM_WRITEMEMORYBARRIER() DRM_READMEMORYBARRIER() +#define DRM_WRITEMEMORYBARRIER( map ) \ + bus_space_barrier((map)->iot, (map)->ioh, 0, (map)->size, 0); +#define DRM_READMEMORYBARRIER( map ) \ + bus_space_barrier((map)->iot, (map)->ioh, 0, (map)->size, BUS_SPACE_BARRIER_READ); #define DRM_WAKEUP(w) wakeup(w) #define DRM_WAKEUP_INT(w) wakeup(w) diff --git a/linux-core/drm_os_linux.h b/linux-core/drm_os_linux.h index 8863e93f..332c3fd9 100644 --- a/linux-core/drm_os_linux.h +++ b/linux-core/drm_os_linux.h @@ -7,18 +7,12 @@ #define DRM_ERR(d) -(d) #define DRM_CURRENTPID current->pid #define DRM_UDELAY(d) udelay(d) -#define DRM_READ8(addr) readb(addr) -#define DRM_READ32(addr) readl(addr) -#define DRM_WRITE8(addr, val) writeb(val, addr) -#define DRM_WRITE32(addr, val) writel(val, addr) -/* -#define DRM_READ8(map, offset) readb((unsigned long)map->handle + offset) -#define DRM_READ32(map, offset) readl((unsigned long)map->handle + offset) -#define DRM_WRITE8(map, offset, val) writeb(val, (unsigned long)map->handle + offset) -#define DRM_WRITE32(map, offset, val) writel(val, (unsigned long)map->handle + offset) -*/ -#define DRM_READMEMORYBARRIER() mb() -#define DRM_WRITEMEMORYBARRIER() wmb() +#define DRM_READ8(map, offset) readb(((unsigned long)(map)->handle) + (offset)) +#define DRM_READ32(map, offset) readl(((unsigned long)(map)->handle) + (offset)) +#define DRM_WRITE8(map, offset, val) writeb(val, ((unsigned long)(map)->handle) + (offset)) +#define DRM_WRITE32(map, offset, val) writel(val, ((unsigned long)(map)->handle) + (offset)) +#define DRM_READMEMORYBARRIER(map) mb() +#define DRM_WRITEMEMORYBARRIER(map) wmb() #define DRM_DEVICE drm_file_t *priv = filp->private_data; \ drm_device_t *dev = priv->dev diff --git a/linux/drm_os_linux.h b/linux/drm_os_linux.h index 8863e93f..332c3fd9 100644 --- a/linux/drm_os_linux.h +++ b/linux/drm_os_linux.h @@ -7,18 +7,12 @@ #define DRM_ERR(d) -(d) #define DRM_CURRENTPID current->pid #define DRM_UDELAY(d) udelay(d) -#define DRM_READ8(addr) readb(addr) -#define DRM_READ32(addr) readl(addr) -#define DRM_WRITE8(addr, val) writeb(val, addr) -#define DRM_WRITE32(addr, val) writel(val, addr) -/* -#define DRM_READ8(map, offset) readb((unsigned long)map->handle + offset) -#define DRM_READ32(map, offset) readl((unsigned long)map->handle + offset) -#define DRM_WRITE8(map, offset, val) writeb(val, (unsigned long)map->handle + offset) -#define DRM_WRITE32(map, offset, val) writel(val, (unsigned long)map->handle + offset) -*/ -#define DRM_READMEMORYBARRIER() mb() -#define DRM_WRITEMEMORYBARRIER() wmb() +#define DRM_READ8(map, offset) readb(((unsigned long)(map)->handle) + (offset)) +#define DRM_READ32(map, offset) readl(((unsigned long)(map)->handle) + (offset)) +#define DRM_WRITE8(map, offset, val) writeb(val, ((unsigned long)(map)->handle) + (offset)) +#define DRM_WRITE32(map, offset, val) writel(val, ((unsigned long)(map)->handle) + (offset)) +#define DRM_READMEMORYBARRIER(map) mb() +#define DRM_WRITEMEMORYBARRIER(map) wmb() #define DRM_DEVICE drm_file_t *priv = filp->private_data; \ drm_device_t *dev = priv->dev diff --git a/shared-core/mga_drv.h b/shared-core/mga_drv.h index cd889e75..d7f85af5 100644 --- a/shared-core/mga_drv.h +++ b/shared-core/mga_drv.h @@ -131,16 +131,15 @@ extern int mga_getparam( DRM_IOCTL_ARGS ); extern int mga_warp_install_microcode( drm_mga_private_t *dev_priv ); extern int mga_warp_init( drm_mga_private_t *dev_priv ); -#define mga_flush_write_combine() DRM_WRITEMEMORYBARRIER() - +#define mga_flush_write_combine() DRM_WRITEMEMORYBARRIER(dev_priv->primary) +#if defined(__linux__) && defined(__alpha__) #define MGA_BASE( reg ) ((unsigned long)(dev_priv->mmio->handle)) #define MGA_ADDR( reg ) (MGA_BASE(reg) + reg) #define MGA_DEREF( reg ) *(volatile u32 *)MGA_ADDR( reg ) #define MGA_DEREF8( reg ) *(volatile u8 *)MGA_ADDR( reg ) -#ifdef __alpha__ #define MGA_READ( reg ) (_MGA_READ((u32 *)MGA_ADDR(reg))) #define MGA_READ8( reg ) (_MGA_READ((u8 *)MGA_ADDR(reg))) #define MGA_WRITE( reg, val ) do { DRM_WRITEMEMORYBARRIER(); MGA_DEREF( reg ) = val; } while (0) @@ -151,18 +150,11 @@ static inline u32 _MGA_READ(u32 *addr) DRM_READMEMORYBARRIER(); return *(volatile u32 *)addr; } - #else -#define MGA_READ( reg ) MGA_DEREF( reg ) -#define MGA_READ8( reg ) MGA_DEREF8( reg ) -#define MGA_WRITE( reg, val ) do { MGA_DEREF( reg ) = val; } while (0) -#define MGA_WRITE8( reg, val ) do { MGA_DEREF8( reg ) = val; } while (0) -/* -#define MGA_READ8( reg ) DRM_READ8(dev_priv->mmio, reg) -#define MGA_READ( reg ) DRM_READ32(dev_priv->mmio, reg) -#define MGA_WRITE8( reg, val ) DRM_WRITE8(dev_priv->mmio, reg, val) -#define MGA_WRITE( reg, val ) DRM_WRITE32(dev_priv->mmio, reg, val) -*/ +#define MGA_READ8( reg ) DRM_READ8(dev_priv->mmio, (reg)) +#define MGA_READ( reg ) DRM_READ32(dev_priv->mmio, (reg)) +#define MGA_WRITE8( reg, val ) DRM_WRITE8(dev_priv->mmio, (reg), (val)) +#define MGA_WRITE( reg, val ) DRM_WRITE32(dev_priv->mmio, (reg), (val)) #endif #define DWGREG0 0x1c00 diff --git a/shared-core/r128_cce.c b/shared-core/r128_cce.c index 5175885e..8d305b75 100644 --- a/shared-core/r128_cce.c +++ b/shared-core/r128_cce.c @@ -579,6 +579,7 @@ static int r128_do_init_cce( drm_device_t *dev, drm_r128_init_t *init ) (dev_priv->ring.size / sizeof(u32)) - 1; dev_priv->ring.high_mark = 128; + dev_priv->ring.ring_rptr = dev_priv->ring_rptr; dev_priv->sarea_priv->last_frame = 0; R128_WRITE( R128_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame ); diff --git a/shared-core/r128_drv.h b/shared-core/r128_drv.h index 26464a5a..5e6f1215 100644 --- a/shared-core/r128_drv.h +++ b/shared-core/r128_drv.h @@ -34,8 +34,8 @@ #ifndef __R128_DRV_H__ #define __R128_DRV_H__ -#define GET_RING_HEAD(ring) DRM_READ32( (volatile u32 *) (ring)->head ) -#define SET_RING_HEAD(ring,val) DRM_WRITE32( (volatile u32 *) (ring)->head, (val) ) +#define GET_RING_HEAD(ring) DRM_READ32( (ring)->ring_rptr, 0 ) /* (ring)->head */ +#define SET_RING_HEAD(ring,val) DRM_WRITE32( (ring)->ring_rptr, 0, (val) ) /* (ring)->head */ typedef struct drm_r128_freelist { unsigned int age; @@ -56,6 +56,7 @@ typedef struct drm_r128_ring_buffer { int space; int high_mark; + drm_local_map_t *ring_rptr; } drm_r128_ring_buffer_t; typedef struct drm_r128_private { @@ -370,21 +371,10 @@ extern int r128_cce_indirect( DRM_IOCTL_ARGS ); #define R128_PERFORMANCE_BOXES 0 - -#define R128_BASE(reg) ((unsigned long)(dev_priv->mmio->handle)) -#define R128_ADDR(reg) (R128_BASE( reg ) + reg) - -#define R128_READ(reg) DRM_READ32( (volatile u32 *) R128_ADDR(reg) ) -#define R128_WRITE(reg,val) DRM_WRITE32( (volatile u32 *) R128_ADDR(reg), (val) ) - -#define R128_READ8(reg) DRM_READ8( (volatile u8 *) R128_ADDR(reg) ) -#define R128_WRITE8(reg,val) DRM_WRITE8( (volatile u8 *) R128_ADDR(reg), (val) ) -/* -#define R128_READ(reg) DRM_READ32( dev_priv->mmio, reg ) -#define R128_WRITE(reg,val) DRM_WRITE32( dev_priv->mmio, reg, (val) ) -#define R128_READ8(reg) DRM_READ8( dev_priv->mmio, reg ) -#define R128_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, reg, (val) ) -*/ +#define R128_READ(reg) DRM_READ32( dev_priv->mmio, (reg) ) +#define R128_WRITE(reg,val) DRM_WRITE32( dev_priv->mmio, (reg), (val) ) +#define R128_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) ) +#define R128_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, (reg), (val) ) #define R128_WRITE_PLL(addr,val) \ do { \ @@ -459,7 +449,7 @@ do { \ #if defined(__powerpc__) #define r128_flush_write_combine() (void) GET_RING_HEAD( &dev_priv->ring ) #else -#define r128_flush_write_combine() DRM_WRITEMEMORYBARRIER() +#define r128_flush_write_combine() DRM_WRITEMEMORYBARRIER(dev_priv->ring_rptr) #endif diff --git a/shared-core/radeon_cp.c b/shared-core/radeon_cp.c index c0fb63ef..d004b681 100644 --- a/shared-core/radeon_cp.c +++ b/shared-core/radeon_cp.c @@ -926,11 +926,11 @@ static void radeon_cp_init_ring_buffer( drm_device_t *dev, RADEON_WRITE( RADEON_SCRATCH_UMSK, 0x7 ); /* Writeback doesn't seem to work everywhere, test it first */ - DRM_WRITE32( &dev_priv->scratch[1], 0 ); + DRM_WRITE32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(1), 0 ); RADEON_WRITE( RADEON_SCRATCH_REG1, 0xdeadbeef ); for ( tmp = 0 ; tmp < dev_priv->usec_timeout ; tmp++ ) { - if ( DRM_READ32( &dev_priv->scratch[1] ) == 0xdeadbeef ) + if ( DRM_READ32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(1) ) == 0xdeadbeef ) break; DRM_UDELAY( 1 ); } @@ -1217,6 +1217,7 @@ static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init ) (dev_priv->ring.size / sizeof(u32)) - 1; dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK; + dev_priv->ring.ring_rptr = dev_priv->ring_rptr; #if __REALLY_HAVE_SG if ( dev_priv->is_pci ) { @@ -1509,7 +1510,7 @@ drm_buf_t *radeon_freelist_get( drm_device_t *dev ) drm_buf_t *buf; int i, t; int start; - u32 done_age = DRM_READ32(&dev_priv->scratch[1]); + u32 done_age = DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1)); if ( ++dev_priv->last_buf >= dma->buf_count ) dev_priv->last_buf = 0; diff --git a/shared-core/radeon_drv.h b/shared-core/radeon_drv.h index 9ba86116..882c77fd 100644 --- a/shared-core/radeon_drv.h +++ b/shared-core/radeon_drv.h @@ -31,8 +31,8 @@ #ifndef __RADEON_DRV_H__ #define __RADEON_DRV_H__ -#define GET_RING_HEAD(ring) DRM_READ32( (volatile u32 *) (ring)->head ) -#define SET_RING_HEAD(ring,val) DRM_WRITE32( (volatile u32 *) (ring)->head , (val)) +#define GET_RING_HEAD(ring) DRM_READ32( (ring)->ring_rptr, 0 ) /* (ring)->head */ +#define SET_RING_HEAD(ring,val) DRM_WRITE32( (ring)->ring_rptr, 0, (val) ) /* (ring)->head */ typedef struct drm_radeon_freelist { unsigned int age; @@ -53,6 +53,7 @@ typedef struct drm_radeon_ring_buffer { int space; int high_mark; + drm_local_map_t *ring_rptr; } drm_radeon_ring_buffer_t; typedef struct drm_radeon_depth_clear_t { @@ -266,8 +267,10 @@ extern int radeon_emit_irq(drm_device_t *dev); #define RADEON_SCRATCH_UMSK 0x0770 #define RADEON_SCRATCH_ADDR 0x0774 +#define RADEON_SCRATCHOFF( x ) (RADEON_SCRATCH_REG_OFFSET + 4*(x)) + #define GET_SCRATCH( x ) (dev_priv->writeback_works \ - ? DRM_READ32( &dev_priv->scratch[(x)] ) \ + ? DRM_READ32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(x) ) \ : RADEON_READ( RADEON_SCRATCH_REG0 + 4*(x) ) ) @@ -686,23 +689,10 @@ extern int radeon_emit_irq(drm_device_t *dev); #define RADEON_RING_HIGH_MARK 128 - -#define RADEON_BASE(reg) ((unsigned long)(dev_priv->mmio->handle)) -#define RADEON_ADDR(reg) (RADEON_BASE( reg ) + reg) - -#define RADEON_READ(reg) DRM_READ32( (volatile u32 *) RADEON_ADDR(reg) ) -#define RADEON_WRITE(reg,val) DRM_WRITE32( (volatile u32 *) RADEON_ADDR(reg), (val) ) -/* -#define RADEON_READ(reg) DRM_READ32( dev_priv->mmio, reg ) -#define RADEON_WRITE(reg,val) DRM_WRITE32( dev_priv->mmio, reg, (val) ) -*/ - -#define RADEON_READ8(reg) DRM_READ8( (volatile u8 *) RADEON_ADDR(reg) ) -#define RADEON_WRITE8(reg,val) DRM_WRITE8( (volatile u8 *) RADEON_ADDR(reg), (val) ) -/* -#define RADEON_READ8(reg) DRM_READ8( dev_priv->mmio, reg ) -#define RADEON_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, reg, (val) ) -*/ +#define RADEON_READ(reg) DRM_READ32( dev_priv->mmio, (reg) ) +#define RADEON_WRITE(reg,val) DRM_WRITE32( dev_priv->mmio, (reg), (val) ) +#define RADEON_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) ) +#define RADEON_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, (reg), (val) ) #define RADEON_WRITE_PLL( addr, val ) \ do { \ @@ -834,7 +824,7 @@ do { \ #if defined(__powerpc__) #define radeon_flush_write_combine() (void) GET_RING_HEAD( &dev_priv->ring ) #else -#define radeon_flush_write_combine() DRM_WRITEMEMORYBARRIER() +#define radeon_flush_write_combine() DRM_WRITEMEMORYBARRIER( dev_priv->ring_rtpr ) #endif diff --git a/shared/mga_drv.h b/shared/mga_drv.h index cd889e75..d7f85af5 100644 --- a/shared/mga_drv.h +++ b/shared/mga_drv.h @@ -131,16 +131,15 @@ extern int mga_getparam( DRM_IOCTL_ARGS ); extern int mga_warp_install_microcode( drm_mga_private_t *dev_priv ); extern int mga_warp_init( drm_mga_private_t *dev_priv ); -#define mga_flush_write_combine() DRM_WRITEMEMORYBARRIER() - +#define mga_flush_write_combine() DRM_WRITEMEMORYBARRIER(dev_priv->primary) +#if defined(__linux__) && defined(__alpha__) #define MGA_BASE( reg ) ((unsigned long)(dev_priv->mmio->handle)) #define MGA_ADDR( reg ) (MGA_BASE(reg) + reg) #define MGA_DEREF( reg ) *(volatile u32 *)MGA_ADDR( reg ) #define MGA_DEREF8( reg ) *(volatile u8 *)MGA_ADDR( reg ) -#ifdef __alpha__ #define MGA_READ( reg ) (_MGA_READ((u32 *)MGA_ADDR(reg))) #define MGA_READ8( reg ) (_MGA_READ((u8 *)MGA_ADDR(reg))) #define MGA_WRITE( reg, val ) do { DRM_WRITEMEMORYBARRIER(); MGA_DEREF( reg ) = val; } while (0) @@ -151,18 +150,11 @@ static inline u32 _MGA_READ(u32 *addr) DRM_READMEMORYBARRIER(); return *(volatile u32 *)addr; } - #else -#define MGA_READ( reg ) MGA_DEREF( reg ) -#define MGA_READ8( reg ) MGA_DEREF8( reg ) -#define MGA_WRITE( reg, val ) do { MGA_DEREF( reg ) = val; } while (0) -#define MGA_WRITE8( reg, val ) do { MGA_DEREF8( reg ) = val; } while (0) -/* -#define MGA_READ8( reg ) DRM_READ8(dev_priv->mmio, reg) -#define MGA_READ( reg ) DRM_READ32(dev_priv->mmio, reg) -#define MGA_WRITE8( reg, val ) DRM_WRITE8(dev_priv->mmio, reg, val) -#define MGA_WRITE( reg, val ) DRM_WRITE32(dev_priv->mmio, reg, val) -*/ +#define MGA_READ8( reg ) DRM_READ8(dev_priv->mmio, (reg)) +#define MGA_READ( reg ) DRM_READ32(dev_priv->mmio, (reg)) +#define MGA_WRITE8( reg, val ) DRM_WRITE8(dev_priv->mmio, (reg), (val)) +#define MGA_WRITE( reg, val ) DRM_WRITE32(dev_priv->mmio, (reg), (val)) #endif #define DWGREG0 0x1c00 diff --git a/shared/r128_cce.c b/shared/r128_cce.c index 5175885e..8d305b75 100644 --- a/shared/r128_cce.c +++ b/shared/r128_cce.c @@ -579,6 +579,7 @@ static int r128_do_init_cce( drm_device_t *dev, drm_r128_init_t *init ) (dev_priv->ring.size / sizeof(u32)) - 1; dev_priv->ring.high_mark = 128; + dev_priv->ring.ring_rptr = dev_priv->ring_rptr; dev_priv->sarea_priv->last_frame = 0; R128_WRITE( R128_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame ); diff --git a/shared/r128_drv.h b/shared/r128_drv.h index 26464a5a..5e6f1215 100644 --- a/shared/r128_drv.h +++ b/shared/r128_drv.h @@ -34,8 +34,8 @@ #ifndef __R128_DRV_H__ #define __R128_DRV_H__ -#define GET_RING_HEAD(ring) DRM_READ32( (volatile u32 *) (ring)->head ) -#define SET_RING_HEAD(ring,val) DRM_WRITE32( (volatile u32 *) (ring)->head, (val) ) +#define GET_RING_HEAD(ring) DRM_READ32( (ring)->ring_rptr, 0 ) /* (ring)->head */ +#define SET_RING_HEAD(ring,val) DRM_WRITE32( (ring)->ring_rptr, 0, (val) ) /* (ring)->head */ typedef struct drm_r128_freelist { unsigned int age; @@ -56,6 +56,7 @@ typedef struct drm_r128_ring_buffer { int space; int high_mark; + drm_local_map_t *ring_rptr; } drm_r128_ring_buffer_t; typedef struct drm_r128_private { @@ -370,21 +371,10 @@ extern int r128_cce_indirect( DRM_IOCTL_ARGS ); #define R128_PERFORMANCE_BOXES 0 - -#define R128_BASE(reg) ((unsigned long)(dev_priv->mmio->handle)) -#define R128_ADDR(reg) (R128_BASE( reg ) + reg) - -#define R128_READ(reg) DRM_READ32( (volatile u32 *) R128_ADDR(reg) ) -#define R128_WRITE(reg,val) DRM_WRITE32( (volatile u32 *) R128_ADDR(reg), (val) ) - -#define R128_READ8(reg) DRM_READ8( (volatile u8 *) R128_ADDR(reg) ) -#define R128_WRITE8(reg,val) DRM_WRITE8( (volatile u8 *) R128_ADDR(reg), (val) ) -/* -#define R128_READ(reg) DRM_READ32( dev_priv->mmio, reg ) -#define R128_WRITE(reg,val) DRM_WRITE32( dev_priv->mmio, reg, (val) ) -#define R128_READ8(reg) DRM_READ8( dev_priv->mmio, reg ) -#define R128_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, reg, (val) ) -*/ +#define R128_READ(reg) DRM_READ32( dev_priv->mmio, (reg) ) +#define R128_WRITE(reg,val) DRM_WRITE32( dev_priv->mmio, (reg), (val) ) +#define R128_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) ) +#define R128_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, (reg), (val) ) #define R128_WRITE_PLL(addr,val) \ do { \ @@ -459,7 +449,7 @@ do { \ #if defined(__powerpc__) #define r128_flush_write_combine() (void) GET_RING_HEAD( &dev_priv->ring ) #else -#define r128_flush_write_combine() DRM_WRITEMEMORYBARRIER() +#define r128_flush_write_combine() DRM_WRITEMEMORYBARRIER(dev_priv->ring_rptr) #endif diff --git a/shared/radeon_cp.c b/shared/radeon_cp.c index c0fb63ef..d004b681 100644 --- a/shared/radeon_cp.c +++ b/shared/radeon_cp.c @@ -926,11 +926,11 @@ static void radeon_cp_init_ring_buffer( drm_device_t *dev, RADEON_WRITE( RADEON_SCRATCH_UMSK, 0x7 ); /* Writeback doesn't seem to work everywhere, test it first */ - DRM_WRITE32( &dev_priv->scratch[1], 0 ); + DRM_WRITE32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(1), 0 ); RADEON_WRITE( RADEON_SCRATCH_REG1, 0xdeadbeef ); for ( tmp = 0 ; tmp < dev_priv->usec_timeout ; tmp++ ) { - if ( DRM_READ32( &dev_priv->scratch[1] ) == 0xdeadbeef ) + if ( DRM_READ32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(1) ) == 0xdeadbeef ) break; DRM_UDELAY( 1 ); } @@ -1217,6 +1217,7 @@ static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init ) (dev_priv->ring.size / sizeof(u32)) - 1; dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK; + dev_priv->ring.ring_rptr = dev_priv->ring_rptr; #if __REALLY_HAVE_SG if ( dev_priv->is_pci ) { @@ -1509,7 +1510,7 @@ drm_buf_t *radeon_freelist_get( drm_device_t *dev ) drm_buf_t *buf; int i, t; int start; - u32 done_age = DRM_READ32(&dev_priv->scratch[1]); + u32 done_age = DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1)); if ( ++dev_priv->last_buf >= dma->buf_count ) dev_priv->last_buf = 0; diff --git a/shared/radeon_drv.h b/shared/radeon_drv.h index 9ba86116..882c77fd 100644 --- a/shared/radeon_drv.h +++ b/shared/radeon_drv.h @@ -31,8 +31,8 @@ #ifndef __RADEON_DRV_H__ #define __RADEON_DRV_H__ -#define GET_RING_HEAD(ring) DRM_READ32( (volatile u32 *) (ring)->head ) -#define SET_RING_HEAD(ring,val) DRM_WRITE32( (volatile u32 *) (ring)->head , (val)) +#define GET_RING_HEAD(ring) DRM_READ32( (ring)->ring_rptr, 0 ) /* (ring)->head */ +#define SET_RING_HEAD(ring,val) DRM_WRITE32( (ring)->ring_rptr, 0, (val) ) /* (ring)->head */ typedef struct drm_radeon_freelist { unsigned int age; @@ -53,6 +53,7 @@ typedef struct drm_radeon_ring_buffer { int space; int high_mark; + drm_local_map_t *ring_rptr; } drm_radeon_ring_buffer_t; typedef struct drm_radeon_depth_clear_t { @@ -266,8 +267,10 @@ extern int radeon_emit_irq(drm_device_t *dev); #define RADEON_SCRATCH_UMSK 0x0770 #define RADEON_SCRATCH_ADDR 0x0774 +#define RADEON_SCRATCHOFF( x ) (RADEON_SCRATCH_REG_OFFSET + 4*(x)) + #define GET_SCRATCH( x ) (dev_priv->writeback_works \ - ? DRM_READ32( &dev_priv->scratch[(x)] ) \ + ? DRM_READ32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(x) ) \ : RADEON_READ( RADEON_SCRATCH_REG0 + 4*(x) ) ) @@ -686,23 +689,10 @@ extern int radeon_emit_irq(drm_device_t *dev); #define RADEON_RING_HIGH_MARK 128 - -#define RADEON_BASE(reg) ((unsigned long)(dev_priv->mmio->handle)) -#define RADEON_ADDR(reg) (RADEON_BASE( reg ) + reg) - -#define RADEON_READ(reg) DRM_READ32( (volatile u32 *) RADEON_ADDR(reg) ) -#define RADEON_WRITE(reg,val) DRM_WRITE32( (volatile u32 *) RADEON_ADDR(reg), (val) ) -/* -#define RADEON_READ(reg) DRM_READ32( dev_priv->mmio, reg ) -#define RADEON_WRITE(reg,val) DRM_WRITE32( dev_priv->mmio, reg, (val) ) -*/ - -#define RADEON_READ8(reg) DRM_READ8( (volatile u8 *) RADEON_ADDR(reg) ) -#define RADEON_WRITE8(reg,val) DRM_WRITE8( (volatile u8 *) RADEON_ADDR(reg), (val) ) -/* -#define RADEON_READ8(reg) DRM_READ8( dev_priv->mmio, reg ) -#define RADEON_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, reg, (val) ) -*/ +#define RADEON_READ(reg) DRM_READ32( dev_priv->mmio, (reg) ) +#define RADEON_WRITE(reg,val) DRM_WRITE32( dev_priv->mmio, (reg), (val) ) +#define RADEON_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) ) +#define RADEON_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, (reg), (val) ) #define RADEON_WRITE_PLL( addr, val ) \ do { \ @@ -834,7 +824,7 @@ do { \ #if defined(__powerpc__) #define radeon_flush_write_combine() (void) GET_RING_HEAD( &dev_priv->ring ) #else -#define radeon_flush_write_combine() DRM_WRITEMEMORYBARRIER() +#define radeon_flush_write_combine() DRM_WRITEMEMORYBARRIER( dev_priv->ring_rtpr ) #endif