mirror of
https://gitlab.freedesktop.org/mesa/drm.git
synced 2026-05-17 10:18:10 +02:00
Checking in latest development work - I need to merge the trunk into this
branch so I can work on my Mobility 128 laptop. This code is probably
broken, and may not even compile properly until after the merge is
done.
This commit is contained in:
Gareth Hughes
parent
ce6bb6dc6e
commit
4ca420eac5
10 changed files with 1140 additions and 637 deletions
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@ -35,7 +35,7 @@
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#define R128_NAME "r128"
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#define R128_DESC "ATI Rage 128"
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#define R128_DATE "20000919"
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#define R128_DATE "20000928"
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#define R128_MAJOR 1
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#define R128_MINOR 1
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#define R128_PATCHLEVEL 0
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@ -105,12 +105,16 @@ static drm_ioctl_desc_t r128_ioctls[] = {
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[DRM_IOCTL_NR(DRM_IOCTL_AGP_UNBIND)] = { drm_agp_unbind, 1, 1 },
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#endif
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[DRM_IOCTL_NR(DRM_IOCTL_R128_INIT)] = { r128_init_cce, 1, 1 },
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[DRM_IOCTL_NR(DRM_IOCTL_R128_RESET)] = { r128_eng_reset, 1, 0 },
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[DRM_IOCTL_NR(DRM_IOCTL_R128_FLUSH)] = { r128_eng_flush, 1, 0 },
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[DRM_IOCTL_NR(DRM_IOCTL_R128_PACKET)] = { r128_cce_packet, 1, 0 },
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[DRM_IOCTL_NR(DRM_IOCTL_R128_IDLE)] = { r128_cce_idle, 1, 0 },
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[DRM_IOCTL_NR(DRM_IOCTL_R128_VERTEX)] = { r128_cce_vertex, 1, 0 },
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[DRM_IOCTL_NR(DRM_IOCTL_R128_INIT)] = { r128_cce_init, 1, 1 },
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[DRM_IOCTL_NR(DRM_IOCTL_R128_CCE_START)] = { r128_cce_start, 1, 0 },
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[DRM_IOCTL_NR(DRM_IOCTL_R128_CCE_STOP)] = { r128_cce_stop, 1, 0 },
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[DRM_IOCTL_NR(DRM_IOCTL_R128_CCE_RESET)] = { r128_cce_reset, 1, 0 },
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[DRM_IOCTL_NR(DRM_IOCTL_R128_CCE_IDLE)] = { r128_cce_idle, 1, 0 },
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[DRM_IOCTL_NR(DRM_IOCTL_R128_RESET)] = { r128_engine_reset, 1, 0 },
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[DRM_IOCTL_NR(DRM_IOCTL_R128_SWAP)] = { r128_cce_swap, 1, 0 },
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[DRM_IOCTL_NR(DRM_IOCTL_R128_CLEAR)] = { r128_cce_clear, 1, 0 },
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[DRM_IOCTL_NR(DRM_IOCTL_R128_VERTEX)] = { r128_cce_vertex, 1, 0 },
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[DRM_IOCTL_NR(DRM_IOCTL_R128_PACKET)] = { r128_cce_packet, 1, 0 },
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};
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#define R128_IOCTL_COUNT DRM_ARRAY_SIZE(r128_ioctls)
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22
linux/drm.h
22
linux/drm.h
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@ -11,11 +11,11 @@
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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@ -23,7 +23,7 @@
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*
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*
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* Authors:
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* Rickard E. (Rik) Faith <faith@valinux.com>
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*
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@ -357,11 +357,15 @@ typedef struct drm_agp_info {
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#define DRM_IOCTL_I810_DOCOPY DRM_IO ( 0x48)
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/* Rage 128 specific ioctls */
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#define DRM_IOCTL_R128_INIT DRM_IOW( 0x40, drm_r128_init_t)
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#define DRM_IOCTL_R128_RESET DRM_IO( 0x41)
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#define DRM_IOCTL_R128_FLUSH DRM_IO( 0x42)
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#define DRM_IOCTL_R128_IDLE DRM_IO( 0x43)
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#define DRM_IOCTL_R128_PACKET DRM_IOW( 0x44, drm_r128_packet_t)
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#define DRM_IOCTL_R128_VERTEX DRM_IOW( 0x45, drm_r128_vertex_t)
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#define DRM_IOCTL_R128_INIT DRM_IOW( 0x40, drm_r128_init_t)
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#define DRM_IOCTL_R128_CCE_START DRM_IO( 0x41)
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#define DRM_IOCTL_R128_CCE_STOP DRM_IO( 0x42)
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#define DRM_IOCTL_R128_CCE_RESET DRM_IO( 0x43)
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#define DRM_IOCTL_R128_CCE_IDLE DRM_IO( 0x44)
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#define DRM_IOCTL_R128_RESET DRM_IO( 0x45)
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#define DRM_IOCTL_R128_SWAP DRM_IO( 0x46)
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#define DRM_IOCTL_R128_CLEAR DRM_IOW( 0x47, drm_r128_clear_t)
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#define DRM_IOCTL_R128_VERTEX DRM_IOWR(0x48, drm_r128_vertex_t)
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#define DRM_IOCTL_R128_PACKET DRM_IOWR(0x49, drm_r128_packet_t)
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#endif
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@ -235,7 +235,7 @@ int r128_mapbufs(struct inode *inode, struct file *filp, unsigned int cmd,
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if (dma->flags & _DRM_DMA_USE_AGP) {
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drm_map_t *map;
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map = dev_priv->agp_vertbufs;
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map = dev_priv->vertex_buffers;
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if (!map) {
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retcode = -EINVAL;
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goto done;
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1035
linux/r128_cce.c
1035
linux/r128_cce.c
File diff suppressed because it is too large
Load diff
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@ -51,9 +51,9 @@
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#define R128_UPLOAD_CLIPRECTS 0x200 /* handled client-side */
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#define R128_REQUIRE_QUIESCENCE 0x400
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#define R128_FRONT 0x1
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#define R128_BACK 0x2
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#define R128_DEPTH 0x4
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#define R128_FRONT 0x1
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#define R128_BACK 0x2
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#define R128_DEPTH 0x4
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/* Keep these small for testing.
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*/
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@ -140,7 +140,6 @@ typedef struct drm_r128_sarea {
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drm_tex_region_t tex_list[R128_NR_TEX_HEAPS][R128_NR_TEX_REGIONS+1];
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int tex_age[R128_NR_TEX_HEAPS];
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int ctx_owner;
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int ring_write;
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} drm_r128_sarea_t;
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@ -155,24 +154,35 @@ typedef struct drm_r128_init {
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int sarea_priv_offset;
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int is_pci;
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int cce_mode;
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int cce_fifo_size;
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int cce_secure;
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int ring_size;
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int usec_timeout;
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int fb_offset;
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int agp_ring_offset;
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int agp_read_ptr_offset;
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int agp_vertbufs_offset;
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int agp_indbufs_offset;
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int agp_textures_offset;
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int mmio_offset;
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unsigned int fb_bpp;
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unsigned int front_offset, front_pitch;
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unsigned int front_x, front_y;
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unsigned int back_offset, back_pitch;
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unsigned int back_x, back_y;
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unsigned int depth_bpp;
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unsigned int depth_offset, depth_pitch;
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unsigned int depth_x, depth_y;
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unsigned int fb_offset;
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unsigned int mmio_offset;
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unsigned int ring_offset;
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unsigned int ring_rptr_offset;
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unsigned int vertex_buffers_offset;
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unsigned int indirect_buffers_offset;
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unsigned int agp_textures_offset;
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} drm_r128_init_t;
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typedef struct drm_r128_clear {
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unsigned int flags;
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int x, y, w, h;
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unsigned int clear_color;
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unsigned int clear_depth;
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unsigned int flags;
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unsigned int color_mask;
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unsigned int depth_mask;
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} drm_r128_clear_t;
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typedef struct drm_r128_vertex {
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@ -35,7 +35,7 @@
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#define R128_NAME "r128"
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#define R128_DESC "ATI Rage 128"
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#define R128_DATE "20000919"
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#define R128_DATE "20000928"
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#define R128_MAJOR 1
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#define R128_MINOR 1
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#define R128_PATCHLEVEL 0
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@ -105,12 +105,16 @@ static drm_ioctl_desc_t r128_ioctls[] = {
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[DRM_IOCTL_NR(DRM_IOCTL_AGP_UNBIND)] = { drm_agp_unbind, 1, 1 },
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#endif
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[DRM_IOCTL_NR(DRM_IOCTL_R128_INIT)] = { r128_init_cce, 1, 1 },
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[DRM_IOCTL_NR(DRM_IOCTL_R128_RESET)] = { r128_eng_reset, 1, 0 },
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[DRM_IOCTL_NR(DRM_IOCTL_R128_FLUSH)] = { r128_eng_flush, 1, 0 },
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[DRM_IOCTL_NR(DRM_IOCTL_R128_PACKET)] = { r128_cce_packet, 1, 0 },
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[DRM_IOCTL_NR(DRM_IOCTL_R128_IDLE)] = { r128_cce_idle, 1, 0 },
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[DRM_IOCTL_NR(DRM_IOCTL_R128_VERTEX)] = { r128_cce_vertex, 1, 0 },
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[DRM_IOCTL_NR(DRM_IOCTL_R128_INIT)] = { r128_cce_init, 1, 1 },
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[DRM_IOCTL_NR(DRM_IOCTL_R128_CCE_START)] = { r128_cce_start, 1, 0 },
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[DRM_IOCTL_NR(DRM_IOCTL_R128_CCE_STOP)] = { r128_cce_stop, 1, 0 },
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[DRM_IOCTL_NR(DRM_IOCTL_R128_CCE_RESET)] = { r128_cce_reset, 1, 0 },
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[DRM_IOCTL_NR(DRM_IOCTL_R128_CCE_IDLE)] = { r128_cce_idle, 1, 0 },
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[DRM_IOCTL_NR(DRM_IOCTL_R128_RESET)] = { r128_engine_reset, 1, 0 },
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[DRM_IOCTL_NR(DRM_IOCTL_R128_SWAP)] = { r128_cce_swap, 1, 0 },
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[DRM_IOCTL_NR(DRM_IOCTL_R128_CLEAR)] = { r128_cce_clear, 1, 0 },
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[DRM_IOCTL_NR(DRM_IOCTL_R128_VERTEX)] = { r128_cce_vertex, 1, 0 },
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[DRM_IOCTL_NR(DRM_IOCTL_R128_PACKET)] = { r128_cce_packet, 1, 0 },
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};
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#define R128_IOCTL_COUNT DRM_ARRAY_SIZE(r128_ioctls)
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323
linux/r128_drv.h
323
linux/r128_drv.h
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@ -29,105 +29,119 @@
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*
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*/
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#ifndef _R128_DRV_H_
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#define _R128_DRV_H_
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#ifndef __R128_DRV_H__
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#define __R128_DRV_H__
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typedef struct drm_r128_freelist {
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unsigned int age;
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drm_buf_t *buf;
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unsigned int age;
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drm_buf_t *buf;
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struct drm_r128_freelist *next;
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struct drm_r128_freelist *prev;
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} drm_r128_freelist_t;
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typedef struct drm_r128_ring_buffer {
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__volatile__ u32 *read_ptr;
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u32 *start;
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u32 *end;
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int size;
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int size_l2qw;
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u32 start;
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u32 end;
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int size;
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int size_l2qw;
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u32 *virtual_start;
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int head;
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int tail;
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u32 tail_mask;
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int space;
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volatile u32 *head;
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u32 tail;
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u32 tail_mask;
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int space;
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} drm_r128_ring_buffer_t;
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typedef struct drm_r128_private {
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__volatile__ u32 *ring_read_ptr;
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drm_r128_ring_buffer_t ring;
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drm_r128_sarea_t *sarea_priv;
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u32 *ring_start;
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u32 *ring_end;
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int ring_size;
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int ring_sizel2qw;
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int ring_entries;
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int cce_mode;
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int cce_fifo_size;
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int cce_is_bm_mode;
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int cce_secure;
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u32 *cce_buffer;
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int cce_mode;
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int cce_fifo_size;
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int cce_secure;
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int cce_running;
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drm_r128_freelist_t *head;
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drm_r128_freelist_t *tail;
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unsigned int submit_age;
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unsigned int submit_age;
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int usec_timeout;
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int is_pci;
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int usec_timeout;
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int is_pci;
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drm_map_t *sarea;
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drm_map_t *fb;
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drm_map_t *agp_ring;
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drm_map_t *agp_read_ptr;
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drm_map_t *agp_vertbufs;
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drm_map_t *agp_indbufs;
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drm_map_t *agp_textures;
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drm_map_t *mmio;
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unsigned int fb_bpp;
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unsigned int front_offset;
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unsigned int front_pitch;
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unsigned int front_x;
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unsigned int front_y;
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unsigned int back_offset;
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unsigned int back_pitch;
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unsigned int back_x;
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unsigned int back_y;
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unsigned int depth_bpp;
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unsigned int depth_offset;
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unsigned int depth_pitch;
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unsigned int depth_x;
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unsigned int depth_y;
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drm_map_t *sarea;
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drm_map_t *fb;
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drm_map_t *mmio;
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drm_map_t *cce_ring;
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drm_map_t *ring_rptr;
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drm_map_t *vertex_buffers;
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drm_map_t *indirect_buffers;
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drm_map_t *agp_textures;
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} drm_r128_private_t;
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typedef struct drm_r128_buf_priv {
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u32 age;
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int discard;
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int dispatched;
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u32 age;
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int discard;
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int dispatched;
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drm_r128_freelist_t *my_freelist;
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} drm_r128_buf_priv_t;
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/* r128_drv.c */
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extern int r128_version(struct inode *inode, struct file *filp,
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unsigned int cmd, unsigned long arg);
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extern int r128_open(struct inode *inode, struct file *filp);
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extern int r128_release(struct inode *inode, struct file *filp);
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extern int r128_ioctl(struct inode *inode, struct file *filp,
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unsigned int cmd, unsigned long arg);
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extern int r128_lock(struct inode *inode, struct file *filp,
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unsigned int cmd, unsigned long arg);
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extern int r128_unlock(struct inode *inode, struct file *filp,
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unsigned int cmd, unsigned long arg);
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extern int r128_version( struct inode *inode, struct file *filp,
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unsigned int cmd, unsigned long arg );
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extern int r128_open( struct inode *inode, struct file *filp );
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extern int r128_release( struct inode *inode, struct file *filp );
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extern int r128_ioctl( struct inode *inode, struct file *filp,
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unsigned int cmd, unsigned long arg );
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extern int r128_lock( struct inode *inode, struct file *filp,
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unsigned int cmd, unsigned long arg );
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extern int r128_unlock( struct inode *inode, struct file *filp,
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unsigned int cmd, unsigned long arg );
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/* r128_dma.c */
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extern int r128_init_cce(struct inode *inode, struct file *filp,
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unsigned int cmd, unsigned long arg);
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extern int r128_eng_reset(struct inode *inode, struct file *filp,
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unsigned int cmd, unsigned long arg);
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extern int r128_eng_flush(struct inode *inode, struct file *filp,
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unsigned int cmd, unsigned long arg);
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extern int r128_cce_packet(struct inode *inode, struct file *filp,
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unsigned int cmd, unsigned long arg);
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extern int r128_cce_idle(struct inode *inode, struct file *filp,
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unsigned int cmd, unsigned long arg);
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/* r128_cce.c */
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extern int r128_cce_init( struct inode *inode, struct file *filp,
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unsigned int cmd, unsigned long arg );
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extern int r128_cce_start( struct inode *inode, struct file *filp,
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unsigned int cmd, unsigned long arg );
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extern int r128_cce_stop( struct inode *inode, struct file *filp,
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unsigned int cmd, unsigned long arg );
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extern int r128_cce_reset( struct inode *inode, struct file *filp,
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unsigned int cmd, unsigned long arg );
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extern int r128_cce_idle( struct inode *inode, struct file *filp,
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unsigned int cmd, unsigned long arg );
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extern int r128_engine_reset( struct inode *inode, struct file *filp,
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unsigned int cmd, unsigned long arg );
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extern int r128_cce_packet( struct inode *inode, struct file *filp,
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unsigned int cmd, unsigned long arg );
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extern void r128_flush_write_combine( void );
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extern int r128_do_wait_for_idle( drm_r128_private_t *dev_priv );
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extern int r128_do_submit_packet( drm_r128_private_t *dev_priv,
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u32 *buffer, int count );
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extern void r128_freelist_reset( drm_device_t *dev );
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extern drm_buf_t *r128_freelist_get( drm_device_t *dev );
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extern int r128_wait_ring( drm_r128_private_t *dev_priv, int n );
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extern void r128_update_ring_snapshot( drm_r128_private_t *dev_priv );
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/* r128_state.c */
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extern int r128_cce_vertex(struct inode *inode, struct file *filp,
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unsigned int cmd, unsigned long arg);
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extern int r128_cce_clear( struct inode *inode, struct file *filp,
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unsigned int cmd, unsigned long arg );
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extern int r128_cce_swap( struct inode *inode, struct file *filp,
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unsigned int cmd, unsigned long arg );
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extern int r128_cce_vertex( struct inode *inode, struct file *filp,
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unsigned int cmd, unsigned long arg );
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/* r128_bufs.c */
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extern int r128_addbufs(struct inode *inode, struct file *filp,
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|
@ -182,12 +196,29 @@ extern int r128_context_switch_complete(drm_device_t *dev, int new);
|
|||
#define R128_AUX3_SC_TOP 0x168c
|
||||
#define R128_AUX3_SC_BOTTOM 0x1690
|
||||
|
||||
#define R128_BUS_CNTL 0x0030
|
||||
# define R128_BUS_MASTER_DIS (1 << 6)
|
||||
|
||||
#define R128_CLOCK_CNTL_INDEX 0x0008
|
||||
#define R128_CLOCK_CNTL_DATA 0x000c
|
||||
# define R128_PLL_WR_EN (1 << 7)
|
||||
|
||||
#define R128_CONSTANT_COLOR_C 0x1d34
|
||||
|
||||
#define R128_DP_GUI_MASTER_CNTL 0x146c
|
||||
# define R128_GMC_BRUSH_SOLID_COLOR (13 << 4)
|
||||
# define R128_GMC_BRUSH_NONE (15 << 4)
|
||||
# define R128_GMC_DST_16BPP (4 << 8)
|
||||
# define R128_GMC_DST_24BPP (5 << 8)
|
||||
# define R128_GMC_DST_32BPP (6 << 8)
|
||||
# define R128_GMC_SRC_DATATYPE_COLOR (3 << 12)
|
||||
# define R128_DP_SRC_SOURCE_MEMORY (2 << 24)
|
||||
# define R128_DP_SRC_SOURCE_HOST_DATA (3 << 24)
|
||||
# define R128_GMC_CLR_CMP_CNTL_DIS (1 << 28)
|
||||
# define R128_GMC_AUX_CLIP_DIS (1 << 29)
|
||||
# define R128_GMC_WR_MSK_DIS (1 << 30)
|
||||
# define R128_ROP3_S 0x00cc0000
|
||||
# define R128_ROP3_P 0x00f00000
|
||||
#define R128_DP_WRITE_MASK 0x16cc
|
||||
#define R128_DST_PITCH_OFFSET_C 0x1c80
|
||||
|
||||
|
|
@ -214,36 +245,6 @@ extern int r128_context_switch_complete(drm_device_t *dev, int new);
|
|||
# define R128_PC_FLUSH_ALL 0x00ff
|
||||
# define R128_PC_BUSY (1 << 31)
|
||||
|
||||
#define R128_PM4_BUFFER_CNTL 0x0704
|
||||
# define R128_PM4_NONPM4 (0 << 28)
|
||||
# define R128_PM4_192PIO (1 << 28)
|
||||
# define R128_PM4_192BM (2 << 28)
|
||||
# define R128_PM4_128PIO_64INDBM (3 << 28)
|
||||
# define R128_PM4_128BM_64INDBM (4 << 28)
|
||||
# define R128_PM4_64PIO_128INDBM (5 << 28)
|
||||
# define R128_PM4_64BM_128INDBM (6 << 28)
|
||||
# define R128_PM4_64PIO_64VCBM_64INDBM (7 << 28)
|
||||
# define R128_PM4_64BM_64VCBM_64INDBM (8 << 28)
|
||||
# define R128_PM4_64PIO_64VCPIO_64INDPIO (15 << 28)
|
||||
|
||||
#define R128_PM4_BUFFER_DL_RPTR 0x0710
|
||||
#define R128_PM4_BUFFER_DL_WPTR 0x0714
|
||||
# define R128_PM4_BUFFER_DL_DONE (1 << 31)
|
||||
|
||||
#define R128_PM4_VC_FPU_SETUP 0x071c
|
||||
|
||||
#define R128_PM4_STAT 0x07b8
|
||||
# define R128_PM4_FIFOCNT_MASK 0x0fff
|
||||
# define R128_PM4_BUSY (1 << 16)
|
||||
# define R128_PM4_GUI_ACTIVE (1 << 31)
|
||||
|
||||
#define R128_PM4_BUFFER_ADDR 0x07f0
|
||||
#define R128_PM4_MICRO_CNTL 0x07fc
|
||||
# define R128_PM4_MICRO_FREERUN (1 << 30)
|
||||
|
||||
#define R128_PM4_FIFO_DATA_EVEN 0x1000
|
||||
#define R128_PM4_FIFO_DATA_ODD 0x1004
|
||||
|
||||
#define R128_PRIM_TEX_CNTL_C 0x1cb0
|
||||
|
||||
#define R128_SCALE_3D_CNTL 0x1a00
|
||||
|
|
@ -258,12 +259,62 @@ extern int r128_context_switch_complete(drm_device_t *dev, int new);
|
|||
#define R128_WINDOW_XY_OFFSET 0x1bcc
|
||||
|
||||
|
||||
/* CCE registers
|
||||
*/
|
||||
#define R128_PM4_BUFFER_OFFSET 0x0700
|
||||
#define R128_PM4_BUFFER_CNTL 0x0704
|
||||
# define R128_PM4_MASK (15 << 28)
|
||||
# define R128_PM4_NONPM4 (0 << 28)
|
||||
# define R128_PM4_192PIO (1 << 28)
|
||||
# define R128_PM4_192BM (2 << 28)
|
||||
# define R128_PM4_128PIO_64INDBM (3 << 28)
|
||||
# define R128_PM4_128BM_64INDBM (4 << 28)
|
||||
# define R128_PM4_64PIO_128INDBM (5 << 28)
|
||||
# define R128_PM4_64BM_128INDBM (6 << 28)
|
||||
# define R128_PM4_64PIO_64VCBM_64INDBM (7 << 28)
|
||||
# define R128_PM4_64BM_64VCBM_64INDBM (8 << 28)
|
||||
# define R128_PM4_64PIO_64VCPIO_64INDPIO (15 << 28)
|
||||
|
||||
#define R128_PM4_BUFFER_WM_CNTL 0x0708
|
||||
# define R128_WMA_SHIFT 0
|
||||
# define R128_WMB_SHIFT 8
|
||||
# define R128_WMC_SHIFT 16
|
||||
# define R128_WB_WM_SHIFT 24
|
||||
|
||||
#define R128_PM4_BUFFER_DL_RPTR_ADDR 0x070c
|
||||
#define R128_PM4_BUFFER_DL_RPTR 0x0710
|
||||
#define R128_PM4_BUFFER_DL_WPTR 0x0714
|
||||
# define R128_PM4_BUFFER_DL_DONE (1 << 31)
|
||||
|
||||
#define R128_PM4_VC_FPU_SETUP 0x071c
|
||||
|
||||
#define R128_PM4_STAT 0x07b8
|
||||
# define R128_PM4_FIFOCNT_MASK 0x0fff
|
||||
# define R128_PM4_BUSY (1 << 16)
|
||||
# define R128_PM4_GUI_ACTIVE (1 << 31)
|
||||
|
||||
#define R128_PM4_MICROCODE_ADDR 0x07d4
|
||||
#define R128_PM4_MICROCODE_RADDR 0x07d8
|
||||
#define R128_PM4_MICROCODE_DATAH 0x07dc
|
||||
#define R128_PM4_MICROCODE_DATAL 0x07e0
|
||||
|
||||
#define R128_PM4_BUFFER_ADDR 0x07f0
|
||||
#define R128_PM4_MICRO_CNTL 0x07fc
|
||||
# define R128_PM4_MICRO_FREERUN (1 << 30)
|
||||
|
||||
#define R128_PM4_FIFO_DATA_EVEN 0x1000
|
||||
#define R128_PM4_FIFO_DATA_ODD 0x1004
|
||||
|
||||
|
||||
/* CCE command packets
|
||||
*/
|
||||
#define R128_CCE_PACKET0 0x00000000
|
||||
#define R128_CCE_PACKET1 0x40000000
|
||||
#define R128_CCE_PACKET2 0x80000000
|
||||
#define R128_CCE_PACKET3 0xC0000000
|
||||
# define R128_CNTL_HOSTDATA_BLT 0x00009400
|
||||
# define R128_CNTL_PAINT_MULTI 0x00009A00
|
||||
# define R128_CNTL_BITBLT_MULTI 0x00009B00
|
||||
# define R128_3D_RNDR_GEN_INDX_PRIM 0x00002300
|
||||
|
||||
#define R128_CCE_PACKET_MASK 0xC0000000
|
||||
|
|
@ -285,6 +336,13 @@ extern int r128_context_switch_complete(drm_device_t *dev, int new);
|
|||
#define R128_CCE_VC_CNTL_PRIM_WALK_RING 0x00000030
|
||||
#define R128_CCE_VC_CNTL_NUM_SHIFT 16
|
||||
|
||||
/* Constants */
|
||||
#define R128_AGP_OFFSET 0x02000000
|
||||
|
||||
#define R128_WATERMARK_L 16
|
||||
#define R128_WATERMARK_M 8
|
||||
#define R128_WATERMARK_N 8
|
||||
#define R128_WATERMARK_K 128
|
||||
|
||||
#define R128_MAX_USEC_TIMEOUT 100000 /* 100 ms */
|
||||
|
||||
|
|
@ -328,77 +386,44 @@ extern int R128_READ_PLL(drm_device_t *dev, int addr);
|
|||
(pkt) | ((n) << 16))
|
||||
|
||||
|
||||
#define r128_flush_write_combine() mb()
|
||||
|
||||
|
||||
#define R128_VERBOSE 0
|
||||
|
||||
#if 0
|
||||
|
||||
#define RING_LOCALS unsigned long outring, ringmask; volatile u32 *virt;
|
||||
#define RING_LOCALS int write; unsigned int mask; volatile u32 *ring;
|
||||
|
||||
#define BEGIN_RING( n ) do { \
|
||||
if ( R128_VERBOSE ) { \
|
||||
DRM_DEBUG( "BEGIN_RING( %d ) in %s\n", \
|
||||
DRM_INFO( "BEGIN_RING( %d ) in %s\n", \
|
||||
n, __FUNCTION__ ); \
|
||||
} \
|
||||
if ( dev_priv->ring.space < n * sizeof(u32) ) { \
|
||||
r128_wait_ring( dev_priv, n * sizeof(u32) ); \
|
||||
} \
|
||||
dev_priv->ring.space -= n * sizeof(u32); \
|
||||
outring = dev_priv->ring.tail; \
|
||||
ringmask = dev_priv->ring.tail_mask; \
|
||||
virt = dev_priv->->ring.virtual_start; \
|
||||
write = dev_priv->ring.tail; \
|
||||
mask = dev_priv->ring.tail_mask; \
|
||||
ring = dev_priv->ring.start; \
|
||||
} while (0)
|
||||
|
||||
#define ADVANCE_RING() do { \
|
||||
if ( R128_VERBOSE ) { \
|
||||
DRM_DEBUG( "ADVANCE_RING()\n" ); \
|
||||
} \
|
||||
dev_priv->sarea_priv->ring_write = write;
|
||||
R128_WRITE( R128_PM4_BUFFER_DL_WPTR, write );
|
||||
__ret = r128_do_submit_packet( dev_priv, buffer, outring ); \
|
||||
if ( __ret < 0 ) { \
|
||||
DRM_ERROR( "ADVANCE_RING fucked up!\n" ); \
|
||||
DRM_INFO( "ADVANCE_RING() tail=0x%06x wr=0x%06x\n", \
|
||||
write, dev_priv->ring.tail ); \
|
||||
} \
|
||||
r128_flush_write_combine(); \
|
||||
dev_priv->ring.tail = write; \
|
||||
R128_WRITE( R128_PM4_BUFFER_DL_WPTR, write ); \
|
||||
} while (0)
|
||||
|
||||
#define OUT_RING( x ) do { \
|
||||
if ( R128_VERBOSE ) { \
|
||||
DRM_DEBUG( " OUT_RING( 0x%08x )\n", \
|
||||
(unsigned int)(x) ); \
|
||||
DRM_INFO( " OUT_RING( 0x%08x ) at 0x%x\n", \
|
||||
(unsigned int)(x), write ); \
|
||||
} \
|
||||
buffer[outring++] = x; \
|
||||
ring[write++] = x; \
|
||||
write &= mask; \
|
||||
} while (0)
|
||||
|
||||
#else
|
||||
|
||||
#define RING_LOCALS unsigned long outring; u32 *buffer; int __ret;
|
||||
|
||||
#define BEGIN_RING( n ) do { \
|
||||
if ( R128_VERBOSE ) { \
|
||||
DRM_DEBUG( "BEGIN_RING( %d ) in %s\n", \
|
||||
n, __FUNCTION__ ); \
|
||||
} \
|
||||
outring = 0; \
|
||||
buffer = dev_priv->cce_buffer; \
|
||||
} while (0)
|
||||
|
||||
#define ADVANCE_RING() do { \
|
||||
if ( R128_VERBOSE ) { \
|
||||
DRM_DEBUG( "ADVANCE_RING()\n" ); \
|
||||
} \
|
||||
__ret = r128_do_submit_packet( dev_priv, buffer, outring ); \
|
||||
if ( __ret < 0 ) { \
|
||||
DRM_ERROR( "ADVANCE_RING fucked up!\n" ); \
|
||||
} \
|
||||
} while (0)
|
||||
|
||||
#define OUT_RING( x ) do { \
|
||||
if ( R128_VERBOSE ) { \
|
||||
DRM_DEBUG( " OUT_RING( 0x%08x )\n", \
|
||||
(unsigned int)(x) ); \
|
||||
} \
|
||||
buffer[outring++] = x; \
|
||||
} while (0)
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
#endif /* __R128_DRV_H__ */
|
||||
|
|
|
|||
|
|
@ -181,7 +181,7 @@ static inline void r128_emit_tex0( drm_r128_private_t *dev_priv )
|
|||
RING_LOCALS;
|
||||
DRM_DEBUG( " %s\n", __FUNCTION__ );
|
||||
|
||||
BEGIN_RING( 3 );
|
||||
BEGIN_RING( 7 + R128_TEX_MAXLEVELS );
|
||||
|
||||
OUT_RING( CCE_PACKET0( R128_PRIM_TEX_CNTL_C,
|
||||
2 + R128_TEX_MAXLEVELS ) );
|
||||
|
|
@ -207,7 +207,7 @@ static inline void r128_emit_tex1( drm_r128_private_t *dev_priv )
|
|||
RING_LOCALS;
|
||||
DRM_DEBUG( " %s\n", __FUNCTION__ );
|
||||
|
||||
BEGIN_RING( 3 );
|
||||
BEGIN_RING( 5 + R128_TEX_MAXLEVELS );
|
||||
|
||||
OUT_RING( CCE_PACKET0( R128_SEC_TEX_CNTL_C,
|
||||
1 + R128_TEX_MAXLEVELS ) );
|
||||
|
|
@ -274,16 +274,214 @@ static inline void r128_emit_state( drm_r128_private_t *dev_priv )
|
|||
* CCE command dispatch functions
|
||||
*/
|
||||
|
||||
static void r128_cce_dispatch_swap( drm_device_t *dev )
|
||||
static void r128_print_dirty( const char *msg, unsigned int flags )
|
||||
{
|
||||
|
||||
DRM_INFO( "%s: (0x%x) %s%s%s%s%s%s%s%s%s\n",
|
||||
msg,
|
||||
flags,
|
||||
(flags & R128_UPLOAD_CORE) ? "core, " : "",
|
||||
(flags & R128_UPLOAD_CONTEXT) ? "context, " : "",
|
||||
(flags & R128_UPLOAD_SETUP) ? "setup, " : "",
|
||||
(flags & R128_UPLOAD_TEX0) ? "tex0, " : "",
|
||||
(flags & R128_UPLOAD_TEX1) ? "tex1, " : "",
|
||||
(flags & R128_UPLOAD_MASKS) ? "masks, " : "",
|
||||
(flags & R128_UPLOAD_WINDOW) ? "window, " : "",
|
||||
(flags & R128_UPLOAD_CLIPRECTS) ? "cliprects, " : "",
|
||||
(flags & R128_REQUIRE_QUIESCENCE) ? "quiescence, " : "" );
|
||||
}
|
||||
|
||||
static void r128_cce_dispatch_clear( drm_device_t *dev, int flags,
|
||||
static void r128_cce_dispatch_clear( drm_device_t *dev,
|
||||
unsigned int flags,
|
||||
int cx, int cy, int cw, int ch,
|
||||
unsigned int clear_color,
|
||||
unsigned int clear_depth )
|
||||
unsigned int clear_depth,
|
||||
unsigned int color_mask,
|
||||
unsigned int depth_mask )
|
||||
{
|
||||
drm_r128_private_t *dev_priv = dev->dev_private;
|
||||
drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
|
||||
int nbox = sarea_priv->nbox;
|
||||
drm_clip_rect_t *pbox = sarea_priv->boxes;
|
||||
u32 fb_bpp, depth_bpp;
|
||||
int i;
|
||||
RING_LOCALS;
|
||||
DRM_DEBUG( "%s\n", __FUNCTION__ );
|
||||
|
||||
switch ( dev_priv->fb_bpp ) {
|
||||
case 16:
|
||||
fb_bpp = R128_GMC_DST_16BPP;
|
||||
break;
|
||||
case 24:
|
||||
fb_bpp = R128_GMC_DST_24BPP;
|
||||
break;
|
||||
case 32:
|
||||
default:
|
||||
fb_bpp = R128_GMC_DST_32BPP;
|
||||
break;
|
||||
}
|
||||
switch ( dev_priv->depth_bpp ) {
|
||||
case 16:
|
||||
depth_bpp = R128_GMC_DST_16BPP;
|
||||
break;
|
||||
case 24:
|
||||
depth_bpp = R128_GMC_DST_32BPP;
|
||||
break;
|
||||
case 32:
|
||||
depth_bpp = R128_GMC_DST_32BPP;
|
||||
break;
|
||||
default:
|
||||
return;
|
||||
}
|
||||
|
||||
for ( i = 0 ; i < nbox ; i++ ) {
|
||||
int x = pbox[i].x1;
|
||||
int y = pbox[i].y1;
|
||||
int w = pbox[i].x2 - x;
|
||||
int h = pbox[i].y2 - y;
|
||||
|
||||
DRM_DEBUG( "dispatch clear %d,%d-%d,%d flags 0x%x\n",
|
||||
pbox[i].x1, pbox[i].y1, pbox[i].x2,
|
||||
pbox[i].y2, flags );
|
||||
|
||||
if ( flags & (R128_FRONT | R128_BACK) ) {
|
||||
BEGIN_RING( 7 );
|
||||
|
||||
OUT_RING( CCE_PACKET0( R128_DP_WRITE_MASK, 0 ) );
|
||||
OUT_RING( color_mask );
|
||||
|
||||
ADVANCE_RING();
|
||||
}
|
||||
|
||||
if ( flags & R128_FRONT ) {
|
||||
int fx = x + dev_priv->front_x;
|
||||
int fy = y + dev_priv->front_y;
|
||||
|
||||
DRM_DEBUG( "clear front\n");
|
||||
BEGIN_RING( 5 );
|
||||
|
||||
OUT_RING( CCE_PACKET3( R128_CNTL_PAINT_MULTI, 3 ) );
|
||||
OUT_RING( R128_GMC_BRUSH_SOLID_COLOR
|
||||
| fb_bpp
|
||||
| R128_GMC_SRC_DATATYPE_COLOR
|
||||
| R128_ROP3_P
|
||||
| R128_GMC_CLR_CMP_CNTL_DIS
|
||||
| R128_GMC_AUX_CLIP_DIS );
|
||||
OUT_RING( clear_color );
|
||||
OUT_RING( (fx << 16) | fy );
|
||||
OUT_RING( (w << 16) | h );
|
||||
|
||||
ADVANCE_RING();
|
||||
}
|
||||
|
||||
if ( flags & R128_BACK ) {
|
||||
int bx = x + dev_priv->back_x;
|
||||
int by = y + dev_priv->back_y;
|
||||
|
||||
DRM_DEBUG( "clear back\n" );
|
||||
BEGIN_RING( 5 );
|
||||
|
||||
OUT_RING( CCE_PACKET3( R128_CNTL_PAINT_MULTI, 3 ) );
|
||||
OUT_RING( R128_GMC_BRUSH_SOLID_COLOR
|
||||
| fb_bpp
|
||||
| R128_GMC_SRC_DATATYPE_COLOR
|
||||
| R128_ROP3_P
|
||||
| R128_GMC_CLR_CMP_CNTL_DIS
|
||||
| R128_GMC_AUX_CLIP_DIS );
|
||||
OUT_RING( clear_color );
|
||||
OUT_RING( (bx << 16) | by );
|
||||
OUT_RING( (w << 16) | h );
|
||||
|
||||
ADVANCE_RING();
|
||||
}
|
||||
|
||||
if ( flags & R128_DEPTH ) {
|
||||
int dx = x + dev_priv->depth_x;
|
||||
int dy = y + dev_priv->depth_y;
|
||||
|
||||
DRM_DEBUG( "clear depth\n" );
|
||||
BEGIN_RING( 7 );
|
||||
|
||||
OUT_RING( CCE_PACKET0( R128_DP_WRITE_MASK, 0 ) );
|
||||
OUT_RING( depth_mask );
|
||||
|
||||
OUT_RING( CCE_PACKET3( R128_CNTL_PAINT_MULTI, 3 ) );
|
||||
OUT_RING( R128_GMC_BRUSH_SOLID_COLOR
|
||||
| depth_bpp
|
||||
| R128_GMC_SRC_DATATYPE_COLOR
|
||||
| R128_ROP3_P
|
||||
| R128_GMC_CLR_CMP_CNTL_DIS
|
||||
| R128_GMC_AUX_CLIP_DIS );
|
||||
OUT_RING( clear_depth );
|
||||
OUT_RING( (dx << 16) | dy );
|
||||
OUT_RING( (w << 16) | h );
|
||||
|
||||
ADVANCE_RING();
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static void r128_cce_dispatch_swap( drm_device_t *dev )
|
||||
{
|
||||
drm_r128_private_t *dev_priv = dev->dev_private;
|
||||
drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
|
||||
int nbox = sarea_priv->nbox;
|
||||
drm_clip_rect_t *pbox = sarea_priv->boxes;
|
||||
u32 fb_bpp;
|
||||
int i;
|
||||
RING_LOCALS;
|
||||
DRM_INFO( "%s\n", __FUNCTION__ );
|
||||
|
||||
switch ( dev_priv->fb_bpp ) {
|
||||
case 16:
|
||||
fb_bpp = R128_GMC_DST_16BPP;
|
||||
break;
|
||||
case 24:
|
||||
fb_bpp = R128_GMC_DST_24BPP;
|
||||
break;
|
||||
case 32:
|
||||
default:
|
||||
fb_bpp = R128_GMC_DST_32BPP;
|
||||
break;
|
||||
}
|
||||
|
||||
for ( i = 0 ; i < nbox ; i++ ) {
|
||||
int fx = pbox[i].x1;
|
||||
int fy = pbox[i].y1;
|
||||
int fw = pbox[i].x2 - fx;
|
||||
int fh = pbox[i].y2 - fy;
|
||||
int bx = fx + dev_priv->back_x;
|
||||
int by = fy + dev_priv->back_y;
|
||||
|
||||
fx += dev_priv->front_x;
|
||||
fy += dev_priv->front_x;
|
||||
|
||||
BEGIN_RING( 5 );
|
||||
|
||||
OUT_RING( CCE_PACKET3( R128_CNTL_BITBLT_MULTI, 3 ) );
|
||||
OUT_RING( R128_GMC_BRUSH_NONE
|
||||
| R128_GMC_SRC_DATATYPE_COLOR
|
||||
| R128_DP_SRC_SOURCE_MEMORY
|
||||
| fb_bpp
|
||||
| R128_ROP3_S
|
||||
| R128_GMC_CLR_CMP_CNTL_DIS
|
||||
| R128_GMC_AUX_CLIP_DIS
|
||||
| R128_GMC_WR_MSK_DIS );
|
||||
|
||||
OUT_RING( (bx << 16) | by );
|
||||
OUT_RING( (fx << 16) | fy );
|
||||
OUT_RING( (fw << 16) | fh );
|
||||
|
||||
ADVANCE_RING();
|
||||
}
|
||||
|
||||
#if 0
|
||||
BEGIN_RING( 2 );
|
||||
|
||||
OUT_RING( CCE_PACKET0( R128_SWAP_AGE_REG, 0 ) );
|
||||
OUT_RING( r128ctx->lastSwapAge );
|
||||
|
||||
ADVANCE_RING();
|
||||
#endif
|
||||
}
|
||||
|
||||
static void r128_cce_dispatch_vertex( drm_device_t *dev,
|
||||
|
|
@ -295,7 +493,7 @@ static void r128_cce_dispatch_vertex( drm_device_t *dev,
|
|||
int vertsize = sarea_priv->vertsize;
|
||||
int format = sarea_priv->vc_format;
|
||||
int index = buf->idx;
|
||||
int offset = dev_priv->agp_vertbufs->offset
|
||||
int offset = dev_priv->vertex_buffers->offset
|
||||
+ buf->offset - dev->agp->base;
|
||||
int size = buf->used / (vertsize * sizeof(u32));
|
||||
int prim;
|
||||
|
|
@ -309,6 +507,11 @@ static void r128_cce_dispatch_vertex( drm_device_t *dev,
|
|||
DRM_DEBUG( "vertex size = %d\n", vertsize );
|
||||
DRM_DEBUG( "vertex format = 0x%x\n", format );
|
||||
|
||||
r128_update_ring_snapshot( dev_priv );
|
||||
|
||||
if ( 0 )
|
||||
r128_print_dirty( "dispatch_vertex", sarea_priv->dirty );
|
||||
|
||||
prim = R128_CCE_VC_CNTL_PRIM_TYPE_TRI_LIST;
|
||||
|
||||
if ( buf->used ) {
|
||||
|
|
@ -389,6 +592,68 @@ static void r128_get_vertex_buffer( drm_device_t *dev, drm_r128_vertex_t *v )
|
|||
v->granted = 1;
|
||||
}
|
||||
|
||||
int r128_cce_clear( struct inode *inode, struct file *filp,
|
||||
unsigned int cmd, unsigned long arg )
|
||||
{
|
||||
drm_file_t *priv = filp->private_data;
|
||||
drm_device_t *dev = priv->dev;
|
||||
drm_r128_private_t *dev_priv = dev->dev_private;
|
||||
drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
|
||||
drm_r128_clear_t clear;
|
||||
DRM_DEBUG( "%s\n", __FUNCTION__ );
|
||||
|
||||
if ( !_DRM_LOCK_IS_HELD( dev->lock.hw_lock->lock ) ||
|
||||
dev->lock.pid != current->pid ) {
|
||||
DRM_ERROR( "r128_cce_clear called without lock held\n" );
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if ( copy_from_user( &clear, (drm_r128_clear_t *) arg,
|
||||
sizeof(clear) ) )
|
||||
return -EFAULT;
|
||||
|
||||
if ( sarea_priv->nbox > R128_NR_SAREA_CLIPRECTS )
|
||||
sarea_priv->nbox = R128_NR_SAREA_CLIPRECTS;
|
||||
|
||||
r128_cce_dispatch_clear( dev, clear.flags,
|
||||
clear.x, clear.y, clear.w, clear.h,
|
||||
clear.clear_color, clear.clear_depth,
|
||||
clear.color_mask, clear.depth_mask );
|
||||
|
||||
/* Make sure we restore the 3D state next time.
|
||||
*/
|
||||
dev_priv->sarea_priv->dirty |= R128_UPLOAD_CONTEXT | R128_UPLOAD_MASKS;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int r128_cce_swap( struct inode *inode, struct file *filp,
|
||||
unsigned int cmd, unsigned long arg )
|
||||
{
|
||||
drm_file_t *priv = filp->private_data;
|
||||
drm_device_t *dev = priv->dev;
|
||||
drm_r128_private_t *dev_priv = dev->dev_private;
|
||||
drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
|
||||
DRM_DEBUG( "%s\n", __FUNCTION__ );
|
||||
|
||||
if ( !_DRM_LOCK_IS_HELD( dev->lock.hw_lock->lock ) ||
|
||||
dev->lock.pid != current->pid ) {
|
||||
DRM_ERROR( "r128_cce_swap called without lock held\n" );
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if ( sarea_priv->nbox > R128_NR_SAREA_CLIPRECTS )
|
||||
sarea_priv->nbox = R128_NR_SAREA_CLIPRECTS;
|
||||
|
||||
r128_cce_dispatch_swap( dev );
|
||||
|
||||
/* Make sure we restore the 3D state next time.
|
||||
*/
|
||||
dev_priv->sarea_priv->dirty |= R128_UPLOAD_CONTEXT | R128_UPLOAD_MASKS;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int r128_cce_vertex( struct inode *inode, struct file *filp,
|
||||
unsigned int cmd, unsigned long arg )
|
||||
{
|
||||
|
|
|
|||
|
|
@ -11,11 +11,11 @@
|
|||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
*
|
||||
* The above copyright notice and this permission notice (including the next
|
||||
* paragraph) shall be included in all copies or substantial portions of the
|
||||
* Software.
|
||||
*
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
|
|
@ -23,7 +23,7 @@
|
|||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
*
|
||||
* Authors:
|
||||
* Rickard E. (Rik) Faith <faith@valinux.com>
|
||||
*
|
||||
|
|
@ -357,11 +357,15 @@ typedef struct drm_agp_info {
|
|||
#define DRM_IOCTL_I810_DOCOPY DRM_IO ( 0x48)
|
||||
|
||||
/* Rage 128 specific ioctls */
|
||||
#define DRM_IOCTL_R128_INIT DRM_IOW( 0x40, drm_r128_init_t)
|
||||
#define DRM_IOCTL_R128_RESET DRM_IO( 0x41)
|
||||
#define DRM_IOCTL_R128_FLUSH DRM_IO( 0x42)
|
||||
#define DRM_IOCTL_R128_IDLE DRM_IO( 0x43)
|
||||
#define DRM_IOCTL_R128_PACKET DRM_IOW( 0x44, drm_r128_packet_t)
|
||||
#define DRM_IOCTL_R128_VERTEX DRM_IOW( 0x45, drm_r128_vertex_t)
|
||||
#define DRM_IOCTL_R128_INIT DRM_IOW( 0x40, drm_r128_init_t)
|
||||
#define DRM_IOCTL_R128_CCE_START DRM_IO( 0x41)
|
||||
#define DRM_IOCTL_R128_CCE_STOP DRM_IO( 0x42)
|
||||
#define DRM_IOCTL_R128_CCE_RESET DRM_IO( 0x43)
|
||||
#define DRM_IOCTL_R128_CCE_IDLE DRM_IO( 0x44)
|
||||
#define DRM_IOCTL_R128_RESET DRM_IO( 0x45)
|
||||
#define DRM_IOCTL_R128_SWAP DRM_IO( 0x46)
|
||||
#define DRM_IOCTL_R128_CLEAR DRM_IOW( 0x47, drm_r128_clear_t)
|
||||
#define DRM_IOCTL_R128_VERTEX DRM_IOWR(0x48, drm_r128_vertex_t)
|
||||
#define DRM_IOCTL_R128_PACKET DRM_IOWR(0x49, drm_r128_packet_t)
|
||||
|
||||
#endif
|
||||
|
|
|
|||
22
shared/drm.h
22
shared/drm.h
|
|
@ -11,11 +11,11 @@
|
|||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
*
|
||||
* The above copyright notice and this permission notice (including the next
|
||||
* paragraph) shall be included in all copies or substantial portions of the
|
||||
* Software.
|
||||
*
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
|
|
@ -23,7 +23,7 @@
|
|||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
*
|
||||
* Authors:
|
||||
* Rickard E. (Rik) Faith <faith@valinux.com>
|
||||
*
|
||||
|
|
@ -357,11 +357,15 @@ typedef struct drm_agp_info {
|
|||
#define DRM_IOCTL_I810_DOCOPY DRM_IO ( 0x48)
|
||||
|
||||
/* Rage 128 specific ioctls */
|
||||
#define DRM_IOCTL_R128_INIT DRM_IOW( 0x40, drm_r128_init_t)
|
||||
#define DRM_IOCTL_R128_RESET DRM_IO( 0x41)
|
||||
#define DRM_IOCTL_R128_FLUSH DRM_IO( 0x42)
|
||||
#define DRM_IOCTL_R128_IDLE DRM_IO( 0x43)
|
||||
#define DRM_IOCTL_R128_PACKET DRM_IOW( 0x44, drm_r128_packet_t)
|
||||
#define DRM_IOCTL_R128_VERTEX DRM_IOW( 0x45, drm_r128_vertex_t)
|
||||
#define DRM_IOCTL_R128_INIT DRM_IOW( 0x40, drm_r128_init_t)
|
||||
#define DRM_IOCTL_R128_CCE_START DRM_IO( 0x41)
|
||||
#define DRM_IOCTL_R128_CCE_STOP DRM_IO( 0x42)
|
||||
#define DRM_IOCTL_R128_CCE_RESET DRM_IO( 0x43)
|
||||
#define DRM_IOCTL_R128_CCE_IDLE DRM_IO( 0x44)
|
||||
#define DRM_IOCTL_R128_RESET DRM_IO( 0x45)
|
||||
#define DRM_IOCTL_R128_SWAP DRM_IO( 0x46)
|
||||
#define DRM_IOCTL_R128_CLEAR DRM_IOW( 0x47, drm_r128_clear_t)
|
||||
#define DRM_IOCTL_R128_VERTEX DRM_IOWR(0x48, drm_r128_vertex_t)
|
||||
#define DRM_IOCTL_R128_PACKET DRM_IOWR(0x49, drm_r128_packet_t)
|
||||
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue